Write command retransmission protection method of battery management system

Abstract

The invention relates to a battery management system, in particular to a write command retransmission protection method of a battery management system, which can hide a time interval between a write command error and write data, retransmit a write command and write data by using a battery sampling chip AFE, effectively reduce the task load of an MCU (Microprogrammed Control Unit) and improve the reliability of the battery management system. Meanwhile, the MCU can more quickly receive error information generated when the device is configured, and the MCU can more flexibly select a processing scheme for configuration errors, so that the communication cost caused by write command errors is greatly reduced; according to the technical scheme provided by the invention, the defect that communication time and cost are remarkably increased due to write command errors in the prior art can be effectively overcome.

Description

Technical Field

[0001] The invention relates to a battery management system, and in particular to a write command retransmission protection method for the battery management system. Background Art

[0002] At present, most battery management systems use a daisy chain structure. Affected by the transmission speed and structure, the write command takes a long time to transmit on the chain. After the write command fails to transmit on the chain, the device on the chain cannot actively feedback the error to the MCU. The MCU needs to send a read status register command to the device to query the current status of the device on the chain in order to obtain the write command error fault. As a result, the write command error causes a significant increase in communication time and cost. Summary of the invention

[0003] 1. Technical issues to be resolved

[0004] In view of the above shortcomings of the prior art, the present invention provides a write command retransmission protection method for a battery management system, which can effectively overcome the defect of the prior art that write command errors cause a significant increase in communication time and cost.

[0005] (II) Technical solution

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0007] A write command retransmission protection method for a battery management system comprises the following steps:

[0008] S1. MCU sends a write command and a write command check code. All devices on the daisy chain directly forward the write command and the write command check code to the next device, and send a write command check correct code or a write command check error code to the upper device. Meanwhile, the device that has no write command check error and receives a write command check code with a valid bit of 1 receives and stores the write command check correct code or the write command check error code of the next device; the device that has a write command check error or receives a write command check code with a valid bit of 0 receives but does not store the write command check correct code or the write command check error code of the next device.

[0009] S2, MCU sends the write data and write data check code of the first-level device, the first-level device returns the write data check correct code to the MCU, and the first-level device completes the write operation; the first device that receives the write command check error code of the next-level device resends the write command and write command check code to the next-level device;

[0010] S3, MCU sends the write data and write data check code of the second-level device. The device that completes the write operation and has not registered the write command check error code sent by the lower-level device directly forwards the write data and write data check code of the second-level device, and the second-level device completes the write operation; the first device that receives the write command check error code of the next-level device resends the write command and write command check code to the next-level device;

[0011] S4, MCU sends the write data and write data verification code of the third-level device, and the device that completes the write operation and has not registered the write command verification error code sent by the lower-level device directly forwards the write data and write data verification code of the third-level device; the device that completes the write operation, registers the write command verification error code of the lower-level device and has not registered the write data and write data verification code of the lower-level device receives, registers and forwards the write data and write data verification code of the third-level device; the device that first receives the write command verification error code of the next-level device resends the write command and write command verification code to the next-level device;

[0012] S5, MCU sends the write data and write data verification code of the fourth-level device, the device that completes the write operation and has not registered the write command verification error code sent by the lower-level device directly forwards the write data and write data verification code of the fourth-level device; the device that completes the write operation, registers the write command verification error code of the lower-level device, and has not registered the write data and write data verification code of the lower-level device receives, registers and forwards the write data and write data verification code of the fourth-level device; the device that completes the write operation, registers the write command verification error code of the lower-level device, and has registered the write data and write data verification code of the lower-level device does not register the write data and write data verification code of the fourth-level device; the device that first receives the write command verification error code of the next-level device resends the write command and the write command verification code to the next-level device;

[0013] S6. After receiving the write command verification error code returned by the first-level device, the MCU cyclically sends the write data and write data verification code of the fifth-level device to the first-level device. The device that completes the write operation, registers the write command verification error code of the lower-level device, and has registered the write data and write data verification code of the lower-level device cyclically sends the stored write data and write data verification code of the lower-level device to the lower-level device; the first device that receives the write command verification error code of the lower-level device resends the write command and the write command verification code to the lower-level device; if the write command verification of the lower-level device is correct, the lower-level device returns the write command verification correct code to the resending device, and the lower-level device directly forwards the received write command and write command verification code to its lower-level device, and at the same time, the lower-level device receives the write command verification correct code returned by its lower-level device;

[0014] S7. After receiving the write command verification error code returned by the first-level device, the MCU cyclically sends the write data and write data verification code of the fifth-level device to the first-level device. The device that completes the write operation and has stored the write data and write data verification code of the lower-level device cyclically sends the stored write data and write data verification code of the lower-level device to the lower-level device until receiving the write data verification correct code returned by the lower-level device.

[0015] S8. The MCU cyclically sends the write data and write data verification code of the fifth-level device to the first-level device before receiving the write data verification code of the device with the write command verification error returned by the first-level device. The device that completes the write operation and has stored the write data and write data verification code of the lower-level device cyclically sends the stored write data and write data verification code of the lower-level device to the lower-level device until receiving the write data verification code returned by the lower-level device.

[0016] S9. When the MCU receives the write data verification correct code returned by the first-level device from the last-level device, it sends a write completion mark to the first-level device to complete the daisy chain write operation.

[0017] Preferably, in S1, the device on the daisy chain that has a write command verification error abandons the received write command and write command verification code, and at the same time modifies the valid bit in the write command verification code forwarded to the next device to 0, so that the write command verification code forwarded to the next device becomes invalid, and can continue to receive write commands and write command verification codes subsequently; the device that receives an invalid write command verification code abandons the write command and write command verification code, and can continue to receive write commands and write command verification codes subsequently.

[0018] Preferably, the write command includes CMD1 and CMD2, which are 16 bits in total; the write command check code includes CFEC1 and CFEC2, which are 16 bits in total;

[0019] The write command check code is followed by the write data and write data check code of the first-level device. The write data of the first-level device includes DATA1-1, DATA2-1, DATA3-1, DATA4-1, DATA5-1, and DATA6-1, which are 48 bits in total. The write data check code of the first-level device includes DFEC1-1 and DFEC2-1, which are 16 bits in total.

[0020] The write data and write data check codes of the devices at all levels are cascaded after the write data check code of the first-level device;

[0021] Among them, the format of the write command check code CFEC and the write data check code DFEC is the same, both of which include two parts, FEC1 and FEC2. FEC1 is the high 8 bits, and FEC2 is the low 8 bits. The high 7 bits of FEC1 and FEC2 are 15-bit check codes calculated according to the write command or write data. The low 1 bit of FEC2 is the valid bit of the check code. The valid bit is 1, which means the check code is valid, and the valid bit is 0, which means the check code is invalid.

[0022] Preferably, the MCU and the devices at each level are connected in sequence to form a daisy chain architecture, the MCU communicates with the first-level device via SPI, and the devices at each level communicate with each other via isoSPI.

[0023] (III) Beneficial effects

[0024] Compared with the prior art, the present invention provides a write command retransmission protection method for a battery management system. The technical solution of the present application can hide the time interval between a write command error and write data, and the battery sampling chip AFE is used to resend write commands and write data, which can effectively reduce the task load of the MCU. At the same time, the MCU can receive error information that occurs when configuring the device more quickly. For configuration errors, the MCU can more flexibly select a processing solution, thereby greatly reducing the communication cost caused by write command errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 is a schematic diagram of step S1 in the present invention;

[0027] Figure 2 is a schematic diagram of step S2 in the present invention;

[0028] Figure 3 is a schematic diagram of step S3 in the present invention;

[0029] Figure 4 is a schematic diagram of step S4 in the present invention;

[0030] Figure 5 is a schematic diagram of step S5 in the present invention;

[0031] Figure 6 is a schematic diagram of step S6 in the present invention;

[0032] Figure 7is a schematic diagram of step S7 in the present invention;

[0033] Figure 8 is a schematic diagram of step S8 in the present invention;

[0034] Fig. 9 is a schematic diagram of step S9 in the present invention;

[0035] Fig.10 This is a schematic diagram of the data frame format written on the daisy chain in the present invention;

[0036] Fig.11 For the present invention Fig.10 Schematic diagram of the format of the write command check code CFEC and the write data check code DFEC. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] A write command retransmission protection method for a battery management system, such as Figure 1 As shown, S1 and MCU send write commands and write command verification codes, and all devices on the daisy chain directly forward the write commands and write command verification codes to the next-level device, and send a write command verification correct code or a write command verification error code to the upper-level device. At the same time, the device that has no write command verification error and receives the write command verification code with a valid bit of 1 receives and stores the write command verification correct code or the write command verification error code of the next-level device; the device that has a write command verification error or receives the write command verification code with a valid bit of 0 receives but does not store the write command verification correct code or the write command verification error code of the next-level device.

[0039] Specifically, a device on the daisy chain that has a write command verification error abandons the received write command and write command verification code, and at the same time modifies the valid bit in the write command verification code forwarded to the next device to 0, so that the write command verification code forwarded to the next device becomes invalid, and can continue to receive write commands and write command verification codes subsequently; a device that receives an invalid write command verification code abandons the write command and write command verification code, and can continue to receive write commands and write command verification codes subsequently.

[0040] like Figure 1 As shown, the MCU sends a write command and a valid write command check code (the valid bit of the write command check code is 1);

[0041] AFE1 will forward the received write command sent by MCU directly to AFE2, and for each 1-bit write command received from MCU, AFE1 will return 1-bit 1 to MCU. At the same time, AFE1 will calculate a 15-bit write command check code based on the received write command. After AFE1 receives the write command sent by MCU, a total of 16-bit 1 will be returned to MCU. AFE2 will forward the received write command sent by AFE1 directly to AFE3, and for each 1-bit write command received from AFE1, AFE2 will return 1-bit 1 to AFE1. At the same time, AFE2 will calculate a 15-bit write command check code based on the received write command. After AFE2 receives the write command sent by AFE1, a total of 16-bit 1 will be returned to AFE1. And so on;

[0042] AFE1 will directly forward the first 15-bit write command verification code sent by the MCU to AFE2. At the same time, AFE1 will return 1 bit of 1 to the MCU every time it receives a 1-bit write command verification code sent by the MCU. Therefore, after receiving the 15-bit write command verification code sent by the MCU, AFE1 will return a total of 15 bits of 1 to the MCU. AFE1 compares the received 15-bit write command verification code with the 15-bit write command verification code calculated by AFE1 based on the write command. If the two are equal, the verification is correct. AFE1 will also directly forward the valid bits of the received write command verification code to AFE2, and at the same time, return 1 bit of 1 to the MCU. At this time, AFE1 returns the write command verification correct code 32'hffff to the MCU, and AFE1 stores the AFE2 write command verification correct code. If the write command verification code received by AFE1 is valid, then the write command is valid for AFE1, and AFE1 cannot continue to receive write commands subsequently;

[0043] AFE2 will directly forward the first 15-bit write command check code received from AFE1 to AFE3. At the same time, AFE2 will return 1-bit 1 to AFE1 every time it receives 1-bit write command check code sent by AFE1. Therefore, after receiving the 15-bit write command check code sent by AFE1, AFE2 will return 15-bit 1 to AFE1 cumulatively. AFE2 will compare the received 15-bit write command check code with the 15-bit write command check code calculated by AFE2 according to the write command. If the two are equal, the check is correct. AFE2 will also directly forward the valid bits of the received write command check code to AFE3, and at the same time, return 1-bit 1 to AFE1. At this time, AFE2 returns the write command check correct code 32'hffff to AFE1, and AFE2 stores the AFE3 write command check error code. If the write command check code received by AFE2 is valid, then the write command is valid for AFE2, and AFE2 cannot continue to receive write commands subsequently;

[0044] AFE3 will directly forward the first 15-bit write command check code received from AFE2 to AFE4. At the same time, AFE3 will return 1-bit 1 to AFE2 every time it receives 1-bit write command check code sent by AFE2. Therefore, after receiving the 15-bit write command check code sent by AFE2, AFE3 returns 15-bit 1 to AFE2 cumulatively. AFE3 compares the received 15-bit write command check code with the 15-bit write command check code calculated by AFE3 according to the write command. If the two are not equal, the check is wrong. The valid bit of the write command check code sent by AFE3 to AFE4 is 0, and at the same time, 1-bit 0 is returned to AFE2. At this time, AFE3 returns the write command check error code 32'hfffe to AFE2, and AFE3 does not register the AFE4 write command check error code. If the write command received by AFE3 has a check error, the write command is invalid for AFE3, and AFE3 can continue to receive write commands later;

[0045] Since the valid bit of the write command check code sent by AFE3 received by AFE4 is 0, AFE4 directly forwards it to AFE5. At the same time, every time AFE4 receives a 1-bit write command check code sent by AFE3, it returns a 1-bit AFE4 write command check error code to AFE3. AFE4 does not register the AFE5 write command check error code. If the valid bit of the write command check code received by AFE4 is 0, the write command is invalid for AFE4, and AFE4 can continue to receive write commands later;

[0046] Since the valid bit of the write command check code sent by AFE4 received by AFE5 is 0, AFE5 will directly forward it. At the same time, every time AFE5 receives a 1-bit write command check code sent by AFE4, it will return a 1-bit AFE5 write command check error code to AFE4. If the valid bit of the write command check code received by AFE5 is 0, the write command is invalid for AFE5, and AFE5 can continue to receive write commands.

[0047] like Figure 2 As shown, S2, MCU sends the write data and write data verification code of the first-level device, the first-level device returns the write data verification correct code to the MCU, and the first-level device completes the write operation; the first device that receives the write command verification error code of the next-level device resends the write command and write command verification code to the next-level device.

[0048] like Figure 2 As shown, MCU sends the write data and write data check code of AFE1;

[0049] Each time AFE1 receives 1-bit write data or write data check code sent by MCU, it returns 1-bit 1 to MCU. After receiving AFE1 write data and write data check code sent by MCU, AFE1 completes the write operation and returns the write data check correct code of AFE1 to MCU, which is 64'hffffffff.

[0050] After receiving the AFE3 write command verification error code 32'hfffe, AFE2 will resend the write command and write command verification code to AFE3, and at the same time receive and register the AFE3 write command verification error code sent by AFE3;

[0051] The operations of AFE3, AFE4 and AFE5 are the same as those in the first step.

[0052] like Figure 3 As shown, S3, MCU sends the write data and write data verification code of the second-level device. The device that completes the write operation and has not registered the write command verification error code sent by the lower-level device directly forwards the write data and write data verification code of the second-level device, and the second-level device completes the write operation; the first device that receives the write command verification error code from the next-level device resends the write command and write command verification code to the next-level device.

[0053] like Figure 3 As shown, MCU sends the write data and write data check code of AFE2;

[0054] AFE1 forwards the AFE2 write data and write data check code sent by the MCU. At the same time, for each 1-bit write data or write data check code received from the MCU, it returns 1-bit 1 to the MCU. AFE1 receives and stores the AFE2 write data check correct code sent by AFE2. After receiving and forwarding the AFE2 write data and write data check code sent by the MCU, AFE1 returns the AFE2 write command check correct code 64'hffffffff to the MCU. The AFE2 write command check code is the AFE2 write command check correct code stored by AFE1 in the first step.

[0055] AFE2 receives the AFE2 write data and write data check code sent by AFE1. At the same time, every time it receives 1 bit of write data or write data check code sent by AFE1, it returns 1 bit of 1 to AFE1. AFE2 receives and stores the AFE3 write command check error code sent by AFE3, and resends the write command and write command check code to AFE3. After receiving the AFE2 write data and write data check code sent by AFE1, AFE2 completes the AFE2 write operation. The cumulative write data check correct code returned by AFE2 to AFE1 is 64'hffffffff;

[0056] The operations of AFE3, AFE4 and AFE5 are the same as those in the first step.

[0057] like Figure 4 As shown, S4, MCU sends the write data and write data verification code of the third-level device, and the device that completes the write operation and has not registered the write command verification error code sent by the lower-level device directly forwards the write data and write data verification code of the third-level device; the device that completes the write operation, registers the write command verification error code of the lower-level device and has not registered the write data and write data verification code of the lower-level device receives, registers and forwards the write data and write data verification code of the third-level device; the first device that receives the write command verification error code of the next-level device resends the write command and the write command verification code to the next-level device.

[0058] like Figure 4 As shown, MCU sends the write data and write data check code of AFE3;

[0059] AFE1 completes the write operation, and forwards the AFE3 write data and write data check code sent by the MCU before receiving the AFE3 write command check error code sent by AFE2. At the same time, for each 1-bit write data or write data check code received from the MCU, 1-bit 1 is returned to the MCU. AFE1 receives and registers the AFE3 write command check error code sent by AFE2. After receiving and forwarding the AFE3 write data and write data check code sent by the MCU, AFE1 returns the AFE2 write data check correct code 64'hffffffff to the MCU. The AFE2 write data check code is the AFE2 write data check correct code registered by AFE1 in the third step.

[0060] AFE2 completes the write operation, and receives and stores the AFE3 write command check error code sent by AFE3. At this time, AFE2 receives and stores the AFE3 write data and write data check code sent by AFE1. At the same time, for each 1-bit write data or write data check code received from AFE1, a 1-bit AFE3 write command check error code is returned to AFE1. AFE2 receives and stores the AFE3 write command check error code sent by AFE3, and resends the write command and write command check code to AFE3. After receiving the AFE3 write data and write data check code sent by AFE1, AFE2 returns the AFE3 write command check error codes stored by AFE2 to AFE1 in total;

[0061] The operations of AFE3, AFE4 and AFE5 are the same as those in the first step.

[0062] like Figure 5As shown, S5, MCU sends the write data and write data verification code of the fourth-level device, and the device that completes the write operation and has not registered the write command verification error code sent by the lower-level device directly forwards the write data and write data verification code of the fourth-level device; the device that completes the write operation, registers the write command verification error code of the lower-level device, and has not registered the write data and write data verification code of the lower-level device receives, registers and forwards the write data and write data verification code of the fourth-level device; the device that completes the write operation, registers the write command verification error code of the lower-level device and has registered the write data and write data verification code of the lower-level device does not register the write data and write data verification code of the fourth-level device; the device that first receives the write command verification error code of the next-level device resends the write command and the write command verification code to the next-level device.

[0063] like Figure 5 As shown, MCU sends the write data and write data check code of AFE4;

[0064] AFE1 completes the write operation and receives and stores the AFE3 write command verification error code sent by AFE2. At this time, AFE1 receives and stores the AFE4 write data and write data verification code sent by the MCU. At the same time, for each 1-bit write data or write data verification code received from the MCU, a 1-bit AFE3 write command verification error code is returned to the MCU. AFE1 receives and stores the AFE3 write command verification error code sent by AFE2. After receiving, storing and forwarding the AFE4 write data and write data verification code sent by the MCU, AFE1 returns a cumulative write command verification error code of 64'hfffffffe to the MCU for AFE3. The AFE3 write command verification code is the AFE3 write command verification error code stored by AFE1 in the fourth step;

[0065] AFE2 completes the write operation, registers the AFE3 write data and write data check code, and receives and registers the AFE3 write command check error code sent by AFE3. At this time, AFE2 will not forward or register the AFE4 write data and write data check code sent by AFE1. At the same time, for each 1-bit write data or write data check code received from AFE1, a 1-bit AFE3 write command check error code is returned to AFE1. AFE2 receives and registers the AFE3 write command check error code sent by AFE3, and resends the write command and write command check code to AFE3. After receiving the AFE4 write data and write data check code sent by AFE1, AFE2 returns the AFE3 write command check error codes stored by AFE2 to AFE1 in total;

[0066] The operations of AFE3, AFE4 and AFE5 are the same as those in the first step.

[0067] like Figure 6As shown, S6, after the MCU receives the write command verification error code returned by the first-level device, it cyclically sends the write data and write data verification code of the fifth-level device to the first-level device, and the device that completes the write operation, registers the write command verification error code of the lower-level device and has registered the write data and write data verification code of the lower-level device cyclically sends the stored write data and write data verification code of the lower-level device to the lower-level device; the first device that receives the write command verification error code of the lower-level device resends the write command and the write command verification code to the next-level device; if the write command verification of the next-level device is correct, the next-level device returns a write command verification correct code to the resending device, and the next-level device directly forwards the received write command and write command verification code to its next-level device, and at the same time, the next-level device receives the write command verification correct code returned by its next-level device.

[0068] like Figure 6 As shown, MCU cyclically sends the write data and write data check code of AFE5;

[0069] AFE1 sends the stored AFE4 write data and write data check code to AFE2 cyclically, and each time it receives 1-bit AFE5 write data or write data check code sent by MCU, AFE1 returns 1-bit AFE3 write command check error code to MCU. After receiving the AFE5 write data and write data check code sent by MCU, AFE1 returns the AFE3 write command check error code stored by AFE1 to MCU cumulatively. At the same time, AFE1 receives and stores the AFE3 write command check error code sent by AFE2;

[0070] AFE2 resends the write command and write command check code to AFE3, and receives and stores the AFE3 write command check correct code sent by AFE3. At the same time, for each 1-bit write data or write data check code sent by AFE1, AFE2 returns a 1-bit AFE3 write command check error code to AFE1. After receiving the AFE4 write data and write data check code sent by AFE1, AFE2 returns the AFE3 write command check error codes stored by AFE2 to AFE1 cumulatively. If AFE2 receives the write command check code returned by AFE3, and has not received the AFE4 write data and write data check code sent by AFE1 at this time, AFE2 will stop sending any data or commands to AFE3 until AFE2 receives the AFE4 write data and write data check code sent by AFE1;

[0071] AFE3 will directly forward the first 15-bit write command received from AFE2 to AFE4. AFE3 will directly forward the first 15-bit write command check code received from AFE2 to AFE4. At the same time, AFE3 will return 1-bit 1 to AFE2 every time it receives 1-bit write command check code sent by AFE2. Therefore, after receiving the 15-bit write command check code sent by AFE2, AFE3 returns 15-bit 1 to AFE2 cumulatively. AFE3 compares the received 15-bit write command check code with the 15-bit write command check code calculated by AFE3 according to the write command. If the two are equal, the check is correct. AFE3 will also directly forward the valid bits of the received write command check code to AFE4, and at the same time, return 1-bit 1 to AFE2. At this time, AFE3 returns the write command check correct code 32'hffff to AFE2, and AFE3 registers the AFE4 write command check correct code. If the write command check code received by AFE3 is valid, the write command is valid for AFE3, and AFE3 cannot continue to receive write commands subsequently;

[0072] The operation process of AFE4 and AFE5 is the same as that of AFE3.

[0073] like Figure 7 As shown, after S7 and MCU receive the write command verification error code returned by the first-level device, they cyclically send the write data and write data verification code of the fifth-level device to the first-level device. The device that completes the write operation and has stored the write data and write data verification code of the lower-level device cyclically sends the stored write data and write data verification code of the lower-level device to the lower-level device until it receives the write data verification correct code returned by the lower-level device.

[0074] like Figure 7 As shown, MCU cyclically sends the write data and write data check code of AFE5;

[0075] AFE1 sends the stored AFE4 write data and write data check code to AFE2 cyclically, and each time it receives 1-bit AFE5 write data or write data check code sent by MCU, AFE1 returns 1-bit AFE3 write command check error code to MCU. After receiving the AFE5 write data and write data check code sent by MCU, AFE1 returns the AFE3 write command check error code stored by AFE1 to MCU. At the same time, AFE1 receives and stores the AFE3 write command check correct code sent by AFE2;

[0076] When AFE2 has not received the AFE3 write data verification code returned by AFE3, AFE2 sends the stored AFE3 write data and write data verification code to AFE3, and receives the stored AFE3 write data verification code sent by AFE3. At the same time, for each 1-bit write data or write data verification code sent by AFE1, AFE2 returns a 1-bit AFE3 write command verification code to AFE1. After AFE2 receives the AFE4 write data and write data verification code sent by AFE1, it returns the AFE3 write command verification code stored by AFE2 to AFE1 cumulatively. After AFE2 receives the AFE3 write data verification code returned by AFE3, it releases the memory storing the AFE3 write data and write data verification code;

[0077] Each time AFE3 receives 1-bit write data or write data check code sent by AFE2, it returns 1-bit 1 to AFE2. After receiving the AFE3 write data and write data check code sent by AFE2, AFE3 completes the write operation and returns the write data check correct code of AFE3 to AFE2, which is 64'hffffffff.

[0078] AFE4 and AFE5 do not perform any operation.

[0079] like Figure 8 As shown, S8, the MCU cyclically sends the write data and write data verification code of the fifth-level device to the first-level device before receiving the write data verification correct code returned by the first-level device from the device with a write command verification error. The device that completes the write operation and has stored the write data and write data verification code of the lower-level device cyclically sends the stored write data and write data verification code of the lower-level device to the lower-level device until it receives the write data verification correct code returned by the lower-level device.

[0080] like Figure 8 As shown, MCU cyclically sends the write data and write data check code of AFE5;

[0081] When AFE1 has not received the AFE3 write data verification code returned by AFE2, AFE1 cyclically sends the stored AFE4 write data and write data verification code to AFE2, and each time AFE1 receives 1 bit of AFE5 write data or write data verification code sent by MCU, AFE1 returns 1 bit of AFE3 write command verification code to MCU. After AFE1 receives the AFE5 write data and write data verification code sent by MCU, it returns the AFE3 write command verification code stored by AFE1 to MCU. At the same time, AFE1 will receive and store the AFE3 write data verification code sent by AFE2. After AFE1 receives the AFE3 write data verification code returned by AFE2, it will release the memory storing the AFE4 write data and write data verification code;

[0082] AFE2 has received the AFE3 write data check code returned by AFE3. After that, AFE2 directly forwards the AFE4 write data and write data check code sent by AFE1 to AFE3, and receives and stores the AFE4 write command check code returned by AFE3. At the same time, for each 1-bit write data or write data check code sent by AFE1, AFE2 returns 1-bit AFE3 write data check code to AFE1. After receiving the AFE4 write data and write data check code sent by AFE1, AFE2 returns the AFE3 write data check code stored by AFE2 to AFE1 in total;

[0083] Each time AFE3 receives 1-bit write data or write data check code sent by AFE2, it returns 1-bit AFE4 write command check correct code to AFE2. After AFE3 receives AFE4 write data and write data check code sent by AFE2, the cumulative write command check correct code returned to AFE2 is 64'hffffffff;

[0084] Each time AFE4 receives 1-bit write data or write data check code sent by AFE3, it returns 1-bit 1 to AFE3. After receiving the AFE4 write data and write data check code sent by AFE3, AFE4 completes the write operation and returns the write data check correct code of AFE4 to AFE3, which is 64'hffffffff.

[0085] AFE5 does not perform any operation.

[0086] like Fig. 9 As shown, when S9 and MCU receive the write data verification correct code of the last-level device returned by the first-level device, they send a write end mark to the first-level device to complete the daisy chain write operation.

[0087] like Fig. 9 As shown, when the MCU has not received the correct write data verification code of AFE3 returned by AFE1, the MCU sends the write data and write data verification code of AFE5. When the MCU receives the correct write data verification code of AFE3 returned by AFE1, it can send a write end mark to AFE1 to complete the daisy chain write operation, or it can continue to send invalid write commands and write data to receive the correct write data verification codes of AFE4 and AFE5 returned by AFE1. After ensuring that the entire write operation is correct, send a write end mark to AFE1 to complete the daisy chain write operation;

[0088] AFE1 has received the AFE3 write data check code returned by AFE2. After that, AFE1 directly forwards the AFE5 write data and write data check code sent by MCU to AFE2, and receives and stores the AFE4 write command check code returned by AFE2. At the same time, for each 1-bit write data or write data check code received from MCU, AFE1 returns 1-bit AFE3 write data check code to MCU. After receiving the AFE5 write data and write data check code sent by MCU, AFE1 returns the AFE3 write data check code stored by AFE1 to MCU.

[0089] Each time AFE2 receives 1-bit write data or write data check code sent by AFE1, it returns 1-bit AFE4 write command check correct code to AFE1. After AFE2 receives AFE5 write data and write data check code sent by AFE1, the cumulative write command check correct code returned to AFE1 by AFE4 is 64'hffffffff;

[0090] Each time AFE3 receives 1-bit write data or write data check code sent by AFE2, it returns 1-bit AFE4 write data check correct code to AFE2. After AFE3 receives AFE5 write data and write data check code sent by AFE2, the cumulative write data check correct code returned to AFE2 by AFE4 is 64'hffffffff;

[0091] Each time AFE4 receives 1-bit write data or write data check code sent by AFE3, it returns 1-bit AFE5 write command check correct code to AFE3. After AFE4 receives the AFE5 write data and write data check code sent by AFE3, the cumulative write command check correct code returned to AFE3 is 64'hffffffff;

[0092] Each time AFE5 receives 1-bit write data or write data check code sent by AFE4, it returns 1-bit 1 to AFE4. After receiving AFE5 write data and write data check code sent by AFE4, AFE5 completes the write operation and returns the write data check correct code of AFE5 to AFE4, which is 64'hffffffff.

[0093] In the technical solution of this application, Fig.10 As shown, the write command includes CMD1 and CMD2, which are 16 bits in total; the write command check code includes CFEC1 and CFEC2, which are 16 bits in total;

[0094] The write command check code is followed by the write data and write data check code of the first-level device. The write data of the first-level device includes DATA1-1, DATA2-1, DATA3-1, DATA4-1, DATA5-1, and DATA6-1, totaling 48 bits; the write data check code of the first-level device includes DFEC1-1 and DFEC2-1, totaling 16 bits;

[0095] The write data and write data check codes of the devices at all levels are cascaded after the write data check code of the first level device;

[0096] Among them, Fig.11 As shown, the format of the write command check code CFEC and the write data check code DFEC is the same, both of which include two parts, FEC1 and FEC2. FEC1 is the upper 8 bits, and FEC2 is the lower 8 bits. The upper 7 bits of FEC1 and FEC2 are 15-bit check codes calculated according to the write command or write data. The lower 1 bit of FEC2 is the valid bit of the check code. The valid bit is 1, which means the check code is valid, and the valid bit is 0, which means the check code is invalid.

[0097] In the technical solution of the present application, the MCU and various levels of devices (i.e., various levels of battery sampling chips AFE) are connected in sequence to form a daisy chain architecture. The MCU communicates with the first-level device via SPI, and the various levels of devices communicate with each other via isoSPI.

[0098] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A write command retransmission protection method for a battery management system, characterized in that: The following steps are involved: S1. MCU sends a write command and a write command check code. All devices on the daisy chain directly forward the write command and the write command check code to the next device, and send a write command check correct code or a write command check error code to the upper device. Meanwhile, the device that has no write command check error and receives a write command check code with a valid bit of 1 receives and stores the write command check correct code or the write command check error code of the next device; the device that has a write command check error or receives a write command check code with a valid bit of 0 receives but does not store the write command check correct code or the write command check error code of the next device. S2, MCU sends the write data and write data check code of the first-level device, the first-level device returns the write data check correct code to the MCU, and the first-level device completes the write operation; the first device that receives the write command check error code of the next-level device resends the write command and write command check code to the next-level device; S3, MCU sends the write data and write data check code of the second-level device. The device that completes the write operation and has not registered the write command check error code sent by the lower-level device directly forwards the write data and write data check code of the second-level device, and the second-level device completes the write operation; the first device that receives the write command check error code of the next-level device resends the write command and write command check code to the next-level device; S4, MCU sends the write data and write data verification code of the third-level device, and the device that completes the write operation and has not registered the write command verification error code sent by the lower-level device directly forwards the write data and write data verification code of the third-level device; the device that completes the write operation, registers the write command verification error code of the lower-level device and has not registered the write data and write data verification code of the lower-level device receives, registers and forwards the write data and write data verification code of the third-level device; the device that first receives the write command verification error code of the next-level device resends the write command and write command verification code to the next-level device; S5, MCU sends the write data and write data verification code of the fourth-level device, the device that completes the write operation and has not registered the write command verification error code sent by the lower-level device directly forwards the write data and write data verification code of the fourth-level device; the device that completes the write operation, registers the write command verification error code of the lower-level device, and has not registered the write data and write data verification code of the lower-level device receives, registers and forwards the write data and write data verification code of the fourth-level device; the device that completes the write operation, registers the write command verification error code of the lower-level device, and has registered the write data and write data verification code of the lower-level device does not register the write data and write data verification code of the fourth-level device; the device that first receives the write command verification error code of the next-level device resends the write command and the write command verification code to the next-level device; S6. After receiving the write command verification error code returned by the first-level device, the MCU cyclically sends the write data and write data verification code of the fifth-level device to the first-level device. The device that completes the write operation, registers the write command verification error code of the lower-level device, and has registered the write data and write data verification code of the lower-level device cyclically sends the stored write data and write data verification code of the lower-level device to the lower-level device; the first device that receives the write command verification error code of the lower-level device resends the write command and the write command verification code to the lower-level device; if the write command verification of the lower-level device is correct, the lower-level device returns the write command verification correct code to the resending device, and the lower-level device directly forwards the received write command and write command verification code to its lower-level device, and at the same time, the lower-level device receives the write command verification correct code returned by its lower-level device; S7. After receiving the write command verification error code returned by the first-level device, the MCU cyclically sends the write data and write data verification code of the fifth-level device to the first-level device. The device that completes the write operation and has stored the write data and write data verification code of the lower-level device cyclically sends the stored write data and write data verification code of the lower-level device to the lower-level device until receiving the write data verification correct code returned by the lower-level device. S8. The MCU cyclically sends the write data and write data verification code of the fifth-level device to the first-level device before receiving the write data verification code of the device with the write command verification error returned by the first-level device. The device that completes the write operation and has stored the write data and write data verification code of the lower-level device cyclically sends the stored write data and write data verification code of the lower-level device to the lower-level device until receiving the write data verification code returned by the lower-level device. S9. When the MCU receives the write data verification correct code returned by the first-level device from the last-level device, it sends a write completion mark to the first-level device to complete the daisy chain write operation.

2. The write command retransmission protection method of the battery management system according to claim 1, characterized in that: In S1, the device on the daisy chain that has a write command verification error abandons the received write command and write command verification code, and at the same time modifies the valid bit in the write command verification code forwarded to the next device to 0, so that the write command verification code forwarded to the next device becomes invalid, and can continue to receive write commands and write command verification codes subsequently; the device that receives the invalid write command verification code abandons the write command and write command verification code, and can continue to receive write commands and write command verification codes subsequently.

3. The write command retransmission protection method of the battery management system according to claim 1, characterized in that: The write command includes CMD1 and CMD2, which are 16 bits in total; the write command check code includes CFEC1 and CFEC2, which are 16 bits in total; The write command check code is followed by the write data and write data check code of the first-level device. The write data of the first-level device includes DATA1-1, DATA2-1, DATA3-1, DATA4-1, DATA5-1, and DATA6-1, which are 48 bits in total. The write data check code of the first-level device includes DFEC1-1 and DFEC2-1, which are 16 bits in total. The write data and write data check codes of the devices at all levels are cascaded after the write data check code of the first-level device; Among them, the format of the write command check code CFEC and the write data check code DFEC is the same, both of which include two parts, FEC1 and FEC2. FEC1 is the high 8 bits, and FEC2 is the low 8 bits. The high 7 bits of FEC1 and FEC2 are 15-bit check codes calculated according to the write command or write data. The low 1 bit of FEC2 is the valid bit of the check code. The valid bit is 1, which means the check code is valid, and the valid bit is 0, which means the check code is invalid.

4. The write command retransmission protection method of the battery management system according to claim 1, characterized in that: The MCU and the devices at each level are connected in sequence to form a daisy chain architecture. The MCU communicates with the first-level device via SPI, and the devices at each level communicate with each other via isoSPI.

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