Write data retransmission protection method of battery management system

Abstract

The invention relates to a battery management system, in particular to a write data retransmission protection method of a battery management system, which retransmits write data by using a battery sampling chip AFE, can effectively reduce the task load of an MCU, can more quickly receive error information generated when a device is configured at the same time, can more flexibly select a processing scheme for configuration errors, and improves the reliability of the device. Therefore, the communication cost caused by data writing errors is greatly reduced; according to the technical scheme provided by the invention, the defect that communication time and cost are remarkably increased due to data writing errors in the prior art can be effectively overcome.

Description

Technical Field

[0001] The invention relates to a battery management system, and in particular to a write data retransmission protection method for the battery management system. Background Art

[0002] At present, most battery management systems use a daisy chain structure. Affected by the transmission speed and structure, the transmission time of write data on the chain is relatively long. After the write data is transmitted in error, the device on the chain cannot actively feedback the error to the MCU. The MCU needs to send a read status register command to the device to query the current status of the device on the chain in order to obtain the write data error fault. As a result, the write data error causes a significant increase in communication time and cost. Summary of the invention

[0003] 1. Technical issues to be solved

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a write data retransmission protection method for a battery management system, which can effectively overcome the defect of the prior art that write data errors cause a significant increase in communication time and cost.

[0005] (II) Technical solution

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0007] A write data retransmission protection method for a battery management system comprises the following steps:

[0008] S1. MCU sends a write command and a write command check code. All devices on the daisy chain directly forward the write command and the write command check code to the next device, and send a write command check correct code to the previous device. The previous device stores the write command check correct code of the next device.

[0009] S2, MCU sends the write data and write data verification code of the first-level device, the first-level device returns the write data verification correct code to the MCU, and the first-level device completes the write operation;

[0010] S3, MCU sends the write data and write data verification code of the second-level device, the device that completes the write operation directly forwards the write data and write data verification code of the second-level device, and the second-level device completes the write operation;

[0011] S4, MCU sends the write data and write data check code of the third-level device, the device that completes the write operation directly forwards the write data and write data check code of the third-level device, and the device that receives the write data check error code returned by the next-level device receives, forwards and stores the write data and write data check code of the third-level device;

[0012] S5. The MCU sends the write data and write data check code of the fourth-level device. The device that receives the write data check error code returned by the lower-level device receives, forwards and stores the write data and write data check code of the fourth-level device. The device that receives the write data check error code returned by the lower-level device resends the write data and write data check code of the lower-level device.

[0013] S6. The MCU sends the write data and write data check code of the fifth-level device. The device storing the write data and write data check code of the lower-level device resends the write data and write data check code of the lower-level device. The device receiving the write data check error code returned by the lower-level device resends the write data and write data check code of the lower-level device.

[0014] S7. After receiving the write data check error code returned by the first-level device, the MCU retransmits the write data and the write data check code of the fifth-level device. The device storing the write data and the write data check code of the lower-level device retransmits the write data and the write data check code of the lower-level device. The device receiving the write data check error code returned by the next-level device retransmits the write data and the write data check code of the next-level device. When the retransmitting device receives the write data check correct code returned by the next-level device, the memory storing the write data and the write data check code of the next-level device is released.

[0015] S8. After receiving the write data check error code returned by the first-level device, the MCU retransmits the write data and write data check code of the fifth-level device. The device storing the write data and write data check code of the lower-level device retransmits the write data and write data check code of the lower-level device. The device that completes the write operation later directly forwards the write data and write data check code sent by the upper-level device to the lower-level device. When the retransmitting device receives the write data check correct code returned by the lower-level device, the memory storing the write data and write data check code of the lower-level device is released.

[0016] S9. After receiving the write data verification error code returned by the first-level device, the MCU resends the write data and write data verification code of the fifth-level device. The device that completes the write operation subsequently directly forwards the write data and write data verification code sent by the previous-level device to the next-level device. When the MCU receives the write data verification correct code returned by the first-level device, it sends a write end flag to the first-level device to complete the daisy chain write operation.

[0017] Preferably, in S9, when the MCU receives the write data verification correct code returned by the first-level device, it sends a write end mark to the first-level device to complete the daisy chain write operation, including:

[0018] When the MCU receives the write data verification code returned by the first-level device, it sends multiple redundant write data and write data verification codes, so as to send a write end mark to the first-level device after receiving the write data verification code from the last-level device, thereby completing the daisy chain write operation.

[0019] Preferably, the write command includes CMD1 and CMD2, which are 16 bits in total; the write command check code includes CFEC1 and CFEC2, which are 16 bits in total;

[0020] The write command check code is followed by the write data and write data check code of the first-level device. The write data of the first-level device includes DATA1-1, DATA2-1, DATA3-1, DATA4-1, DATA5-1, and DATA6-1, which are 48 bits in total. The write data check code of the first-level device includes DFEC1-1 and DFEC2-1, which are 16 bits in total.

[0021] The write data and write data check codes of the devices at all levels are cascaded after the write data check code of the first-level device;

[0022] Among them, the format of the write command check code CFEC and the write data check code DFEC is the same, both of which include two parts, FEC1 and FEC2. FEC1 is the high 8 bits, and FEC2 is the low 8 bits. The high 7 bits of FEC1 and FEC2 are 15-bit check codes calculated according to the write command or write data. The low 1 bit of FEC2 is the valid bit of the check code. The valid bit is 1, which means the check code is valid, and the valid bit is 0, which means the check code is invalid.

[0023] Preferably, the MCU and the devices at each level are connected in sequence to form a daisy chain architecture, the MCU communicates with the first-level device via SPI, and the devices at each level communicate with each other via isoSPI.

[0024] (III) Beneficial effects

[0025] Compared with the prior art, the present invention provides a write data retransmission protection method for a battery management system, which utilizes the battery sampling chip AFE to resend write data, and can effectively reduce the task load of the MCU. At the same time, the MCU can receive error information that occurs when configuring the device more quickly. For configuration errors, the MCU can more flexibly select a processing solution, thereby greatly reducing the communication cost caused by write data errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 is a schematic diagram of step S1 in the present invention;

[0028] Figure 2 is a schematic diagram of step S2 in the present invention;

[0029] Figure 3 is a schematic diagram of step S3 in the present invention;

[0030] Figure 4 is a schematic diagram of step S4 in the present invention;

[0031] Figure 5 is a schematic diagram of step S5 in the present invention;

[0032] Figure 6 is a schematic diagram of step S6 in the present invention;

[0033] Figure 7 is a schematic diagram of step S7 in the present invention;

[0034] Figure 8 is a schematic diagram of step S8 in the present invention;

[0035] Fig. 9 is a schematic diagram of step S9 in the present invention;

[0036] Fig.10 This is a schematic diagram of the data frame format written on the daisy chain in the present invention;

[0037] Fig.11 For the present invention Fig.10 Schematic diagram of the format of the write command check code CFEC and the write data check code DFEC. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] A write data retransmission protection method for a battery management system, such as Figure 1 As shown, S1 and MCU send write commands and write command verification codes, and each level of devices on the daisy chain directly forwards the write command and write command verification code to the next level device, and sends a write command verification correct code to the upper level device, and the upper level device stores the write command verification correct code of the lower level device.

[0040] like Figure 1 As shown, the MCU sends a write command and a write command verification code, and receives the AFE1 write command verification correct code returned by AFE1;

[0041] AFE1 will directly forward the received write command and write command verification code sent by MCU to AFE2, and AFE1 will return 1bit 1 to MCU for each 1bit write command or write command verification code received from MCU. After AFE1 receives the write command and write verification code sent by MCU, the total AFE1 write command verification code returned to MCU is 32'hffff. At the same time, AFE1 will receive and store the AFE2 write command verification code returned by AFE2;

[0042] AFE2, AFE3, AFE4 and AFE5 operate similarly to AFE1.

[0043] like Figure 2 As shown, S2, MCU sends the write data and write data verification code of the first-level device, the first-level device returns the write data verification correct code to the MCU, and the first-level device completes the write operation.

[0044] like Figure 2 As shown, MCU sends the write data and write data check code of AFE1, and receives the AFE1 write data check correct code returned by AFE1;

[0045] Each time AFE1 receives 1-bit write data or write data check code sent by MCU, it returns 1-bit 1 to MCU. At the same time, AFE1 will calculate a 15-bit write data check code based on the received 48-bit write AFE1 data, and compare it with the calculated write data check code after receiving the first 15-bit write data check code sent by MCU. If the two are equal, the data verification is correct. After AFE1 receives the valid bit of the last 1-bit write data check code sent by MCU, it returns 1-bit 1 to MCU. After receiving the AFE1 write data and write data check code sent by MCU, AFE1 completes the write operation and returns the correct write data check code of AFE1 to MCU, which is 64'hffffffff;

[0046] AFE2, AFE3, AFE4, and AFE5 have no operation.

[0047] like Figure 3 As shown, S3, MCU sends the write data and write data verification code of the second-level device, the device that completes the write operation directly forwards the write data and write data verification code of the second-level device, and the second-level device completes the write operation.

[0048] like Figure 3 As shown, the MCU sends the write data and write data verification code of AFE2, and receives the AFE2 write command verification code returned by AFE1;

[0049] AFE1 has completed the write operation, and will directly forward the AFE2 write data and write data verification code sent by the MCU to AFE2. At the same time, for each 1-bit write data or write data verification code received from the MCU, it will return a 1-bit AFE2 write command verification code to the MCU. After AFE1 receives and forwards the AFE2 write data and write data verification code sent by the MCU, the cumulative AFE2 write command verification code returned to the MCU is 64'hffffffff, which is the AFE2 write command verification code stored by AFE1 in the first step. At the same time, AFE1 will receive and store the AFE2 write data verification code returned by AFE1;

[0050] AFE2 receives the AFE2 write data and write data check code sent by AFE1. At the same time, AFE2 returns 1 bit of 1 to AFE1 for each 1 bit of write data or write data check code sent by AFE1. At the same time, AFE2 calculates a 15 bit write data check code based on the received 48 bit write AFE2 data, and compares it with the calculated write data check code after receiving the first 15 bits of write data check code sent by AFE1. If the two are equal, the data verification is correct. After AFE2 receives the valid bit of the last 1 bit of write data check code sent by AFE1, it returns 1 bit of 1 to AFE1. After receiving the AFE2 write data and write data check code sent by AFE1, AFE2 completes the AFE2 write operation. The cumulative write data check correct code returned by AFE2 to AFE1 is 64'hffffffff;

[0051] AFE3, AFE4, and AFE5 do not have any operation.

[0052] like Figure 4 As shown, S4, MCU sends the write data and write data verification code of the third-level device, the device that completes the write operation directly forwards the write data and write data verification code of the third-level device, and the device that receives the write data verification error code returned by the next-level device receives, forwards and stores the write data and write data verification code of the third-level device.

[0053] like Figure 4 As shown, the MCU sends the write data and write data check code of AFE3, and receives the write data check correct code of AFE2 returned by AFE1;

[0054] AFE1 has completed the write operation, and will directly forward the AFE3 write data and write data check code sent by the MCU to AFE2. At the same time, for each 1-bit write data or write data check code received from the MCU, it will return a 1-bit AFE2 write data check correct code to the MCU. After AFE1 receives and forwards the AFE2 write data and write data check code sent by the MCU, the cumulative AFE2 write data check correct code returned to the MCU is 64'hffffffff, which is the AFE2 write data check correct code stored by AFE1 in the third step. At the same time, AFE1 receives and stores the AFE3 write command check correct code returned by AFE2;

[0055] AFE2 has completed the write operation, and will directly forward the AFE3 write data and write data check code sent by AFE1 to AFE3. At the same time, for each 1-bit write data or write data check code received from AFE1, AFE2 returns a 1-bit AFE3 write command check code to AFE1. After AFE2 receives and forwards the AFE3 write data and write data check code sent by AFE1, the cumulative write command check code returned to AFE1 for AFE3 is 64'hffffffff, which is the AFE3 write command check code stored by AFE2 in the first step. At the same time, AFE2 receives and stores the AFE3 write data check error code returned by AFE3, and stores the AFE3 write data and write data check code after receiving the AFE3 write data check error code;

[0056] AFE3 receives AFE3 write data and write data check code sent by AFE2. At the same time, for each 1-bit write data or write data check code received from AFE2, AFE3 returns 1-bit 1 to AFE2. AFE3 will calculate a 15-bit write data check code based on the received 48-bit write data, and compare it with the calculated 15-bit write data check code after receiving the first 15-bit write data check code sent by AFE2. If the two are not equal, the data check error occurs. After AFE3 receives the valid bit of the last 1-bit write data check code sent by AFE2, it returns 1-bit 0 to AFE2. Data check error, AFE3 write operation is not completed, and the cumulative write data check error code returned by AFE3 to AFE2 is 64'hfffffffe;

[0057] AFE4 and AFE5 do not have any operation.

[0058] like Figure 5As shown, S5, MCU sends the write data and write data verification code of the fourth-level device, the device that receives the write data verification error code returned by the lower-level device receives, forwards and stores the write data and write data verification code of the fourth-level device, and the device that receives the write data verification error code returned by the next-level device resends the write data and write data verification code of the next-level device.

[0059] like Figure 5 As shown, the MCU sends the write data and write data verification code of AFE4, and receives the AFE3 write command verification code returned by AFE1;

[0060] AFE1 has completed the write operation, and will directly forward the AFE4 write data and write data check code sent by the MCU to AFE2. At the same time, for each 1-bit write data or write data check code received from the MCU, it will return a 1-bit AFE3 write command check code to the MCU. After AFE1 receives and forwards the AFE4 write data and write data check code sent by the MCU, the cumulative write command check code returned to the MCU for AFE3 is 64'hffffffff, which is the AFE3 write command check code stored by AFE1 in the fourth step. At the same time, AFE1 receives and stores the AFE3 write data check error code returned by AFE2, and after receiving the AFE3 write data check error code, it stores the AFE4 write data and write data check code;

[0061] AFE2 has completed the write operation and received the write data check error code from AFE3. It will directly resend the AFE3 write data and write data check code to AFE3. At the same time, for every 1-bit write data or write data check code received from AFE1, it will return a 1-bit AFE3 write data check error code to AFE1. After AFE2 receives the AFE4 write data and write data check code sent by AFE1, the cumulative write data check error code of AFE3 returned to AFE1 is 64'hfffffffe. This AFE3 write data check error code is the AFE3 write data check error code stored by AFE2 in the fourth step. At the same time, AFE2 receives and stores the AFE3 write data check error code returned by AFE3;

[0062] AFE3 receives AFE3 write data and write data check code sent by AFE2. At the same time, for each 1-bit write data or write data check code received from AFE2, AFE3 returns 1-bit 1 to AFE2. AFE3 will calculate a 15-bit write data check code based on the received 48-bit write data, and compare it with the calculated 15-bit write data check code after receiving the first 15-bit write data check code sent by AFE2. If the two are not equal, the data check error occurs. After AFE3 receives the valid bit of the last 1-bit write data check code sent by AFE2, it returns 1-bit 0 to AFE2. Data check error, AFE3 write operation is not completed, and the cumulative write data check error code returned by AFE3 to AFE2 is 64'hfffffffe;

[0063] AFE4 and AFE5 do not have any operation.

[0064] like Figure 6 As shown, S6, MCU sends the write data and write data verification code of the fifth-level device, the device that stores the write data and write data verification code of the lower-level device resends the write data and write data verification code of the lower-level device, and the device that receives the write data verification error code returned by the next-level device resends the write data and write data verification code of the next-level device.

[0065] like Figure 6 As shown, the MCU sends the write data and write data check code of AFE5, and receives the write data check error code of AFE3 returned by AFE1;

[0066] AFE1 has completed the write operation and received the write data check error code of AFE3. It will directly resend AFE4 write data and write data check code to AFE2. At the same time, for each 1-bit write data or write data check code received from MCU, it will return 1-bit AFE3 write data check error code to MCU. After AFE1 receives the AFE5 write data and write data check code sent by MCU, the cumulative write data check error code of AFE3 returned to MCU is 64'hfffffffe. This AFE3 write data check error code is the AFE3 write data check error code stored by AFE1 in the fifth step. At the same time, AFE1 receives and stores the AFE3 write data check error code returned by AFE2;

[0067] AFE2 has completed the write operation and received the write data check error code from AFE3. It will directly resend the AFE3 write data and write data check code to AFE3. At the same time, for every 1-bit write data or write data check code received from AFE1, it will return a 1-bit AFE3 write data check error code to AFE1. After AFE2 receives the AFE4 write data and write data check code sent by AFE1, the cumulative write data check error code of AFE3 returned to AFE1 is 64'hfffffffe. This AFE3 write data check error code is the AFE3 write data check error code stored by AFE2 in the fifth step. At the same time, AFE2 receives and stores the AFE3 write data check error code returned by AFE3;

[0068] AFE3 receives AFE3 write data and write data check code sent by AFE2. At the same time, for each 1-bit write data or write data check code received from AFE2, AFE3 returns 1-bit 1 to AFE2. AFE3 will calculate a 15-bit write data check code based on the received 48-bit write data, and compare it with the calculated 15-bit write data check code after receiving the first 15-bit write data check code sent by AFE2. If the two are not equal, the data check error occurs. After AFE3 receives the valid bit of the last 1-bit write data check code sent by AFE2, it returns 1-bit 0 to AFE2. Data check error, AFE3 write operation is not completed, and the cumulative write data check error code returned by AFE3 to AFE2 is 64'hfffffffe;

[0069] AFE4 and AFE5 do not have any operation.

[0070] like Figure 7 As shown, S7, MCU retransmits the write data and write data verification code of the fifth-level device after receiving the write data verification error code returned by the first-level device, the device storing the write data and write data verification code of the lower-level device retransmits the write data and write data verification code of the lower-level device, the device receiving the write data verification error code returned by the next-level device retransmits the write data and write data verification code of the next-level device, and when the retransmitting device receives the write data verification correct code returned by the next-level device, the memory storing the write data and write data verification code of the next-level device is released.

[0071] like Figure 7 As shown, the MCU sends the write data and write data check code of AFE5, and receives the write data check error code of AFE3 returned by AFE1;

[0072] AFE1 has completed the write operation and received the write data check error code of AFE3. It will directly resend AFE4 write data and write data check code to AFE2. At the same time, for each 1-bit write data or write data check code received from MCU, it will return 1-bit AFE3 write data check error code to MCU. After AFE1 receives the AFE5 write data and write data check code sent by MCU, the cumulative write data check error code of AFE3 returned to MCU is 64'hfffffffe. This AFE3 write data check error code is the AFE3 write data check error code stored by AFE1 in step 6. At the same time, AFE1 receives and stores the AFE3 write data check error code returned by AFE2;

[0073] AFE2 has completed the write operation and has received the write data check error code from AFE3. It will directly resend the AFE3 write data and write data check code to AFE3. At the same time, for every 1-bit write data or write data check code received from AFE1, it will return a 1-bit AFE3 write data check error code to AFE1. After AFE2 has received the AFE4 write data and write data check code sent by AFE1, the cumulative write data check error code returned to AFE1 for AFE3 is 64'hfffffffe. This AFE3 write data check error code is the AFE3 write data check error code stored by AFE2 in the sixth step. At the same time, AFE2 receives and stores the AFE3 write data check correct code returned by AFE3. After receiving the AFE3 write data check correct code, AFE2 releases the memory storing the AFE3 write data and write data check code;

[0074] AFE3 receives the AFE3 write data and write data check code sent by AFE2. At the same time, for each 1-bit write data or write data check code sent by AFE2, AFE3 returns 1-bit 1 to AFE2. AFE3 will calculate a 15-bit write data check code based on the received 48-bit write data, and compare it with the calculated 15-bit write data check code after receiving the first 15-bit write data check code sent by AFE2. If the two are equal, the data verification is correct. After AFE3 receives the valid bit of the last 1-bit write data check code sent by AFE2, it returns 1-bit 1 to AFE2. After receiving the AFE3 write data and write data check code sent by AFE2, AFE3 completes the write operation. The cumulative write data check correct code returned by AFE3 to AFE2 is 64'hffffffff;

[0075] AFE4 and AFE5 do not have any operation.

[0076] like Figure 8As shown, S8, after the MCU receives the write data verification error code returned by the first-level device, it resends the write data and write data verification code of the fifth-level device, the device that stores the write data and write data verification code of the lower-level device resends the write data and write data verification code of the lower-level device, and the device that subsequently completes the write operation directly forwards the write data and write data verification code sent by the upper-level device to the next-level device. When the resending device receives the write data verification correct code returned by the lower-level device, it releases the memory storing the write data and write data verification code of the lower-level device.

[0077] like Figure 8 As shown, the MCU sends the write data and write data check code of AFE5, and receives the write data check error code of AFE3 returned by AFE1;

[0078] AFE1 has completed the write operation and received the write data check error code from AFE3. It will directly resend the AFE4 write data and write data check code to AFE2. At the same time, for each 1-bit write data or write data check code received from the MCU, it will return a 1-bit AFE3 write data check error code to the MCU. After AFE1 receives the AFE5 write data and write data check code sent by the MCU, the cumulative write data check error code returned to the MCU for AFE3 is 64'hfffffffe. The AFE3 write data check error code is the AFE3 write data check error code stored by AFE1 in the seventh step. At the same time, AFE1 receives and stores the AFE3 write data check correct code returned by AFE2. After receiving the AFE3 write data check correct code, AFE1 releases the memory storing the AFE4 write data and write data check code;

[0079] AFE2 has completed the write operation and received the write data check code from AFE3. It will directly forward the AFE4 write data and write data check code to AFE3. At the same time, for each 1-bit write data or write data check code received from AFE1, it will return 1-bit AFE3 write data check code to AFE1. After AFE2 receives the AFE4 write data and write data check code sent by AFE1, the cumulative write data check code returned to AFE1 for AFE3 is 64'hffffffff. This AFE3 write data check code is the AFE3 write data check code stored by AFE2 in the seventh step. At the same time, AFE2 receives and stores the AFE4 write command check code returned by AFE3;

[0080] AFE3 has completed the write operation, and will directly forward the AFE4 write data and write data check code to AFE4. At the same time, for each 1-bit write data or write data check code received from AFE2, AFE3 returns a 1-bit AFE4 write command check correct code to AFE2. After AFE3 receives the AFE4 write data and write data check code sent by AFE2, the cumulative AFE4 write command check correct code returned to AFE2 is 64'hffffffff, which is the AFE4 write command check correct code stored by AFE3 in the first step. At the same time, AFE3 receives and stores the AFE4 write data check correct code returned by AFE4;

[0081] AFE4 receives the AFE4 write data and write data check code sent by AFE3. At the same time, for each 1-bit write data or write data check code sent by AFE3, AFE4 returns 1-bit 1 to AFE3. AFE4 will calculate a 15-bit write data check code based on the received 48-bit write data, and compare it with the calculated 15-bit write data check code after receiving the first 15-bit write data check code sent by AFE3. If the two are equal, the data verification is correct. After AFE4 receives the valid bit of the last 1-bit write data check code sent by AFE3, it returns 1-bit 1 to AFE3. After receiving the AFE4 write data and write data check code sent by AFE3, AFE4 completes the write operation. The cumulative write data check correct code returned by AFE4 to AFE3 is 64'hffffffff;

[0082] AFE5 does not have any operation.

[0083] like Fig. 9 As shown, S9, after the MCU receives the write data verification error code returned by the first-level device, it resends the write data and write data verification code of the fifth-level device. The device that completes the write operation subsequently directly forwards the write data and write data verification code sent by the previous-level device to the next-level device. When the MCU receives the write data verification correct code returned by the first-level device, it sends a write end flag to the first-level device to complete the daisy chain write operation.

[0084] Specifically, when the MCU receives the write data verification code returned by the first-level device, it sends a write end mark to the first-level device to complete the daisy chain write operation, including:

[0085] When the MCU receives the write data verification code returned by the first-level device, it sends multiple redundant write data and write data verification codes, so as to send a write end mark to the first-level device after receiving the write data verification code from the last-level device, thereby completing the daisy chain write operation.

[0086] like Fig. 9As shown, the MCU sends the write data and write data check code of AFE5, receives the write data check correct code of AFE3 returned by AFE1, and after receiving the write data check correct code of AFE3, the write operation can be ended directly, or multiple redundant write data and write data check codes can be sent again, so as to end the write operation after receiving the write data check correct code of AFE5;

[0087] AFE1 has completed the write operation and received the write data check code from AFE3. It will directly forward the AFE5 write data and write data check code to AFE2. At the same time, for each 1-bit write data or write data check code received from the MCU, it will return 1-bit AFE3 write data check code to the MCU. After AFE1 receives the AFE5 write data and write data check code sent by the MCU, the cumulative write data check code returned to the MCU is 64'hffffffff. The AFE3 write data check code is the AFE3 write data check code stored by AFE1 in the eighth step. At the same time, AFE1 receives and stores the AFE4 write command check code returned by AFE2.

[0088] AFE2 has completed the write operation and received the write data verification code from AFE3. It will directly forward the AFE5 write data and write data verification code to AFE3. At the same time, for each 1-bit write data or write data verification code sent by AFE1, it will return a 1-bit AFE4 write command verification code to AFE1. After AFE2 receives the AFE5 write data and write data verification code sent by AFE1, the cumulative write command verification code of AFE4 returned to AFE1 is 64'hffffffff. The AFE4 write command verification code is the AFE4 write command verification code stored by AFE2 in the eighth step. At the same time, AFE2 receives and stores the AFE4 write data verification code returned by AFE3;

[0089] AFE3 has completed the write operation and will directly forward AFE5 write data and write data check code to AFE4. At the same time, for every 1-bit write data or write data check code received from AFE2, AFE3 returns 1-bit AFE4 write data check correct code to AFE2. After AFE3 receives the AFE5 write data and write data check code sent by AFE2, the cumulative write data check correct code returned to AFE2 for AFE4 is 64'hffffffff, which is the AFE4 write data check correct code stored by AFE3 in step 8. At the same time, AFE3 receives and stores the AFE5 write command check correct code returned by AFE4;

[0090] AFE4 has completed the write operation and will directly forward the AFE5 write data and write data check code to AFE5. At the same time, for each 1-bit write data or write data check code received from AFE3, AFE4 returns a 1-bit AFE5 write command check correct code to AFE3. After AFE4 receives the AFE5 write data and write data check code sent by AFE3, the cumulative AFE5 write command check correct code returned to AFE3 is 64'hffffffff, which is the AFE5 write command check correct code stored by AFE4 in the first step. At the same time, AFE4 receives and stores the AFE5 write data check correct code returned by AFE5;

[0091] AFE5 receives the AFE5 write data and write data check code sent by AFE4. At the same time, every time it receives 1 bit of write data or write data check code sent by AFE4, it returns 1 bit of 1 to AFE4. AFE5 will calculate a 15 bit write data check code based on the received 48 bit write data, and compare it with the calculated 15 bit write data check code after receiving the first 15 bit write data check code sent by AFE4. If the two are equal, the data verification is correct. After AFE5 receives the valid bit of the last 1 bit write data check code sent by AFE4, it returns 1 bit of 1 to AFE4. After AFE5 receives the AFE5 write data and write data check code sent by AFE4, the write operation is completed. AFE5 returns the correct write data check code of AFE5 to AFE4, which is 64'hffffffff.

[0092] In the technical solution of this application, if Fig.10 As shown, the write command includes CMD1 and CMD2, which are 16 bits in total; the write command check code includes CFEC1 and CFEC2, which are 16 bits in total;

[0093] The write command check code is followed by the write data and write data check code of the first-level device. The write data of the first-level device includes DATA1-1, DATA2-1, DATA3-1, DATA4-1, DATA5-1, and DATA6-1, totaling 48 bits; the write data check code of the first-level device includes DFEC1-1 and DFEC2-1, totaling 16 bits;

[0094] The write data and write data check codes of the devices at all levels are cascaded after the write data check code of the first level device;

[0095] Among them, Fig.11As shown, the format of the write command check code CFEC and the write data check code DFEC is the same, both of which include two parts, FEC1 and FEC2. FEC1 is the upper 8 bits, and FEC2 is the lower 8 bits. The upper 7 bits of FEC1 and FEC2 are 15-bit check codes calculated according to the write command or write data. The lower 1 bit of FEC2 is the valid bit of the check code. The valid bit is 1, which means the check code is valid, and the valid bit is 0, which means the check code is invalid.

[0096] In the technical solution of the present application, the MCU and various levels of devices (i.e., various levels of battery sampling chips AFE) are connected in sequence to form a daisy chain architecture. The MCU communicates with the first-level device via SPI, and the various levels of devices communicate with each other via isoSPI.

[0097] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A write data retransmission protection method for a battery management system, characterized in that: The following steps are involved: S1. MCU sends a write command and a write command check code. All devices on the daisy chain directly forward the write command and the write command check code to the next device, and send a write command check correct code to the previous device. The previous device stores the write command check correct code of the next device. S2, MCU sends the write data and write data verification code of the first-level device, the first-level device returns the write data verification correct code to the MCU, and the first-level device completes the write operation; S3, MCU sends the write data and write data verification code of the second-level device, the device that completes the write operation directly forwards the write data and write data verification code of the second-level device, and the second-level device completes the write operation; S4, MCU sends the write data and write data check code of the third-level device, the device that completes the write operation directly forwards the write data and write data check code of the third-level device, and the device that receives the write data check error code returned by the next-level device receives, forwards and stores the write data and write data check code of the third-level device; S5. The MCU sends the write data and write data check code of the fourth-level device. The device that receives the write data check error code returned by the lower-level device receives, forwards and stores the write data and write data check code of the fourth-level device. The device that receives the write data check error code returned by the lower-level device resends the write data and write data check code of the lower-level device. S6. The MCU sends the write data and write data check code of the fifth-level device. The device storing the write data and write data check code of the lower-level device resends the write data and write data check code of the lower-level device. The device receiving the write data check error code returned by the lower-level device resends the write data and write data check code of the lower-level device. S7. After receiving the write data check error code returned by the first-level device, the MCU retransmits the write data and the write data check code of the fifth-level device. The device storing the write data and the write data check code of the lower-level device retransmits the write data and the write data check code of the lower-level device. The device receiving the write data check error code returned by the next-level device retransmits the write data and the write data check code of the next-level device. When the retransmitting device receives the write data check correct code returned by the next-level device, the memory storing the write data and the write data check code of the next-level device is released. S8. After receiving the write data check error code returned by the first-level device, the MCU retransmits the write data and write data check code of the fifth-level device. The device storing the write data and write data check code of the lower-level device retransmits the write data and write data check code of the lower-level device. The device that completes the write operation later directly forwards the write data and write data check code sent by the upper-level device to the lower-level device. When the retransmitting device receives the write data check correct code returned by the lower-level device, the memory storing the write data and write data check code of the lower-level device is released. S9. After receiving the write data verification error code returned by the first-level device, the MCU resends the write data and write data verification code of the fifth-level device. The device that completes the write operation subsequently directly forwards the write data and write data verification code sent by the previous-level device to the next-level device. When the MCU receives the write data verification correct code returned by the first-level device, it sends a write end flag to the first-level device to complete the daisy chain write operation.

2. The write data retransmission protection method of the battery management system according to claim 1, characterized in that: In S9, when the MCU receives the write data verification code returned by the first-level device, it sends a write end mark to the first-level device to complete the daisy chain write operation, including: When the MCU receives the write data verification code returned by the first-level device, it sends multiple redundant write data and write data verification codes, so as to send a write end mark to the first-level device after receiving the write data verification code from the last-level device, thereby completing the daisy chain write operation.

3. The write data retransmission protection method of the battery management system according to claim 1, characterized in that: The write command includes CMD1 and CMD2, which are 16 bits in total; the write command check code includes CFEC1 and CFEC2, which are 16 bits in total; The write command check code is followed by the write data and write data check code of the first-level device. The write data of the first-level device includes DATA1-1, DATA2-1, DATA3-1, DATA4-1, DATA5-1, and DATA6-1, which are 48 bits in total. The write data check code of the first-level device includes DFEC1-1 and DFEC2-1, which are 16 bits in total. The write data and write data check codes of the devices at all levels are cascaded after the write data check code of the first-level device; Among them, the format of the write command check code CFEC and the write data check code DFEC is the same, both of which include two parts, FEC1 and FEC2. FEC1 is the high 8 bits, and FEC2 is the low 8 bits. The high 7 bits of FEC1 and FEC2 are 15-bit check codes calculated according to the write command or write data. The low 1 bit of FEC2 is the valid bit of the check code. The valid bit is 1, which means the check code is valid, and the valid bit is 0, which means the check code is invalid.

4. The write data retransmission protection method of the battery management system according to claim 1, characterized in that: The MCU and the devices at each level are connected in sequence to form a daisy chain architecture. The MCU communicates with the first-level device via SPI, and the devices at each level communicate with each other via isoSPI.

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