SPI communication system and SPI communication method

Abstract

The invention relates to an SPI communication system and an SPI communication method.The SPI communication system comprises a master SPI device and a slave SPI device, and the slave SPI device is used for sequentially sending a synchronous data signal and a read data signal based on a read data clock signal under the condition that a read instruction and the read data clock signal of the master SPI device are received, the synchronous data signal comprises reference valid data; the main SPI equipment is used for determining an intermediate sampling point of a read-back data bit according to the sampling sequence of the reference effective data; and receiving effective data in the sampled and received read data signal by using the middle sampling point of the read-back data bit. According to the embodiment of the invention, the problems that the delay is large and the read data sampling debugging is troublesome and difficult due to the change of the delay along with the environment can be solved, the hardware equipment adaptively samples the read-back data, and the communication rate of SPI communication is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to an SPI communication system and an SPI communication method. Background Art

[0002] SPI (Serial Peripheral Interface) is a widely used communication protocol, mainly used for data transmission between microcontrollers and peripheral devices. It is a synchronous, full-duplex, master-slave interface that allows data to be transmitted synchronously on the rising or falling edge of the clock signal, thereby enabling the master device and the slave device to send and receive data at the same time. At present, in the communication between SPI devices, in the master SPI device data reading stage, the master SPI sends a clock signal CLK, the slave SPI receives the clock signal CLK sent by the master, and then sends the read data to the data signal line according to the clock signal CLK beat. The master SPI receives the read data returned by the slave SPI, and a large delay will be generated during this period. Because of these delays, originally at the slave SPI device end, the clock signal CLK and the data signal Dx timing are good (the rising edge of CLK is at the center point of each group of bits Dx), at the master SPI device end, the clock signal CLK and the data signal Dx timing have changed greatly relative to the sending end signal, and there are problems of large read data delay and delay variation, resulting in the SPI master device needing to carefully adjust the sampling point of the readback data to ensure accurate sampling of the readback data and ensure data correctness. Summary of the invention

[0003] According to one aspect of the present disclosure, there is provided an SPI communication system, the SPI communication system comprising a master SPI device and a slave SPI device, wherein:

[0004] The slave SPI device is used to: upon receiving a read instruction and a read data clock signal from the master SPI device, sequentially send a synchronous data signal and a read data signal based on the read data clock signal, wherein the synchronous data signal includes reference valid data;

[0005] The master SPI device is used to:

[0006] Determine an intermediate sampling point of the readback data bit according to a sampling sequence of reference valid data in the synchronous data signal;

[0007] Valid data in the read data signal is received using an intermediate sampling point of the readback data bit.

[0008] In a possible implementation manner, determining the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronous data signal includes:

[0009] Continuously sampling the synchronous data signal using a high-multiple sampling clock to obtain a sampling sequence of the reference valid data, wherein the high-multiple sampling clock is L times the read data clock signal, where L is a positive number;

[0010] The middle sampling point of the readback data bit is determined according to the sampling sequence of the reference valid data.

[0011] In a possible implementation manner, determining the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data includes:

[0012] If the sampling reference point of the reference valid data is taken as point 0, the position of the high-multiple sampling clock of the data bit of the reference valid data sampled for the first time is marked as MIN, and the position of the high-multiple sampling clock of the data bit of the reference valid data sampled for the last time is marked as MAX, then the middle sampling point of the readback data bit is determined to be the (MIN+MAX) / 2th high-multiple sampling clock after the sampling reference point,

[0013] The MIN before the sampling reference point is a negative integer, the MIN at the sampling reference point is 0, the MIN after the sampling reference point is a positive integer, the MAX is a positive integer, and the absolute value of the MAX is greater than the absolute value of the MIN.

[0014] The middle sampling point of all subsequent read-back data bits is the (MIN+MAX) / 2th high-multiple sampling clock after the sampling reference point of each read-back data bit.

[0015] In a possible implementation manner, receiving valid data in the read data signal using the middle sampling point of the readback data bit includes:

[0016] A sampling reference point of each of the read data signals is delayed by (MIN+MAX) / 2 times the sampling clock frequency to sample and receive each of the read-back data at a middle sampling point of each of the read-back data.

[0017] In a possible implementation manner, the master SPI device and the slave SPI device are both chips.

[0018] According to one aspect of the present disclosure, a SPI communication method is provided, the method being applied to an SPI communication system including a master SPI device and a slave SPI device, wherein the method comprises:

[0019] When receiving a read instruction and a read data clock signal from the master SPI device, using the slave SPI device to sequentially send a synchronous data signal and a read data signal based on the read data clock signal, wherein the synchronous data signal includes reference valid data;

[0020] The master SPI device is used to determine the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronous data signal, and the middle sampling point of the readback data bit is used to receive the valid data in the read data signal.

[0021] In a possible implementation manner, determining the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronous data signal includes:

[0022] Continuously sampling the synchronous data signal using a high-multiple sampling clock to obtain a sampling sequence of the reference valid data, wherein the high-multiple sampling clock is L times the read data clock signal, where L is a positive number;

[0023] The middle sampling point of the readback data bit is determined according to the sampling sequence of the reference valid data.

[0024] In a possible implementation manner, determining the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data includes:

[0025] If the sampling reference point of the reference valid data is taken as point 0, the position of the high-multiple sampling clock of the data bit of the reference valid data sampled for the first time is marked as MIN, and the position of the high-multiple sampling clock of the data bit of the reference valid data sampled for the last time is marked as MAX, then the middle sampling point of the readback data bit is determined to be the (MIN+MAX) / 2th high-multiple sampling clock after the sampling reference point,

[0026] The MIN before the sampling reference point is a negative integer, the MIN at the sampling reference point is 0, the MIN after the sampling reference point is a positive integer, the MAX is a positive integer, and the absolute value of the MAX is greater than the absolute value of the MIN.

[0027] The middle sampling point of all subsequent read-back data bits is the (MIN+MAX) / 2th high-multiple sampling clock after the sampling reference point of each read-back data bit.

[0028] In a possible implementation manner, receiving valid data in the read data signal using the middle sampling point of the readback data bit includes:

[0029] A sampling reference point of each of the read data signals is delayed by (MIN+MAX) / 2 times the sampling clock frequency to sample and receive each of the read-back data at a middle sampling point of each of the read-back data.

[0030] In a possible implementation manner, the master SPI device and the slave SPI device are both chips.

[0031] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0032] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

[0033] In the SPI communication system of the embodiment of the present disclosure, when the slave SPI device receives the read instruction and the read data clock signal of the master SPI device, it sequentially sends the synchronous data signal and the read data signal based on the read data clock signal, so that the master SPI device determines the middle sampling point of the read-back data bit according to the sampling sequence of the reference valid data in the synchronous data signal, and uses the middle sampling point of the read-back data bit to receive the valid data in the read data signal, thereby solving the problem of troublesome and difficult debugging of read data sampling caused by large delay and delay changes with the environment. The hardware device can adaptively sample the read-back data. Since no additional debugging is allowed, the debugging time is reduced. The embodiment of the present disclosure can also improve the communication rate of SPI communication.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0036] Figure 1 A block diagram of an SPI communication system according to an embodiment of the present disclosure is shown.

[0037] Figure 2 A timing diagram of a master SPI device write operation according to an embodiment of the present disclosure is shown.

[0038] Figure 3 A timing diagram of a master SPI device read operation in the related art is shown.

[0039] Figure 4 , Figure 5 A timing diagram of a master SPI device read operation according to an embodiment of the present disclosure is shown.

[0040] Figure 6 A flow chart of an SPI communication method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0041] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0042] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0044] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0045] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0046] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0047] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0048] See also Figure 1 , Figure 1 A block diagram of an SPI communication system according to an embodiment of the present disclosure is shown.

[0049] like Figure 1 As shown, the SPI communication system includes a master SPI device and a slave SPI device.

[0050] Exemplarily, SPI devices (including master and slave) may include terminal devices and chips. Exemplarily, terminal devices may be user equipment (UE), mobile devices, user terminals, terminals, handheld devices, computing devices or vehicle-mounted devices, etc. Exemplarily, some examples of terminals are: mobile phones, tablet computers, laptop computers, PDAs, mobile Internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control (Industrial Control), wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids (Smart Grid), wireless terminals in transportation safety (Transportation Safety), wireless terminals in smart cities (Smart City), wireless terminals in smart homes (Smart Home), wireless terminals in Internet of Vehicles, etc. For example, a server may be a local server or a cloud server.

[0051] In one example, the chip or processing component includes but is not limited to a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller having an execution instruction function in an electronic device, and the processor may be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components. Inside the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0052] Exemplarily, SPI communication usually includes a chip select signal line (CS), a clock signal line (CLK), and several data signal lines (Dx). In order to speed up data transmission, the data signal lines are usually 2 (DUAL) or 4 (QUAD), or more. In order to distinguish between read / write, an operation can be divided into a command phase (Command Phase) in the first half and a data phase (DATA Phase) in the second half. In the related art, the command phase is when the master SPI device 10 sends a command (including (read / write) command, address, length, etc.) to the slave SPI device 20. In the write operation data phase, the master SPI device 10 sends write data, and the slave SPI device 20 receives write data. All data signal lines are driven by the master SPI device 10 and never driven. In the read operation data phase, the slave SPI device 20 sends read data, and the master SPI device 10 receives read data, and all data lines are driven by the slave SPI device 20.

[0053] Table 1 shows the signal driving description of the write operation in the related art.

[0054] Table 1

[0055]

[0056] From Table 1, we can see that:

[0057] The master SPI device 10 drives the chip select signal line to send a chip select signal CS, and the slave SPI device 20 receives the chip select signal CS.

[0058] The master SPI device 10 drives the clock signal line to send the clock signal CLK, and the slave SPI device 20 receives the clock signal CLK.

[0059] Write instruction period: the master SPI device 10 drives the data signal line Dx to send a write instruction, and the slave SPI device 20 samples the data signal line Dx to receive the write instruction.

[0060] Data writing period: the master SPI device 10 drives the data signal line Dx to send write data, and the slave SPI device 20 samples the data signal line Dx to receive write data.

[0061] See also Figure 2 , Figure 2 FIG. 1 is a timing diagram of a write operation of the master SPI device 10 according to an embodiment of the present disclosure.

[0062] Depend on Figure 2 It can be seen that in the write operation, whether it is the write instruction period or the write data period, the data signal Dx is sent by the master and received by the slave, the clock signal CLK delay (Delay1) and the data signal Dx delay (Delay2) are the same, and the timing relationship between the clock signal CLK and the data signal Dx remains consistent in the master and slave SPI. For example, the rising edge of the clock signal CLK in the figure is exactly in the middle of each segment of the data signal Dx, which is very convenient for the receiving end to receive data and also very convenient for increasing the SPI communication rate.

[0063] Table 2 shows the signal driving description of the read operation in the related art.

[0064] Table 2

[0065]

[0066] From Table 2, we can see that:

[0067] The master SPI device 10 drives the chip select signal line to send a chip select signal CS, and the slave SPI device 20 receives the chip select signal CS.

[0068] The master SPI device 10 drives the clock signal line to send the clock signal CLK, and the slave SPI device 20 receives the clock signal CLK.

[0069] Read instruction period: the master SPI device 10 drives the data signal line Dx to send a read instruction, and the slave SPI device 20 samples the data signal line Dx to receive the read instruction.

[0070] Read conversion period (Turnaround Phase): the master and slave SPI devices 20 do not drive the data signal line Dx. During the conversion period, the data signal line Dx is driven by the master SPI device 10 and then converted to being driven by the slave SPI device 20. During the conversion period, the master and slave SPI devices 20 do not drive the data signal line Dx at the same time.

[0071] Data reading period: the slave SPI device 20 drives the data signal line Dx to send read data, and the master SPI device 10 samples the data signal line Dx to receive the read data.

[0072] See also Figure 3 , Figure 3 A timing diagram of a read operation of a master SPI device 10 in the related art is shown.

[0073] Depend on Figure 3 It can be seen that in the read operation, during the read instruction period, it is very convenient for the slave SPI device 20 to receive the read instruction. During the data read period, the master SPI device 10 sends out the clock signal CLK, and the slave SPI device 20 receives the clock signal CLK sent by the master (delay Delay1), and then sends out the read data to the data signal line Dx according to the clock signal CLK beat, and the master SPI device 10 receives the read data returned by the slave SPI device 20 (delay Delay2). Because of the existence of these delays, originally at the slave SPI device 20 end, the clock signal CLK and the data signal Dx timing were good (the rising edge of CLK was in the middle of each segment Dx), and at the master SPI device 10 end, the clock signal CLK and the data signal Dx timing changed greatly relative to the sending end, and debugging is required to find the stable middle point of the read data signal for sampling and receiving, to ensure that the received read data is correct.

[0074] In summary, in the related art, the master SPI device 10 drives the clock signal CLK, and the master-slave SPI device 20 switches the driving data signal Dx according to the write / read data direction. The timing of the write operation is very good, but the read operation has the problems of large read data delay and delay variation:

[0075] The delay from the clock signal CLK of the master SPI device 10 to the master SPI receiving the read data Dx is relatively large;

[0076] The delay (Delay3) from the clock signal CLK of the master SPI device 10 to the master SPI receiving read data Dx is the sum of the delay (Delay1) of the master SPI clock signal CLK being transmitted to the slave SPI device 20 and the delay (Delay2) of the data signal Dx being transmitted from the slave SPI device 20 to the master SPI device 10 (Delay3=Delay1+Delay2);

[0077] The delay from the clock signal CLK of the master SPI device 10 to the master SPI device 10 receiving the read data Dx is prone to change. For example, the delay will change significantly with changes in operating conditions such as operating temperature, and the delay will change due to differences in chip internal wiring and board-level routing. Of course, there are various reasons for the delay change, which are not listed here exhaustively.

[0078] In the case of large read data delay and delay variation, in order to receive read data accurately, it is necessary to debug each chip system, support a higher SPI rate as much as possible, and adapt to various change limits (such as high and low temperature), and debugging is cumbersome. It is also necessary to support various change delay limits such as high and low temperatures. In pursuit of the goal of the highest SPI rate (fast data transmission), only one relatively low rate can be selected to adapt to the change limit to ensure the correct reception of data. The configuration setting readback data sampling time point must meet the requirements of correct sampling data with small delay (such as low temperature) and correct sampling data with large delay (such as high temperature). This limits the minimum value of the period (signal width) of a single data signal Dx. If the signal width of the data signal Dx is too narrow, it is difficult to find a data sampling time point that meets the requirements of correct sampling data with small / large delays.

[0079] It can be seen that it is necessary to solve the above-mentioned problems of large read data delay and delay variation, which cause cumbersome debugging and rate limitation, so as to improve the efficiency and accuracy of SPI communication.

[0080] The present disclosure provides an SPI communication system. Figure 1 As shown, the slave SPI device 20 is used to: upon receiving a read instruction and a read data clock signal from the master SPI device 10, sequentially send a synchronous data signal and a read data signal based on the read data clock signal, wherein the synchronous data signal includes reference valid data;

[0081] The master SPI device 10 is used to: determine the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronous data signal; and receive the valid data in the read data signal using the middle sampling point of the readback data bit.

[0082] In the SPI communication system of the embodiment of the present disclosure, when the slave SPI device 20 receives the read instruction and the read data clock signal of the master SPI device 10, it sequentially sends the synchronous data signal and the read data signal based on the read data clock signal, so that the master SPI device 10 determines the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronous data signal, and uses the middle sampling point of the readback data bit to receive the valid data in the read data signal, thereby solving the problem of troublesome and difficult debugging of read data sampling caused by large delay and delay changes with the environment. The hardware device can adaptively sample the readback data. Since no additional debugging is allowed, the debugging time is reduced. The embodiment of the present disclosure can also improve the communication rate of SPI communication.

[0083] The embodiments of the present disclosure do not limit the specific implementation methods of the master SPI device 10 and the slave SPI device 20. For example, the master SPI device 10 and the slave SPI device 20 can both be chips. The SPI communication scheme of the embodiments of the present disclosure is used to implement SPI communication between chips, which can effectively improve the communication efficiency between chips.

[0084] The embodiments of the present disclosure do not limit the specific size of the synchronization data signal and the read data signal. By way of example, the number of bits of the synchronization data signal and each read data signal may be the same or different. For example, it may be one byte, and each byte may include 8 bits. Of course, those skilled in the art may set the specific length of the synchronization data signal and each read data signal according to actual conditions and needs.

[0085] The embodiments of the present disclosure do not limit the specific form of the synchronization data signal. Those skilled in the art can set it according to actual conditions and needs. For example, the reference valid data can be set to "1" and the remaining data can be set to "0". As an example, any bit between sequence numbers 1 to 6 can be set as reference valid data according to the order of the transmitted digits (the first transmitted bit is recorded as sequence number 0, the second is sequence number 1, ..., and the eighth is sequence number 7). For example, the bit corresponding to sequence number 1 is set to reference valid data "1", and the remaining bits are set to "0". Non-reference valid data can be set before and after the reference valid data so that the reference valid data can be distinguished. In this example, "0" is the non-reference valid data. Of course, the embodiments of the present disclosure are introduced with the preferred embodiment that the reference valid data includes 1 bit, but the embodiments of the present disclosure are not limited thereto. In other embodiments, those skilled in the art can set the synchronization data signal to include more than 1 bit of reference valid data according to actual conditions and needs. For example, any continuous number of bits between sequence numbers 0 to 7 can be set as reference valid data, for example, the bits corresponding to sequence numbers 2 to 4 are set to "1".

[0086] It should be understood that the master SPI device 10 and the slave SPI device 20 can be set in advance to understand the communication protocol, that is, the slave SPI device 20 sends synchronization data before sending the read data, and agrees that the reference valid data of the synchronization data is "1" and its sequence number (such as the second bit, which is also the sequence number 1). In this way, the master SPI device 10 first receives the synchronization data, and determines the delay information of the reference valid data based on the sampling reference point of the synchronization data reference valid data sequence number, and determines the middle sampling point of the readback data bit according to the delay information of the reference valid data. Of course, the above introduction is exemplary and should not be regarded as a limitation on the embodiments of the present disclosure. Those skilled in the art can adopt appropriate technical means according to actual conditions and needs to realize the determination of the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronization data signal. For example, in a possible implementation, the determination of the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronization data signal can include:

[0087] Continuously sampling the synchronous data signal using a high-multiple sampling clock to obtain a sampling sequence of reference valid data, wherein the high-multiple sampling clock rate is L times the rate of the read data clock signal, where L is a positive number;

[0088] The middle sampling point of the readback data bit is determined according to the sampling sequence of the reference valid data.

[0089] In this way, the embodiment of the present disclosure uses a high-multiple sampling clock to continuously sample the synchronous data signal to obtain a sampling sequence of reference valid data, and determines the intermediate sampling point of the readback data bit according to the sampling sequence of the reference valid data. It can quickly and accurately determine the intermediate sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronous data signal.

[0090] The embodiment of the present disclosure does not limit the size of L. Those skilled in the art can set it according to actual conditions and needs. L is a positive number. For example, L can be set to 3 times, 3.5 times, 4.3 times, etc., whichever multiples meet the sampling requirements.

[0091] The embodiments of the present disclosure do not limit the specific implementation manner of determining the intermediate sampling point of the readback data bit according to the sampling sequence of the reference valid data. Those skilled in the art may adopt appropriate technical means to implement it according to actual conditions and needs. For example, in a possible implementation manner, determining the intermediate sampling point of the readback data bit according to the sampling sequence of the reference valid data may include:

[0092] Continuously sampling the synchronous data signal using a high-multiple sampling clock to obtain a sampling sequence of the reference valid data, wherein the high-multiple sampling clock is L times the read data clock signal, where L is a positive number;

[0093] The middle sampling point of the readback data bit is determined according to the sampling sequence of the reference valid data.

[0094] Exemplarily, determining the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data may include:

[0095] If the sampling reference point of the reference valid data is taken as point 0, the position of the high-multiple sampling clock of the data bit of the reference valid data sampled for the first time is marked as MIN, and the position of the high-multiple sampling clock of the data bit of the reference valid data sampled for the last time is marked as MAX, then the middle sampling point of the readback data bit is determined to be the (MIN+MAX) / 2th high-multiple sampling clock after the sampling reference point,

[0096] Among them, MIN before the sampling reference point is a negative integer, MIN at the sampling reference point is 0, MIN after the sampling reference point is a positive integer, MAX is a positive integer, and because of the existence of delay, the absolute value of MAX> the absolute value of MIN,

[0097] Because the delays are the same, the middle sampling point of all subsequent read-back data bits is the (MIN+MAX) / 2th high-multiple sampling clock after the sampling reference point of each read-back data bit.

[0098] In a possible implementation manner, receiving valid data in the read data signal using the middle sampling point of the readback data bit includes:

[0099] A sampling reference point of each of the read data signals is delayed by (MIN+MAX) / 2 times the sampling clock frequency to sample and receive each of the read-back data at a middle sampling point of each of the read-back data.

[0100] The embodiments of the present disclosure do not limit the specific setting of the sampling reference point. Those skilled in the art may set it according to relevant technical standards. Among them, the sampling reference point of reference valid data and the sampling reference point of read data signal may be set according to the technical standards of SPI mode (including mode 0, mode 1, mode 2, and mode 3).

[0101] For example, in SPI mode 0, for each bit, the transmitter sends data at the falling edge of CLK, and the receiver samples the data sent by the transmitter at the rising edge of CLK (this CLK rising edge is the sampling reference point).

[0102] Of course, the above description of the sampling reference points is exemplary and should not be regarded as a limitation on the embodiments of the present disclosure.

[0103] Generally, the receiving end requires that the MISO (Master Input Slave Output) returned from the transmitting end should remain stable within the setup time before the rising edge of CLK (sampling reference point) at the receiving end, so that the MISO data can be correctly sampled and received. For example, taking a SPI communication system with a total delay (CLK transmission delay: board-level wiring delay + chip PAD delay + chip internal delay plus MISO transmission delay: chip internal delay + chip PAD delay + board-level wiring delay) of 30ns and a setup time of 10ns as an example, the minimum half-cycle of CLK is 40ns (total delay 30ns + setup time 10ns), and the maximum SPI communication rate that can be supported is 12.5MHz (1 / (40ns+40ns)).

[0104] By using the adaptive method described in this patent to find the intermediate sampling point sampling of the read-back data, instead of the default sampling reference point sampling, the communication rate can be easily improved without manual debugging. Taking the above-mentioned SPI communication system with a total delay of 30ns as an example, the SPI communication rate is 20MHz (CLK half cycle 25ns, full cycle 50ns, which is also the data signal width), the slave SPI device sends data MISO on the falling edge of CLK, and MISO reaches the master SPI device, which is delayed by 30ns relative to the falling edge of CLK of the master SPI device, and the rising edge of CLK of the master SPI device is only 25ns half a cycle after the falling edge of CLK. The receiving end of the master SPI device receives MISO 5ns after the rising edge of CLK (the establishment time - 5ns does not meet the establishment time requirement). MISO is sampled and received directly on the rising edge of CLK (sampling reference point), and the sampled data is incorrect. MISO can be sampled and received by delaying 30ns (5ns + half a cycle of MISO 25ns) after the rising edge of CLK (sampling reference point) to the middle point of the MISO data (the actual sampling point of the delayed sampling, that is, the middle sampling point) (100MHz high-multiple sampling clock is 3), and the sampled data is correct, and there is at least one high-multiple sampling clock cycle before and after the sampling point, and the sampled data remains stable. It can be seen that the method described in this patent improves the communication rate and simplifies the configuration settings.

[0105] The operation of the SPI communication system is described below by way of example.

[0106] See also Figure 4 , Figure 4 A timing diagram of a read operation (with low delay) of the master SPI device 10 according to an embodiment of the present disclosure is shown.

[0107] See also Figure 5 , Figure 5 FIG. 4 is a timing diagram of a read operation (large delay) of the master SPI device 10 according to an embodiment of the present disclosure.

[0108] Exemplarily, assume that the fixed value sequence of the synchronization data signal is: the first entry is 0 (agreed to be non-reference valid data), the second entry is 1 (if the multi-bit data signal can also agree on other non-0 values, agreed to be reference valid data), the third entry is 0, and the signal duration width of each bit is, for example, greater than 3 high-multiple sampling clocks to facilitate sampling and determine the intermediate sampling point. Of course, this is only an exemplary description. The synchronization data signal can be 8 bits, and the fourth to eighth data entries are, for example, all 0 (non-reference valid data).

[0109] For example, Figure 4 , Figure 5 As shown, the master SPI device 10 uses a high-multiple sampling clock (smpclk) to sample synchronous data. In the synchronous data period, the sampling reference point where the reference valid data 1 should be sampled is taken as point 0, the position where the reference valid data 1 is sampled for the first time is marked as MIN (marked as a negative integer before the reference point, marked as 0 on the reference point, and marked as a positive integer after the reference point), and the position where the reference valid data 1 is sampled for the last time is marked as MAX (marked as a positive integer after the reference point), where, due to the existence of delay, the absolute value of MAX> the absolute value of MIN and both are integers; then the middle sampling point of the reference valid data bit to be read back is determined to be the (MIN+MAX) / 2th high-multiple sampling clock point after the sampling reference point of the reference valid data, and because the delay is the same, the middle sampling point of all subsequent read-back data bits is also the (MIN+MAX) / 2th high-multiple sampling clock point ((MIN+MAX) / 2th smpclk) after the sampling reference point of each read-back data bit.

[0110] This means that in this read operation, the master SPI uses the sampling reference point of each readback data, and the delay (MIN+MAX) / 2 smpclk (the (MIN+MAX) / 2 smpclk) is the middle sampling point of each readback data, so each readback data can be stably sampled. The readback data is sampled at the middle sampling point of each readback data, and there is a good setup time and hold time before and after, and the sampled readback data is stable and accurate.

[0111] The following is an illustrative description using different delay situations as examples.

[0112] Figure 4 Example of small delay:

[0113] Taking the sampling reference point of the reference valid data of the synchronous data as point 0, the sequence of the reference valid data sampled is 0000111110000 (corresponding to marked sequence number -5 to marked sequence number -2, marked sequence number -1 to marked sequence number 3, marked sequence number 4 to marked sequence number 7 in sequence); it indicates that four 0s are sampled from sequence number -5 to sequence number -2 (non-reference valid data, not concerned, but non-reference valid data is required to reflect the reference valid data), five 1s are sampled from sequence number -1 to sequence number 3 (reference valid data, mainly focusing on the position and length of the sampling sequence of the reference valid data bits in the synchronous data signal), and four 0s are sampled from sequence number 4 to sequence number 7 (non-reference valid data). It can be seen that the middle sampling point of the reference valid data (1 sequence) is 1=(-1+3) / 2, that is, sequence number 1, which is delayed from the sampling reference point by 1 high-multiple sampling clock (1*T smpclk ), which is exactly the middle sampling point of each read-back data. In this example, MIN=-1, MAX=3.

[0114] Figure 5 Example of large delay:

[0115] Taking the sampling reference point of the reference valid data of the synchronous data as point 0, the sequence of the reference valid data sampled is 0000111110000 (corresponding to marked sequence number 0 to marked sequence number 3, marked sequence number 4 to marked sequence number 8, marked sequence number 9 to marked sequence number 12 in sequence); it indicates that four 0s are sampled from sequence number 0 to sequence number 3 (non-reference valid data, not concerned, but non-reference valid data is required to reflect the reference valid data), five 1s are sampled from sequence number 4 to sequence number 8 (reference valid data, mainly focusing on the position and length of the sampling sequence of the reference valid data bits in the synchronous data signal), and four 0s are sampled from sequence number 9 to sequence number 11 (non-reference valid data). It can be seen that the middle sampling point of the reference valid data (sequence of 1) is 6=(4+8) / 2, that is, sequence number 6, which is 6 high-multiple sampling clocks (6*T smpclk ), which is exactly the middle sampling point of each read-back data. In this example, MIN=4, MAX=8.

[0116] It should be noted that, under the same high-multiple sampling clock, the lower the SPI communication rate (the wider the signal width), the more reference valid data bits in the sampling sequence, and under the same SPI communication rate, the higher the high-multiple sampling clock, the more reference valid data bits in the sampling sequence. The disclosed embodiment does not limit the width of the data signal. For example, the signal width can be at least 3 times the sampling clock period Tsmpclk to avoid interference caused by signal jitter, improve the stability of the system, and facilitate finding the center point.

[0117] Exemplarily, after determining MIN and MAX, the disclosed embodiment can cache MIN and MAX in the storage module respectively for calling. In one example, the storage module may include a computer-readable storage medium, which may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, - but not limited to - an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), static random access memories (SRAM), programmable read-only memories (PROM), portable compact disk read-only memories (CD-ROM), digital versatile disks (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or protruding structures in grooves on which instructions are stored, and any suitable combination of the above. The computer-readable storage medium used herein is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses through a fiber optic cable), or an electrical signal transmitted through wires.

[0118] In the SPI communication system of the disclosed embodiment, for each SPI read operation, before the slave SPI device 20 sends the read data, a fixed-value synchronous data signal is first sent to determine the middle sampling point of the readback data bit. The master SPI device 10 uses the middle sampling point of the readback data bit as a reference, continuously samples the synchronous data containing the fixed-value sequence using a high-multiple sampling clock (smpclk), adaptively determines the Delay size of the readback data, and selects the middle sampling point sampled to the synchronous value of the synchronous data as the best sampling point for the readback data. Subsequent read data is sampled according to the best sampling point for the readback data to ensure data correctness.

[0119] Exemplarily, the master SPI device 10 samples the synchronization data first, and adaptively detects the middle sampling point of the reference valid data of the synchronization data (i.e., the delay (MIN+MAX) / 2 smpclk after the sampling reference point) as the best sampling point. Subsequent read data all start from the sampling reference point of each readback data bit, delay (MIN+MAX) / 2 smpclk (the (MIN+MAX) / 2 smpclk), arrive at the middle sampling point of the data, sample the stable and accurate value of each readback data, and correctly receive all the readback data.

[0120] According to the technical solution of the disclosed embodiment, for each SPI read operation, no matter the readback data Delay is large or small, the hardware can find the middle sampling point of the readback data by adaptively detecting the synchronization data. For each SPI read operation, synchronization data is sent for adaptive detection, which can adapt to the delay changes caused by changes in the system over time / temperature / working conditions. For each single operation, the change in SPI transmission delay is the same. However, the temperature and humidity change within 1 hour before and after, and the operating conditions are indoors and outdoors, and these changes will cause delay changes. The adaptive sampling used in this patent can adapt well to these changes, automatically find the middle sampling point of the readback data, and accurately and stably sample the readback data.

[0121] Because of adaptive sampling, the hardware automatically selects the best sampling point, so that the time width (period) of the data signal Dx can be made as narrow as possible (for example, 3 Tsmpclk), and it can also adapt to the changes in different delays and sample the correct value, thereby achieving the highest possible SPI communication rate.

[0122] For example, for the same SPI communication project, if the SPI communication is implemented using the technical solution in the related technology, CLK and Dx reuse the same PAD design, and the CLK rate of the SPI that is debugged and works stably under various working conditions such as high and low temperatures is 15MHz (corresponding to a single-line data communication rate of 15Mbps, a two-line data communication rate of 30Mbps, and a four-line data communication rate of 60Mbps).

[0123] According to the technical solution of the embodiment of the present disclosure, when the PAD design of CLK and Dx and the high-multiple sampling clock remain unchanged, the CLK rate of the SPI that is debugged and works stably under various working conditions such as high and low temperatures is 25MHz (corresponding to a single-line data communication rate of 25Mbps, a two-line data communication rate of 50Mbps, and a four-line data communication rate of 100Mbps). It can be seen that the data communication rate has increased by 66.7%.

[0124] See also Figure 6 , Figure 6 A flow chart of an SPI communication method according to an embodiment of the present disclosure is shown.

[0125] The method is applied to a SPI communication system including a master SPI device 10 and a slave SPI device 20, wherein: Figure 6 As shown, the method includes:

[0126] Step S11, upon receiving a read instruction and a read data clock signal from the master SPI device 10, using the slave SPI device 20 to sequentially send a synchronous data signal and a read data signal based on the read data clock signal, wherein the synchronous data signal includes reference valid data;

[0127] Step S12, using the master SPI device 10 to determine the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronous data signal, and using the middle sampling point of the readback data bit to receive the valid data in the read data signal.

[0128] In the SPI communication system of the embodiment of the present disclosure, when the slave SPI device 20 receives the read instruction and the read data clock signal of the master SPI device 10, it sequentially sends the synchronous data signal and the read data signal based on the read data clock signal, so that the master SPI device 10 determines the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronous data signal, and uses the middle sampling point of the readback data bit to receive the valid data in the read data signal, thereby solving the problem of troublesome and difficult debugging of read data sampling caused by large delay and delay changes with the environment. The hardware device can adaptively sample the readback data. Since no additional debugging is allowed, the debugging time is reduced. The embodiment of the present disclosure can also improve the communication rate of SPI communication.

[0129] In a possible implementation manner, determining the intermediate sampling point of the readback data bit according to the sampling sequence data of the reference valid number in the synchronous data signal includes:

[0130] Continuously sampling the synchronous data signal using a high-multiple sampling clock to obtain a sampling sequence of reference valid data, wherein the high-multiple sampling clock is L times the read data clock signal, where L is a positive number;

[0131] The middle sampling point of the readback data bit is determined according to the sampling sequence of the reference valid data.

[0132] In a possible implementation manner, determining the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data includes:

[0133] If the sampling reference point of the reference valid data is taken as point 0, the position of the high-multiple sampling clock of the data bit of the reference valid data sampled for the first time is marked as MIN, and the position of the high-multiple sampling clock of the data bit of the reference valid data sampled for the last time is marked as MAX, then the middle sampling point of the readback data bit is determined to be the (MIN+MAX) / 2th high-multiple sampling clock after the sampling reference point,

[0134] The MIN before the sampling reference point is a negative integer, the MIN at the sampling reference point is 0, the MIN after the sampling reference point is a positive integer, the MAX is a positive integer, and the absolute value of the MAX is greater than the absolute value of the MIN.

[0135] The middle sampling point of all subsequent read-back data bits is the (MIN+MAX) / 2th high-multiple sampling clock after the sampling reference point of each read-back data bit.

[0136] In a possible implementation manner, receiving valid data in the read data signal using an intermediate sampling point determined by reference valid data of the synchronization data includes:

[0137] A sampling reference point of each of the read data signals is delayed by (MIN+MAX) / 2 times the sampling clock frequency to sample and receive each of the read-back data at a middle sampling point of each of the read-back data.

[0138] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0139] It should be noted that the SPI communication method is a method corresponding to the aforementioned SPI communication system. For details, please refer to the previous introduction to the SPI communication system, which will not be repeated here.

[0140] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An SPI communication system, characterized in that: The SPI communication system comprises a master SPI device and a slave SPI device, wherein: The slave SPI device is used to: upon receiving a read instruction and a read data clock signal from the master SPI device, sequentially send a synchronous data signal and a read data signal based on the read data clock signal, wherein the synchronous data signal includes reference valid data; The master SPI device is used to: Determine an intermediate sampling point of the readback data bit according to a sampling sequence of reference valid data in the synchronous data signal; Valid data in the read data signal is received using an intermediate sampling point of the readback data bit.

2. The system according to claim 1, characterized in that: The step of determining the intermediate sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronous data signal comprises: Continuously sampling the synchronous data signal using a high-multiple sampling clock to obtain a sampling sequence of the reference valid data, wherein the high-multiple sampling clock is L times the read data clock signal, where L is a positive number; The middle sampling point of the readback data bit is determined according to the sampling sequence of the reference valid data.

3. The system according to claim 2, characterized in that The step of determining the intermediate sampling point of the readback data bit according to the sampling sequence of the reference valid data comprises: If the sampling reference point of the reference valid data is taken as point 0, the position of the high-multiple sampling clock of the data bit of the reference valid data sampled for the first time is marked as MIN, and the position of the high-multiple sampling clock of the data bit of the reference valid data sampled for the last time is marked as MAX, then the middle sampling point of the readback data bit is determined to be the (MIN+MAX) / 2th high-multiple sampling clock after the sampling reference point, The MIN before the sampling reference point is a negative integer, the MIN at the sampling reference point is 0, the MIN after the sampling reference point is a positive integer, the MAX is a positive integer, and the absolute value of the MAX is greater than the absolute value of the MIN. The middle sampling point of all subsequent read-back data bits is the (MIN+MAX) / 2th high-multiple sampling clock after the sampling reference point of each read-back data bit.

4. The SPI communication system according to claim 3, characterized in that: Receiving valid data in the read data signal using the intermediate sampling point of the readback data bit includes: A sampling reference point of each of the read data signals is delayed by (MIN+MAX) / 2 times the sampling clock frequency to sample and receive each of the read-back data at a middle sampling point of each of the read-back data.

5. The SPI communication system according to claim 1, characterized in that: The master SPI device and the slave SPI device are both chips.

6. An SPI communication method, characterized in that: The method is applied to an SPI communication system including a master SPI device and a slave SPI device, wherein the method comprises: When receiving a read instruction and a read data clock signal from the master SPI device, using the slave SPI device to sequentially send a synchronous data signal and a read data signal based on the read data clock signal, wherein the synchronous data signal includes reference valid data; The master SPI device is used to determine the middle sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronous data signal, and the middle sampling point of the readback data bit is used to receive the valid data in the read data signal.

7. The SPI communication method according to claim 6, characterized in that: The step of determining the intermediate sampling point of the readback data bit according to the sampling sequence of the reference valid data in the synchronous data signal comprises: Continuously sampling the synchronous data signal using a high-multiple sampling clock to obtain a sampling sequence of the reference valid data, wherein the high-multiple sampling clock is L times the read data clock signal, where L is a positive number; The middle sampling point of the readback data bit is determined according to the sampling sequence of the reference valid data.

8. The SPI communication method according to claim 7, characterized in that: The step of determining the intermediate sampling point of the readback data bit according to the sampling sequence of the reference valid data comprises: If the sampling reference point of the reference valid data is taken as point 0, the position of the high-multiple sampling clock of the data bit of the reference valid data sampled for the first time is marked as MIN, and the position of the high-multiple sampling clock of the data bit of the reference valid data sampled for the last time is marked as MAX, then the middle sampling point of the readback data bit is determined to be the (MIN+MAX) / 2th high-multiple sampling clock after the sampling reference point, The MIN before the sampling reference point is a negative integer, the MIN at the sampling reference point is 0, the MIN after the sampling reference point is a positive integer, the MAX is a positive integer, and the absolute value of the MAX is greater than the absolute value of the MIN. The middle sampling point of all subsequent read-back data bits is the (MIN+MAX) / 2th high-multiple sampling clock after the sampling reference point of each read-back data bit.

9. The SPI communication method according to claim 8, characterized in that: Receiving valid data in the read data signal using the intermediate sampling point of the readback data bit includes: A sampling reference point of each of the read data signals is delayed by (MIN+MAX) / 2 times the sampling clock frequency to sample and receive each of the read-back data at a middle sampling point of each of the read-back data.

10. The SPI communication method according to claim 6, characterized in that: The master SPI device and the slave SPI device are both chips.

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