Power supply network optimization method for enhancing reliability of chip in strong magnetic pulse environment

Abstract

The invention belongs to the technical field of chip power supply networks. The invention provides a power supply network optimization method for enhancing the reliability of a chip in a strong magnetic pulse environment. According to the embodiment of the invention, the chip is designed by using the EDA tool based on the design condition of the chip, and the initial power supply network is obtained. The initial power supply network forms a closed loop as much as possible; through holes of different metal layers are enabled to be in the same vertical line as much as possible, and an open-loop structure is converted into an L-shaped structure; under the condition that the power supply requirement is met, redundant metal lines are properly added; and reducing the magnetic flux integral area through a multi-fold structure to obtain a target power supply network. The range of improving the magnetic interference resistance of the chip is expanded, the influence of an external magnetic field on a chip power supply network is considered, and a reliability optimization scheme is provided for chip design in a strong magnetic pulse environment.

Description

Background Art

[0002] With the rapid development of integrated circuits, the feature size has shrunk from micron to nanometer. Now researchers are breaking the saying that "Moore's Law is no longer applicable" again and again. New transistor structures or integrated circuit architectures such as FinFET, GAAFET, and Chiplet have emerged. The feature size is developing towards the atomic level, and the integration of integrated circuits is no longer what it used to be. The rapid increase in integration has brought a series of advantages, such as lower power supply voltage, which greatly reduces power consumption, and the surge in the number of transistors makes the chip performance more powerful. However, increasingly complex integrated circuits will also face more complex reliability issues. For example, the electromagnetic environment is a major area of ​​reliability research.

[0003] Inside the chip, researchers mainly focus on EMI caused by fast switching currents. In this regard, Wataru Ichimura et al. reduced EMI by using variable online capacitors and resistors to suppress the Q factor of PDN in 2014. Dongil Shin et al. used a cavity resonant circuit model to efficiently calculate the electromagnetic interference coefficient of PDN in 2015. In 2021, Changjong Lee et al. optimized the decoupling capacitor of PDN based on deep reinforcement learning to suppress EMI. In 2022, Jingook Kim's team proposed automatic reinforcement learning based on spice integration for the problems of EMI and power integrity.

[0004] Outside the chip, since the chip's PDN is very small, according to Faraday's law of electromagnetic induction, the potential fluctuations generated by the magnetic field pulse in a small area loop are very small, so researchers often ignore the impact of external EMI on the PDN. However, the actual situation is that in some special application environments, the intensity and rate of change of the magnetic field are sufficient to cause the potential of the PDN to fluctuate, resulting in timing problems, logic errors, and even burning of the chip. For example, in the military field, in addition to using electromagnetic interference to destroy enemy control systems, electromagnetic pulses can also be used to develop new weapons. Electromagnetic coil guns or electromagnetic rail guns all use electromagnetic force to launch projectiles. Its principle is as follows: Figure 1 In applications such as these, capacitor discharge is often used to generate transient current and induce magnetic field. The topology of the discharge circuit is Figure 2As shown. The peak value of the magnetic field pulse generated by the discharge of a general electromagnetic gun can reach about 10T, and its frequency is about 10kHz-300MHz. In addition, in the civilian field, some medical equipment, such as nuclear magnetic resonance, will also generate high-frequency and high-intensity magnetic fields, and wireless local area networks (WiFi) will generate high-frequency and low-intensity magnetic fields. Whether in the military field or in the civilian field, electromagnetic pulses are everywhere and in a variety of types. Clarifying the characteristics of various electromagnetic pulses is the key to designing anti-electromagnetic interference chips.

[0005] Therefore, it is necessary to improve one or more problems existing in the above-mentioned related technical solutions.

[0006] It should be noted that this section is intended to provide background or context for the technical solutions of the present disclosure stated in the claims. The description herein is not admitted to be prior art by virtue of being included in this section. Summary of the invention

[0007] In order to avoid the shortcomings of the prior art, the present invention provides a power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment, so as to solve the problem in the prior art that the impact of external harsh magnetic fields on the chip power supply network is ignored due to the small area of ​​the chip power supply network.

[0008] According to a first aspect of an embodiment of the present disclosure, a power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment is provided, the method comprising: Based on the design conditions of the chip, use EDA tools to design the chip to obtain the initial power network; Performing a first DRC check on the initial power supply network, and if the check passes, selecting an optimization strategy to optimize the initial power supply network; A second DRC check is performed on the optimized initial power supply network, and if the second DRC check passes, a target power supply network is obtained.

[0009] Furthermore, the optimization strategy includes: Strategy 1: Make the loop formed by the power supply network itself close; Strategy 2: adding a preset number of redundant metal lines in the power network; Strategy three: A multi-fold structure is used in the power supply network to reduce the integrated area.

[0010] Furthermore, the step of selecting an optimization strategy to optimize the initial power supply network includes: The initial power supply network is optimized using the strategy one, the strategy two and the strategy three in sequence.

[0011] Furthermore, the method also includes: If the first DRC check fails, modifying the initial power supply network according to error information of the first DRC check; The first DRC check is performed on the corrected initial power supply network.

[0012] Furthermore, the method further comprises: If the second DRC check fails, modifying the optimized initial power network according to the error information of the second DRC check; The second DRC check is performed on the modified optimized initial power supply network.

[0013] According to a second aspect of an embodiment of the present disclosure, a power supply network optimization device for enhancing chip reliability in a strong magnetic pulse environment is provided, the device comprising: A design module is used to design a chip based on the design conditions of the chip using EDA tools to obtain an initial power supply network; An optimization module, configured to perform a first DRC check on the initial power supply network, and if the check passes, select an optimization strategy to optimize the initial power supply network; The output module is used to perform a second DRC check on the optimized initial power supply network, and if the second DRC check passes, a target power supply network is obtained.

[0014] Furthermore, the device also includes: A first correction module is used to correct the initial power supply network according to error information of the first DRC check if the first DRC check fails; and perform the first DRC check on the corrected initial power supply network.

[0015] Furthermore, the device also includes: The second correction module is used to correct the optimized initial power network according to the error information of the second DRC check if the second DRC check fails; and perform the second DRC check on the corrected optimized initial power network.

[0016] According to a third aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the steps of the power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment described in any of the above embodiments are implemented.

[0017] According to a fourth aspect of an embodiment of the present disclosure, there is provided an electronic device, including: Processor; and A memory, configured to store executable instructions of the processor; The processor is configured to execute the steps of the power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment described in any one of the above embodiments by executing the executable instructions.

[0018] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects: In the embodiments of the present disclosure, through the above-mentioned power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment, on the one hand, based on the design conditions of the chip, the chip is designed using EDA tools to obtain an initial power supply network. The initial power supply network itself is made to form a closed loop as much as possible; the through holes of different metal layers are made to be on the same vertical line as much as possible, and the open-loop structure is converted into an L-shaped structure; while meeting the power supply requirements, redundant metal lines are appropriately added; the magnetic flux integral area is reduced through a multi-fold structure to obtain a target power supply network. On the other hand, the scope of improving the chip's anti-magnetic interference capability is expanded, the influence of the external magnetic field on the chip power supply network is taken into account, and a reliability optimization solution is provided for chip design in a strong magnetic pulse environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0020] Figure 1 The schematic diagram of electromagnetic gun in the prior art is shown; Figure 2 The discharge circuit of the electromagnetic gun in the prior art is shown; Figure 3 A step diagram showing a method for optimizing a power supply network for enhancing chip reliability in a strong magnetic pulse environment in an exemplary embodiment of the present disclosure; Figure 4 The simplified parameter model in the exemplary embodiment of the present disclosure is shown; Figure 5 shows potential fluctuations of a tree structure and a ring structure in an exemplary embodiment of the present disclosure; Figure 6 A tree structure diagram showing case 1 and case 2 in an exemplary embodiment of the present disclosure is shown; Figure 7 The potential fluctuations of the tree structures of Case 1 and Case 2 in the exemplary embodiment of the present disclosure are shown; Figure 8 The single-fold structure of the power supply network in the exemplary embodiment of the present disclosure is shown; Fig. 9The integral region enclosed by the open-loop wire and the symmetric point of the magnetic field in the exemplary embodiment of the present disclosure is shown; Fig.10 The three-fold structure of the power supply network in the exemplary embodiment of the present disclosure is shown; Fig.11 The simulation results of the change of the number of folding angles of the multi-fold structure in the exemplary embodiment of the present disclosure are shown; Fig.12 A power network model with different hem lengths in an exemplary embodiment of the present disclosure is shown; Fig.13 The simulation results of the open-loop network structure with different fold lengths in the exemplary embodiment of the present disclosure are shown; Fig.14 shows potential fluctuations for different line widths in an exemplary embodiment of the present disclosure; Fig.15 FIG. 2 shows voltage fluctuations of different power supply line numbers PDN in an exemplary embodiment of the present disclosure; Fig.16 A local model of a Leon2 power supply network in an exemplary embodiment of the present disclosure is shown; Fig.17 The power supply path separated from the Leon2 power supply network in the exemplary embodiment of the present disclosure is shown; Fig.18 Showing a prototype line from input port to port 1 in an exemplary embodiment of the present disclosure; Fig.19 Schematic diagram showing an optimized route from an input port to port 1 in an exemplary embodiment of the present disclosure; Fig. 20 shows the simulation results before and after optimization of port 1 in an exemplary embodiment of the present disclosure; Fig.21 A prototype circuit from the input port to port 2 in an exemplary embodiment of the present disclosure is shown; Fig. 22 The optimized circuit from the input port to port 2 in the exemplary embodiment of the present disclosure is shown; Fig.23 shows the simulation results before and after optimization of port 2 in an exemplary embodiment of the present disclosure; Fig.24 A prototype circuit from the input port to port 3 in an exemplary embodiment of the present disclosure is shown; Fig.25 An optimized circuit from the input port to port 3 in an exemplary embodiment of the present disclosure is shown; Fig.26 shows the simulation results before and after optimization of port 3 in the exemplary embodiment of the present disclosure; Fig. 27 A prototype circuit from the input port to port 4 in an exemplary embodiment of the present disclosure is shown; Fig.28An optimized circuit from the input port to port 4 in an exemplary embodiment of the present disclosure is shown; Fig.29 shows the simulation results before and after optimization of port 4 in the exemplary embodiment of the present disclosure; Fig.30 The PDN model before optimization in the exemplary embodiment of the present disclosure is shown; Fig.31 shows the potential fluctuation of the PDN model before optimization in the exemplary embodiment of the present disclosure; Fig.32 The optimized PDN model in the exemplary embodiment of the present disclosure is shown; Fig.33 shows the potential fluctuation of the optimized PDN model in the exemplary embodiment of the present disclosure; Fig.34 The comparison of potential fluctuations before and after optimization of each test point in the exemplary embodiment of the present disclosure is shown; Fig.35 A schematic diagram of a power network optimization device for enhancing chip reliability in a strong magnetic pulse environment in an exemplary embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0021] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0022] In addition, the accompanying drawings are only schematic illustrations of the embodiments of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0023] This exemplary embodiment provides a power network optimization method for enhancing chip reliability in a strong magnetic pulse environment. Figure 3 As shown in , the power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment may include: steps S101 to S103.

[0024] Based on the design conditions of the chip, use EDA tools to design the chip to obtain the initial power network; Performing a first DRC check on the initial power supply network, and if the check passes, selecting an optimization strategy to optimize the initial power supply network; A second DRC check is performed on the optimized initial power supply network, and if the second DRC check passes, a target power supply network is obtained.

[0025] Through the above-mentioned power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment, on the one hand, based on the chip design conditions, the chip is designed using EDA tools to obtain an initial power supply network. The initial power supply network itself is made to form a closed loop as much as possible; the through holes of different metal layers are made to be on the same vertical line as much as possible, and the open-loop structure is converted into an L-shaped structure; while meeting the power supply requirements, redundant metal lines are appropriately added; the magnetic flux integral area is reduced through a multi-fold structure to obtain the target power supply network. On the other hand, the scope of improving the chip's anti-magnetic interference ability is expanded, the influence of the external magnetic field on the chip power supply network is considered, and a reliability optimization solution is provided for chip design in a strong magnetic pulse environment.

[0026] Next, we will refer to Figures 3 to 34 The various steps of the above-mentioned power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment in this exemplary embodiment are described in more detail.

[0027] In step S101 to step S103, when the back-end engineer starts to layout and route the chip, in order to improve the chip's anti-magnetic interference capability, the corresponding design work can be performed according to the following steps: Fully understand the design specifications for line width, line spacing, and constraints such as resource usage.

[0028] Use EDA tools to complete the preliminary power supply network of the chip.

[0029] Perform a DRC (design rule) check on the results of the power supply network. If the DRC check passes, proceed to the power supply network initially completed by the EDA tool and perform gradual optimization with the help of optimization strategies one, two, and three. If the DRC check fails, manually modify the power supply network based on the DRC error message.

[0030] Perform a DRC check on the optimized power network. If the DRC check passes, the power network is completed; if the DRC check fails, manually modify the power network according to the DRC error information.

[0031] In a specific embodiment, the simulation model of the present application uses simplified models with different parameters for different simulation variables, such as Figure 4As shown in the figure. Stripes_length is the length of the stripe, the entire model is a mesh structure, Stripes_width is the stripe width, and the number of metal wires in the model is also one of the important influencing factors discussed later, so the number of metal wires in the model (Stripes_num) is also parameterized. The blue stripe and the green stripe are located in the upper and lower layers respectively, and are connected together through black vias.

[0032] In a specific embodiment, in the multi-layer metal network of the chip, there are ring structures (such as the PDN of the top two layers and the power supply lines connected by through holes between the multi-layer metals) and tree structures (such as the power supply lines of the multi-layer metals that are finally connected to the functional units after being connected by vias). This section adds background magnetic fields for simulation of the above two different structures.

[0033] The simulation model of the ring structure adopts a closed-loop structure with a line length of 1000um, a line width of 0.25um, and a line number of 4.

[0034] The simulation model of the tree structure adopts an open-loop structure with a line number of 1000um, a line width of 0.25um, and a line number of 4.

[0035] In the ring structure, the load of the metal wire is very small, so the induced ring current does not produce a large potential fluctuation in the ring structure. In the tree structure, the changing magnetic field causes the electrons to move in a directional manner, resulting in high and low potentials at different ends, so the rapid change rate of magnetic flux produces a larger potential fluctuation in the tree structure.

[0036] After adding the background magnetic field, the potential fluctuations at different locations of the PDN are as follows: Figure 5 As shown in the figure, the potential fluctuation in the ring structure is about 30% of the potential fluctuation in the tree structure. Therefore, when designing PDN, metals of different layers should be connected through vias as much as possible to transform the tree structure into a ring structure.

[0037] Due to the different positions of vias, the power lines in the tree structure will also form different structures. Different structures make the PDN's anti-interference ability to magnetic fields different. The following is based on the position of the vias to divide the PDN into Figure 6 (a) Situation (i.e. Situation 1) and Figure 6 (b) Case 2, and simulate its anti-electromagnetic interference capability. Figure 6 (a) The four metal lines in the structure form an open loop structure because the vias are not on the same vertical line. Figure 6 (b) The vias connecting the four metal wires in the structure are located on the same vertical line, so that the four metal wires form an L-shaped structure, where metal wire 3 is located directly below metal wire 1 and metal wire 4 is located directly below metal wire 2. The simulation results are shown in Figure 2. Figure 7 shown.

[0038] from Figure 7 It can be concluded from the simulation results that Figure 6 (b) The potential fluctuation of the structure is reduced to Figure 6 (a) The structure is 50% stronger in anti-interference ability. This is mainly because the pulse magnetic field generates a vortex electric field in space, and the electrons in the conductor move in a directional manner in the electric field, thereby generating an electric potential difference. Figure 6 (a) The distance that electrons travel in the structure is Figure 6 (b) The structure is twice as large, so the potential difference generated by the work done by the electrons is also twice as large. In addition, Figure 6 The open-loop structure of (a) can easily form a multi-turn coil structure in the most layer structure, which increases the number of coil turns of magnetic induction, thereby superimposing the induced potential. Figure 6 The L-shaped structure of (b) breaks the spiral structure of the multi-layer open-loop structure, and the multi-layer metal will naturally not have the effect of overlapping turns of the coil, thereby greatly reducing the potential fluctuation.

[0039] A more in-depth discussion of the tree structure for case 2 shows that different multi-fold structures can be formed between two fixed potential test points. Next, a simulation analysis is performed based on the number and length of the folded edges.

[0040] The simulation model of the multi-fold structure adopts a fixed potential reference point and test point, and the outermost line length is 1000um and the line width is 0.25um.

[0041] For the number of folds In the layout design of the chip power network, from point A to point B on the next layer, most of the wiring structures automatically generated by EDA software are as follows: Figure 8 The circuit model shown.

[0042] The magnetic field has symmetric properties, which can be mainly divided into two types of symmetry, namely axisymmetry and point symmetry. Point symmetry means that the magnetic field has symmetric properties at a certain point in space, that is, any straight line or plane passing through the point cuts the spatial magnetic field, and the two sides of the spatial magnetic field after cutting have absolutely the same magnetic field properties. Using Maxwell's explicit solution, a time-varying homogeneous magnetic field is constructed, and the induced voltage of the open-loop circuit depends on the symmetry point of the magnetic field through Gauss's law, Lorentz gauge and delay potential derivation. And the induced voltage formula of the open-loop wire in a uniform time-varying magnetic field is simply summarized through the Maxwell equations (1): (1) in, The area enclosed by the conductor and the symmetrical point is Fig. 9 shown.

[0043] The area enclosed here can be obtained by formula (2): (2) In order to minimize the voltage fluctuation of the on-chip power supply network under the influence of electromagnetic pulses, the integral area enclosed by the symmetric points of the open-loop circuit and the electromagnetic field should be minimized as much as possible, so as to minimize the potential difference fluctuation at both ends of the open-loop wire. Therefore, based on this theory, this paper derives the single-fold structure preset in the computer into a three-fold structure from point A to point B, such as Fig.10 shown.

[0044] In order to accurately compare the difference between the single-fold structure and the three-fold structure of the power network, the parameters of the physical models of both are: open-loop structure with a line length of 492μm and a line width of 8μm. In the three-fold structure, the area enclosed by the open-loop line from point A to point B and the symmetric point of the magnetic field is reduced by nearly half compared to the single-fold structure. Fig.11 shown.

[0045] From the simulation results, it can be seen that the voltage fluctuation limit of the single-fold loop structure is 0.1435V, while the voltage fluctuation limit of the triple-fold structure is 0.0717V.

[0046] from Fig.11 It can be seen from the simulation results that the potential difference fluctuation of the three-fold structure is reduced to 50% of that of the single-fold structure, and the electromagnetic compatibility performance is stronger. This is mainly because in the three-fold structure, the integral area enclosed by the conductor of the three-fold structure and the symmetric point of the magnetic field is nearly half smaller than the area enclosed by the single-fold structure. Therefore, when calculating the open-loop induced voltage, the induced voltage of the three-fold structure will be nearly half of the induced voltage generated by the single-fold structure, and the voltage fluctuation generated is also almost half. From this, a conclusion can be drawn: the number of corners of the multi-fold structure in the power supply network will affect the voltage fluctuation of the power supply network under the pulsed magnetic field. The fluctuating voltage increases with the increase in the number of corners, and when the area enclosed by the open-loop power line structure and the symmetric point of the magnetic field is reduced by half, the reduction is also about 50.0%.

[0047] For hem length Similarly, for the study of the induced voltage of the open-loop power line, reducing the integral area enclosed by the open-loop power line path and the symmetric point of the magnetic field can reduce the voltage fluctuations generated by the high-power electromagnetic pulse on the open-loop power line. There are two ways to reduce the integral area enclosed by the open-loop power line path and the symmetric point of the magnetic field. One is to increase the number of corners so that the open-loop power line path can be closer to the symmetric point of the magnetic field. This method has been verified in the simulation experiment to verify the influence of the number of corners on electromagnetic interference. However, this method cannot be infinitely extended to a structure with a number of corners of 50%, 70%, 90%, and so on, because the on-chip power network of the chip has certain space limitations and cost conditions. Blindly increasing the number of corners will not only waste the scarce space resources of the on-chip power network, but also increase the manufacturing difficulty and manufacturing cost. Therefore, there is another way to reduce the integral area enclosed by the open-loop power line path and the symmetric point of the magnetic field, which is to change the length of the fold. Such as Fig.12 shown.

[0048] Among them, the left side is an open-loop network structure with a three-fold side length of 246μm, and the right side is a loop network structure with a three-fold side length of 123μm. With the help of CAD modeling software, a physical model is established for the circuit model, and its material is set to copper, the model line length is 492μm, the model line width and height are 8μm, and its fold angle is determined to be 3 folds. The fold lengths are modified to 246μm and 123μm respectively, and then imported into the finite element simulation software. The finite time domain algorithm is used in the low-frequency studio to solve the potential difference fluctuation between its ports, and the following is obtained: Fig.13 The simulation results are shown.

[0049] The voltage fluctuation limit of the loop network structure with a three-fold side length of 246μm is 0.0717V, and the voltage fluctuation limit of the loop network structure with a three-fold side length of 123μm is 0.0179V. Figure 3 It can be seen that the potential difference fluctuation of the power network structure with a three-fold side length of 246μm is much greater than the potential difference fluctuation of the power network structure with a three-fold side length of 123μm. This is mainly because the integral area surrounded by the open-loop power line path of the structure with a three-fold side length of 123μm and the symmetric point of the magnetic field is much smaller than the integral path surrounded by the open-loop power line path of the structure with a three-fold side length of 246μm and the symmetric point of the magnetic field. Therefore, when calculating the induced voltage in the open-loop circuit, the voltage fluctuation extreme value of the power network structure with a three-fold side length of 246μm will be much greater than the voltage fluctuation extreme value of the power network with a three-fold side length of 123μm.

[0050] Therefore, when optimizing the design of the power supply network, the fold length condition in the multi-fold structure should be fully considered to minimize the integral area enclosed by the open-loop power line path and the magnetic field symmetry point. However, this optimization is different from the optimization scheme of increasing the number of folds in the multi-fold structure in that, under the same number of folds, there will be a minimum voltage fluctuation. In other words, this optimization strategy cannot theoretically perfectly offset the voltage fluctuation caused by the electromagnetic pulse on the power supply network, while increasing the number of folds can theoretically make the voltage fluctuation close to 0V.

[0051] In a specific embodiment, a background magnetic field is added to the model with line widths of 0.25um, 0.50um, and 0.75um, and the potential fluctuations are as follows: Fig.14 As shown in the figure, as the line width increases, the maximum potential fluctuation of the power supply network is similar, but the rate of potential drop gradually decreases, and the influence of the line width increase on the anti-magnetic interference capability gradually decreases. When the line width increases to 0.75um, the line width no longer affects the potential fluctuation of the power supply network under the pulse magnetic field.

[0052] After analyzing the simulation results, it can be found that no matter how large the metal line width is, the maximum potential induced by the pulse magnetic field will not be much different. Therefore, the line width is not the main factor affecting the PDN's ability to resist magnetic interference.

[0053] In a specific embodiment, tree-like PDN structures with 4, 8, 12, and 16 lines are simulated respectively. The simulation results are shown in FIG. Fig.15 As shown, by analyzing the simulation results, it can be concluded that the more lines there are, the smaller the potential fluctuation caused by the pulse magnetic field, and the potential fluctuation decreases by 50% every time the number of lines doubles.

[0054] Extra wires will generate extra loops in the metal network. The same metal wire may belong to multiple loops with different areas at the same time. The direction of the same pulse magnetic field will generate electric fields with the same rotation direction in different loops, but different directions of electric fields will be generated on the same common metal wire, and the electric fields in different directions will cancel each other out. This is also the reason why the more wires there are, the smaller the potential fluctuation will be.

[0055] Therefore, when designing the actual chip power supply network, some redundant metal strips can be appropriately added on the basis of meeting the module power supply requirements and if the chip area allows.

[0056] In a specific embodiment, based on the local model of the on-chip power network of LEON2, such as Fig.16As shown. Referring to the parameters of its physical model, several typical power line paths are stripped from the power network structure of the Leon2 chip to form a four-layer seven-port power network original model. The line width of the original power network model is set to 8μm and the frame length is set to 492μm. Fig.17 As shown in the figure, the material of the model is metal copper.

[0057] Based on the simulation analysis results in the previous article, the four ports of this power supply path are optimized to resist strong magnetic pulse interference.

[0058] Port 1 optimization strategy and its optimization efficiency like Fig.18 As shown, the line marked in red is the prototype line from the input port to port 1.

[0059] According to the optimization scheme verified above, two additional folds are added to the basic line of port one, and the original single-fold structure is improved to a three-fold structure, thereby reducing the integral area enclosed by the magnetic field symmetry point and the open-loop power supply line, which can theoretically reduce the voltage fluctuation range between ports under high-power electromagnetic pulses. Its specific structure is as follows Fig.19 shown.

[0060] The above two circuit models are imported into the finite element simulation software for electromagnetic simulation, and the following results are obtained: Fig. 20 The simulation results are shown.

[0061] In the simulation experiment, the maximum value of the inter-port voltage fluctuation of the original model of port 1 is 0.0372V, while the maximum value of the inter-port voltage fluctuation after optimization is 0.0175V, and the optimization efficiency is 52.9%.

[0062] Port 2 optimization strategy and its optimization efficiency like Fig.21 As shown, the part marked in red is the prototype circuit of port 2 before optimization.

[0063] According to the optimization scheme verified in Chapter 3, two additional corners are added to the basic line of port 2, and the plane area covered by the entire line in space is reduced, thereby reducing the integral area surrounded by the magnetic field symmetry point and the power line, and reducing the voltage fluctuation range induced by the magnetic field in the open-loop circuit. The specific optimization scheme is as follows Fig. 22 shown.

[0064] The above two circuit models are imported into the finite element simulation software for electromagnetic simulation, and the following results are obtained: Fig.23 The simulation results are shown.

[0065] In the simulation experiment, the maximum value of the inter-port voltage fluctuation of the original model of port 2 is 0.108V, while the maximum value of the inter-port voltage fluctuation after optimization is 0.0329V, and the optimization efficiency is 69.5%.

[0066] Port three optimization strategy and its optimization efficiency like Fig.24 As shown, the part marked in red is the prototype circuit of port 3 before optimization.

[0067] According to the optimization scheme verified above, 4 additional corners are added to the basic line of port 3, and part of the circuit from the input port to port 3 is shared with the circuit from the input port to port 2, which reduces the overall space occupied by the power network, improves space utilization, and reduces the integral path between the magnetic field symmetry point and the open-loop power line, thereby reducing the potential difference fluctuation between the ports. The specific line is as follows Fig.25 shown.

[0068] The above two circuit models are imported into the finite element simulation software for electromagnetic simulation, and the following results are obtained: Fig.26 The simulation results are shown.

[0069] In the simulation experiment, the maximum value of the inter-port voltage fluctuation of the original model of port 3 is 0.0681V, while the maximum value of the inter-port voltage fluctuation after optimization is 0.0071V, and the optimization efficiency is 89.5%.

[0070] Port Four Optimization Strategy and Its Optimization Efficiency like Fig. 27 As shown, the part marked in red is the prototype circuit of port 4 before optimization.

[0071] According to the optimization scheme verified above, two additional corners are added to the basic line of port 4, and the plane area covered by the entire line in space is reduced, thereby reducing the integral area surrounded by the magnetic field symmetry point and the power line, and reducing the voltage fluctuation range induced by the magnetic field in the open-loop circuit. The specific optimization scheme is as follows Fig.28 shown.

[0072] The above two circuit models are imported into the finite element simulation software for electromagnetic simulation, and the following results are obtained: Fig.28 The simulation results are shown.

[0073] In the simulation experiment, the maximum value of the inter-port voltage fluctuation of the original model of port 4 is 0.1435 V, while the maximum value of the inter-port voltage fluctuation after optimization is 0.0780 V, and the optimization efficiency is 45.6%.

[0074] In a specific embodiment, by modeling the local PDN of a SMIC130nm-based Leon2 processor ( Fig.30) is used as the PDN model before optimization. The model has a maximum line length of 20um, a minimum line width of 0.3um, and is composed of 5 layers of metal. Compared with the area of ​​the abstract model selected in the previous simulation, the area of ​​a small part of the actual PDN model selected here is nearly 2500 times smaller, so the induced potential in the simulation results is also much smaller, from the mV level to uV. The comparison before and after optimization for the same model is not for different models, so the use of local models does not affect the verification results of the optimization strategy, and the local model greatly speeds up the simulation speed and the simulation pressure of the software. Fig.30 Five randomly selected potential fluctuation monitoring points are marked in Figure 2. Adding a background magnetic field to the model, the simulation results are shown in Figure 2. Fig.31 shown.

[0075] Comprehensive simulation analysis, modify the minimum line width of the model, reduce unnecessary lines, change the via position, and thus change the network structure. The optimized model is as follows Fig.32 The simulation results after adding the background magnetic field to the optimized model are shown in Fig.33 shown.

[0076] Comparing the models before and after optimization, Fig.32 The red module is the part added to the simulation result based on the model before optimization. The optimization strategy here mainly includes: 1. Add vias at appropriate locations to connect metal wires on different layers into rings; 2. Appropriately increase redundant metal wires.

[0077] Fig.34 The maximum potential fluctuations at each monitoring point before and after optimization are compared. The potential fluctuations at monitoring points 1, 3, and 4 all showed significant reductions after optimization. The potential fluctuation at monitoring point 1 dropped directly to near 0V after optimization, the potential fluctuation at monitoring point 3 decreased by 90%, and the potential fluctuation at monitoring point 4 decreased by 50%. The main reason why monitoring points 2 and 5 did not show significant changes was that the optimized positions did not cover the entire model. When only one power supply node is optimized, the potential fluctuations of other nodes in the entire power supply network will inevitably be affected. Considering all power supply nodes comprehensively, a large amount of simulation calculations and result predictions are required. Perhaps it is a good idea to introduce machine learning methods. The current optimization strategy research still focuses on the potential fluctuations of a certain node, evaluates the voltage fluctuation tolerance threshold of each module in advance, selects the path with a lower voltage fluctuation tolerance threshold for key optimization, and also provides a direction for subsequent research.

[0078] Through the above-mentioned power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment, on the one hand, based on the chip design conditions, the chip is designed using EDA tools to obtain an initial power supply network. The initial power supply network itself is made to form a closed loop as much as possible; the through holes of different metal layers are made to be on the same vertical line as much as possible, and the open-loop structure is converted into an L-shaped structure; while meeting the power supply requirements, redundant metal lines are appropriately added; the magnetic flux integral area is reduced through a multi-fold structure to obtain the target power supply network. On the other hand, the scope of improving the chip's anti-magnetic interference ability is expanded, the influence of the external magnetic field on the chip power supply network is considered, and a reliability optimization solution is provided for chip design in a strong magnetic pulse environment.

[0079] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc. In addition, it is also easy to understand that these steps may be, for example, executed synchronously or asynchronously in multiple modules / processes / threads.

[0080] Furthermore, in this exemplary embodiment, a power supply network optimization device for enhancing chip reliability in a strong magnetic pulse environment is also provided. Fig.35 As shown in , the apparatus 100 may include a design module 101, an optimization module 102, and an output module 103. Among them: A design module 101 is used to design a chip using an EDA tool based on the design conditions of the chip to obtain an initial power supply network; The optimization module 102 is used to perform a first DRC check on the initial power supply network, and if the check passes, select an optimization strategy to optimize the initial power supply network; The output module 103 is used to perform a second DRC check on the optimized initial power supply network, and if the second DRC check passes, a target power supply network is obtained.

[0081] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0082] It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiment of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of a module or unit described above can be further divided into multiple modules or units for concretization. The components displayed as modules or units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the disclosed solution. Those of ordinary skill in the art can understand and implement it without paying creative work.

[0083] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is also provided, on which a computer program is stored, and when the program is included in a processor and executed, the steps of the power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment described in any of the above embodiments can be implemented. In some possible implementations, various aspects of the present invention can also be implemented in the form of a program product, which includes a program code, and when the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps of various exemplary embodiments of the present invention described in the above section of the power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment of this specification.

[0084] In an exemplary embodiment of the present disclosure, an electronic device is also provided, which may include a processor and a memory for storing executable instructions of the processor. The processor is configured to execute the steps of the power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment described in any of the above embodiments by executing the executable instructions.

[0085] It will be appreciated by those skilled in the art that various aspects of the present invention may be implemented as a system, method or program product. Therefore, various aspects of the present invention may be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as a "circuit", "module" or "system".

Claims

1. A power network optimization method for enhancing chip reliability in a strong magnetic pulse environment, characterized in that: The method includes: Based on the design conditions of the chip, use EDA tools to design the chip to obtain the initial power network; Performing a first DRC check on the initial power supply network, and if the check passes, selecting an optimization strategy to optimize the initial power supply network; A second DRC check is performed on the optimized initial power supply network, and if the second DRC check passes, a target power supply network is obtained.

2. The power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment according to claim 1 is characterized in that: The optimization strategies include: Strategy 1: Make the loop formed by the power supply network itself close; Strategy 2: adding a preset number of redundant metal lines in the power network; Strategy three: A multi-fold structure is used in the power supply network to reduce the integrated area.

3. The power network optimization method for enhancing chip reliability in a strong magnetic pulse environment according to claim 2 is characterized in that: The step of selecting an optimization strategy to optimize the initial power supply network includes: The initial power supply network is optimized using the strategy one, the strategy two and the strategy three in sequence.

4. The power network optimization method for enhancing chip reliability in a strong magnetic pulse environment according to claim 1 is characterized in that: The method further includes: If the first DRC check fails, modifying the initial power supply network according to error information of the first DRC check; The first DRC check is performed on the corrected initial power supply network.

5. The power network optimization method for enhancing chip reliability in a strong magnetic pulse environment according to claim 1, characterized in that: The method further includes: If the second DRC check fails, modifying the optimized initial power network according to the error information of the second DRC check; The second DRC check is performed on the modified optimized initial power supply network.

6. A power network optimization device for enhancing chip reliability in a strong magnetic pulse environment, characterized in that: The device includes: A design module is used to design a chip based on the design conditions of the chip using EDA tools to obtain an initial power supply network; An optimization module, configured to perform a first DRC check on the initial power supply network, and if the check passes, select an optimization strategy to optimize the initial power supply network; The output module is used to perform a second DRC check on the optimized initial power supply network, and if the second DRC check passes, a target power supply network is obtained.

7. The power network optimization device for enhancing chip reliability in a strong magnetic pulse environment according to claim 6, characterized in that: The device also includes: A first correction module is used to correct the initial power supply network according to error information of the first DRC check if the first DRC check fails; and perform the first DRC check on the corrected initial power supply network.

8. The power network optimization device for enhancing chip reliability in a strong magnetic pulse environment according to claim 6, characterized in that: The device also includes: The second correction module is used to correct the optimized initial power network according to the error information of the second DRC check if the second DRC check fails; and perform the second DRC check on the corrected optimized initial power network.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment as described in any one of claims 1 to 5 are implemented.

10. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to execute the steps of the power supply network optimization method for enhancing chip reliability in a strong magnetic pulse environment as described in any one of claims 1 to 5 by executing the executable instructions.

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