Driving module and display device

Abstract

The present application belongs to the field of display, and specifically relates to a driving module and a display device, wherein the driving module includes a plurality of source driving chips, a polarity partitioning control module, a picture detection module, a reversal time extension module, and a reversal signal control module, wherein each source driving chip is connected to a plurality of columns of data lines of a display panel, source driving chips of odd columns are connected to a pull-down power supply, a polarity partitioning control module controls source driving chips of even columns to be connected to a pull-up power supply or a pull-down power supply, a picture detection module is used to detect whether polarity partitioning is required for the display panel, so that the polarities of display areas controlled by adjacent source driving chips are symmetrical, and a reversal time extension module is connected to all source driving chips, and is used to extend the interval time of polarity reversal of the display panel. When polarity partitioning is required, the interval time of polarity reversal is extended by the reversal time extension module, which can alleviate lateral crosstalk while eliminating the problem of bright and dark lines, thereby improving the display effect of the display panel.

Description

Technical Field

[0001] The present application belongs to the field of display, and specifically relates to a driving module and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) includes an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. When the liquid crystal display is displayed, the pixel electrode on one side of the array substrate and the common electrode on one side of the color filter substrate form a liquid crystal capacitor (Clc) to drive the deflection of the liquid crystal molecules and control the brightness of each sub-pixel to realize the picture display. The pixel electrode and the common electrode on one side of the array substrate form a storage capacitor (Cst) to maintain the voltage of the liquid crystal capacitor.

[0003] If a single-direction electric field is applied to the liquid crystal molecules for a long time, the liquid crystal molecules may be polarized, resulting in a decrease in display quality or even damage to the liquid crystal material. By reversing the polarity and alternating the direction of the electric field, the polarization of the liquid crystal molecules can be effectively avoided. Polarity reversal methods include frame reversal, row reversal, column reversal, and dot reversal.

[0004] When the liquid crystal display is displaying, the data line provides pixel voltage to the pixel electrode. The polarity reversal makes the pixel voltage greater than or less than the voltage of the common electrode. The coupling capacitance (Cdc) formed between the data line and the pixel electrode will cause the pixel voltage to shift, resulting in lateral crosstalk (H-Crosstalk), which affects the display effect of the liquid crystal display. Summary of the invention

[0005] The purpose of the present application is to provide a driving module and a display device to improve or eliminate lateral crosstalk and improve the display effect of a liquid crystal display.

[0006] In order to achieve the above object, the present application provides a driving module, including a plurality of source driving chips, each of which is connected to a plurality of columns of data lines of a display panel, and the driving module further includes:

[0007] A polarity partition control module, wherein the source driver chips of the odd columns are connected to a pull-down power supply, and the source driver chips of the even columns are connected to a pull-up power supply and the pull-down power supply through the polarity partition control module, and the pull-down power supply includes a ground terminal;

[0008] A picture detection module connected to the display panel and the polarity partition control module, used to detect whether the display panel needs to be polarized, and when polarity partition is needed, control the polarity partition control module to turn on the source driver chips and the pull-up power supply of the even-numbered columns, so that the polarities of the display areas controlled by the adjacent source driver chips are symmetrical;

[0009] A reversal time extension module, connected to all the source driver chips, for extending the interval time of polarity reversal of the display panel;

[0010] The inversion signal control module is connected to the polarity partition control module or the picture detection module, and is used to control the inversion time extension module to be turned on with the source driver chip when polarity partition is required.

[0011] Optionally, the polarity partition control module includes a first transistor and a first resistor, the control end of the first transistor is connected to the screen detection module, the first end of the first transistor is connected to the pull-up power supply, the second end of the first transistor is connected to the source driver chip of the even column through a first node, the source driver chip of the odd column is connected to the pull-down power supply through a second node, and the first resistor connects the first node and the second node.

[0012] Optionally, the inversion signal control module includes a second transistor and a second resistor, the control end of the second transistor is connected to the first node through the second resistor, the first end of the second transistor is connected to the pull-up power supply, and the second end of the second transistor is connected to the inversion time extension module.

[0013] Optionally, the inversion signal control module includes a second transistor and a comparison unit, the first input end of the comparison unit is connected to the first node, the second input end of the comparison unit is connected to the second node, the output end of the comparison unit is connected to the control end of the second transistor, the first end of the second transistor is connected to the pull-up power supply, and the second end of the second transistor is connected to the inversion time extension module.

[0014] Optionally, the inversion signal control module includes a second transistor and an OR gate circuit, the first input end of the OR gate circuit is connected to the first node, the second input end of the OR gate circuit is connected to the second node, the output end of the OR gate circuit is connected to the control end of the second transistor, the first end of the second transistor is connected to the pull-up power supply, and the second end of the second transistor is connected to the inversion time extension module.

[0015] Optionally, the inversion time extension module includes a third transistor and a divider, the control end of the third transistor is connected to the pull-up power supply through the inversion signal control module, the first end of the third transistor is connected to the picture detection module, and the second end of the third transistor is connected to the source driver chip through the divider, or the first end of the third transistor is connected to the picture detection module through the divider, and the second end of the third transistor is connected to the source driver chip.

[0016] Optionally, the inversion time extension module also includes a frequency detection unit, a level conversion unit and a selection unit, the frequency detection unit is connected to the level conversion unit, the frequency detection unit is used to obtain the refresh frequency of the display panel, the selection unit includes a plurality of different frequency dividers and a plurality of different selection transistors, the frequency dividers correspond to the selection transistors one-to-one, the turn-on voltage of the selection transistor is positively correlated with the frequency reduction multiple of the frequency divider, the first end of the selection transistor is connected to the picture detection module through the frequency divider, the second end of the selection transistor is connected to the third transistor, the control ends of all the selection transistors are connected to the level conversion unit, and the level conversion unit is used to output a control voltage that is positively correlated with the refresh frequency.

[0017] Optionally, the level conversion unit is also connected to a reference power supply, and the control voltage V output by the level conversion unit is:

[0018] V = V0 × q × F;

[0019] Wherein, V0 is the voltage of the reference power supply, F is the refresh frequency of the display panel, and q is an adjustable proportional coefficient.

[0020] Optionally, the picture detection module includes a timing controller, the timing controller includes a waveform recognition unit, the waveform recognition unit is connected to the common electrode of the display panel and the polarity partition control module, and the waveform recognition unit is used to control the polarity partition control module to turn on the source driver chip and the pull-up power supply of the even column when the common electrode voltage exceeds a preset interval.

[0021] The present application also provides a display device, comprising:

[0022] Display panel;

[0023] The driving module is connected to the display panel.

[0024] The driving module and display device disclosed in this application have the following beneficial effects:

[0025] In the present application, the driving module includes a plurality of source driver chips, a polarity partition control module, a picture detection module, a reversal time extension module and a reversal signal control module, each source driver chip is connected to a plurality of columns of data lines of the display panel, the source driver chips of the odd columns are connected to the pull-down power supply, the polarity partition control module controls the source driver chips of the even columns to be connected to the pull-up power supply or the pull-down power supply, the picture detection module is connected to the display panel and the polarity partition control module, and is used to detect whether the display panel needs to be polarized, so that the polarity of the display area controlled by the adjacent source driver chips is symmetrical, the reversal time extension module is connected to all the source driver chips, and is used to extend the interval time of polarity reversal of the display panel, and the reversal signal control module is used to control the reversal time extension module to be turned on with the source driver chip when polarity partitioning is required. Since the obviousness of the bright line or dark line is related to the interval time of polarity reversal, when polarity partitioning is required, the interval time of polarity reversal is extended by the reversal time extension module, which can not only improve or eliminate lateral crosstalk, but also alleviate or eliminate the problem of bright and dark lines, thereby improving the display effect of the display panel.

[0026] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 It is a structural schematic diagram of the driving module in Example 1 of the present application.

[0030] Figure 2 This is a schematic diagram of the display panel in the first embodiment of the present application being in a conventional polarity mode.

[0031] Figure 3 It is a schematic diagram of the polarity symmetric mode of the display panel in the first embodiment of the present application.

[0032] Figure 4 It is a schematic diagram of the change of bright and dark lines with the refresh frequency of the display panel.

[0033] Figure 5 This is a schematic diagram of the inversion signal control module in the first embodiment of the present application being a comparison unit.

[0034] Figure 6 This is a schematic diagram of an OR gate circuit in which the inversion signal control module in the first embodiment of the present application is a circuit.

[0035] Figure 7 It is the truth table of the OR gate circuit in the first embodiment of the present application.

[0036] Figure 8 is a schematic diagram of a first inversion control signal and a second inversion control signal.

[0037] Fig. 9 Schematic diagram of the common electrode voltage waveform in Example 1 of the present application.

[0038] Fig.10 It is a schematic diagram of the structure of the display device in the second embodiment of the present application.

[0039] Description of reference numerals:

[0040] 10. Driving module; 100. Source driving chip; 200. Polarity partition control module; 210. First transistor; 220. First resistor; 300. Picture detection module; 310. Waveform recognition unit; 400. Inversion time extension module; 410. Third transistor; 420. Frequency detection unit; 430. Level conversion unit; 440. Selection unit; 441. Frequency divider; 442. Selection transistor; 500. Inversion signal control module; 510. Second transistor; 520. Second resistor; 530. Comparison unit; 540. OR gate circuit; 601. Pull-down power supply; 602. Pull-up power supply; 603. Reference power supply;

[0041] 20. Display panel; 21. First display area; 22. Second display area. DETAILED DESCRIPTION

[0042] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0043] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0044] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0045] Embodiment 1

[0046] See also Figure 1 As shown, in this embodiment, the driving module 10 is used to drive the display panel 20 to display a picture, and the driving module 10 includes a source driving chip 100, a polarity partitioning control module 200, a picture detection module 300, an inversion time extension module 400 and an inversion signal control module 500. The display panel 20 includes a plurality of rows of scan lines and a plurality of columns of data lines, and the driving module 10 includes a plurality of source driving chips 100, each of which is connected to a plurality of columns of data lines of the display panel 20, that is, a plurality of source driving chips 100 form a plurality of columns.

[0047] The source driver chips 100 of the odd columns are connected to the pull-down power supply 601, and the pull-down power supply 601 includes a ground terminal (GND); the source driver chips 100 of the even columns are connected to the pull-up power supply 602 and the pull-down power supply 601 through the polarity partition control module 200. The voltage VDD of the pull-up power supply 602 is greater than the voltage of the pull-down power supply 601. The total number of source driver chips 100 can be an odd number or an even number.

[0048] Taking column inversion as an example, the pull-down power supply 601 outputs a low-level signal to the source driver chip 100 of the odd-numbered columns, and the polarity of the first display area 21 controlled by the source driver chip 100 of the odd-numbered columns is "+-+-"; when the polarity partition control module 200 controls the source driver chip 100 of the even-numbered columns to be disconnected from the pull-up power supply 602, the pull-down power supply 601 outputs a low-level signal to the source driver chip 100 of the even-numbered columns, and the polarity of the second display area 22 controlled by the source driver chip 100 of the even-numbered columns is "+-+-", and the display panel 20 is in a conventional polarity mode, such as Figure 2 shown.

[0049] The polarity of the first display area 21 controlled by the source driver chip 100 of the odd number column remains unchanged. When the polarity partition control module 200 controls the source driver chip 100 of the even number column to be turned on with the pull-up power supply 602, the pull-up power supply 602 outputs a high level signal to the source driver chip 100 of the even number column, and the polarity of the second display area 22 controlled by the source driver chip 100 of the even number column becomes "-+-+", and the display panel 20 is in a polarity symmetric mode, such as Figure 3 shown.

[0050] The image detection module 300 is connected to the display panel 20 and the polarity partition control module 200, and is used to detect the display image of the display panel 20, and determine whether polarity partitioning is required according to the lateral crosstalk degree of the display image. When polarity partitioning is required, the image detection module 300 controls the polarity partition control module 200 to turn on the source driver chips 100 of the even columns and the pull-up power supply 602, so that the polarities of the display areas controlled by the adjacent source driver chips 100 are symmetrical, that is, the display panel 20 is in polarity symmetric mode; when polarity partitioning is not required, the image detection module 300 controls the polarity partition control module 200 to disconnect the source driver chips 100 of the even columns and the pull-up power supply 602, so that the polarities of the display areas controlled by the adjacent source driver chips 100 are the same, that is, the display panel 20 is in normal polarity mode.

[0051] In the polarity symmetry mode, the pixel voltage coupling directions of the adjacent first display area 21 and the second display area 22 are opposite, and the common voltage coupling directions of the adjacent first display area 21 and the second display area 22 are also opposite, thereby offsetting the coupling, improving or eliminating the lateral crosstalk, and achieving the purpose of improving the display effect of the display panel 20.

[0052] The inversion time extension module 400 is connected to all source driver chips 100, and is used to output the second inversion control signal P2 to the source driver chip 100, so as to extend the interval time of polarity inversion of the display panel 20. The inversion signal control module 500 is connected to the polarity partition control module 200 or the picture detection module 300, and is used to control the inversion time extension module 400 and the source driver chip 100 to be turned on when polarity partitioning is required.

[0053] In the polarity symmetry mode, the pixel voltage coupling directions of the adjacent first display area 21 and the second display area 22 are opposite, which can offset the coupling and improve or eliminate lateral crosstalk. However, the sub-pixels of the adjacent first display area 21 and the second display area 22 always have the "++" or "--" polarity and will not change. Under the effect of long-term lighting and aging, it may have a certain impact on this part of the liquid crystal. In addition, at the boundary position of the adjacent first display area 21 and the second display area 22, the polarity of the sub-pixels in the column direction is always the same, while the polarity of the sub-pixels in the same column in other areas is "+-+-" alternating, causing the sub-pixels at the boundary position to become brighter or darker than the surrounding sub-pixels, that is, forming bright lines or dark lines, affecting the display effect of the display panel 20.

[0054] The degree of visibility of the bright line or dark line is related to the refresh frequency of the display panel 20. The higher the refresh frequency of the display panel 20, the shorter the time of one frame. Since the display panel 20 performs a polarity reversal once per frame, the shorter the time of one frame and the shorter the interval of polarity reversal, the more obvious the bright line or dark line between the adjacent first display area 21 and the second display area 22 is. Figure 4 shown.

[0055] In this embodiment, the driving module 10 includes a plurality of source driving chips 100, a polarity partition control module 200, a picture detection module 300, an inversion time extension module 400 and an inversion signal control module 500. Each source driving chip 100 is connected to a plurality of columns of data lines of the display panel 20. The source driving chips 100 of the odd columns are connected to the pull-down power supply 601. The source driving chips 100 of the even columns are connected to the pull-up power supply 602 and the pull-down power supply 601 through the polarity partition control module 200. The picture detection module 300 is connected to the display panel 20 and the polarity partition control module 200, and is used to detect whether the display panel 20 is Polarity partitioning is required. When polarity partitioning is required, the image detection module 300 controls the polarity partitioning control module 200 to turn on the source driver chips 100 of the even columns and the pull-up power supply 602, so that the polarity of the display area controlled by the adjacent source driver chips 100 is symmetrical. The reversal time extension module 400 is connected to all the source driver chips 100 to extend the interval time of polarity reversal of the display panel 20. The reversal signal control module 500 is connected to the polarity partitioning control module 200 or the image detection module 300 to control the reversal time extension module 400 to be connected to the source driver chip 100 when polarity partitioning is required. Since the degree of visibility of bright lines or dark lines is related to the interval time of polarity reversal, when polarity partitioning is required, the interval time of polarity reversal is extended by the reversal time extension module 400, which can improve or eliminate lateral crosstalk, and can also alleviate or eliminate the problem of bright and dark lines, thereby improving the display effect of the display panel 20.

[0056] It should be noted that the above embodiments are only described by taking column inversion as an example, and the polarity inversion methods of the display panel 20 also include frame inversion, row inversion and dot inversion, etc. The principles of frame inversion, row inversion and dot inversion to improve or eliminate lateral crosstalk are the same as dot inversion. Therefore, the driving module 10 in the present application can also be used to drive the display panel 20 using other polarity inversion methods.

[0057] In addition, the image detection module 300 is used to detect the image displayed by the display panel 20, and determine whether polarity partitioning is required based on the degree of lateral crosstalk of the displayed image. When the display panel 20 displays special images, such as V1Line (alternating black and white columns), Excel, TXT text documents, etc., these images are more likely to generate lateral crosstalk, and polarity partitioning is required to improve or eliminate crosstalk. In other words, when the display panel 20 displays a special image, polarity partitioning is required and the interval time of polarity reversal is extended. When the display panel 20 displays an ordinary image, polarity partitioning and extension of the interval time of polarity reversal are not required. When displaying a special image, the interval time of polarity reversal is extended for a short time, which will not cause polarization of the liquid crystal molecules.

[0058] See also Figure 1 As shown, the polarity partition control module 200 includes a first transistor 210 and a first resistor 220, the control end of the first transistor 210 is connected to the picture detection module 300, the first end of the first transistor 210 is connected to the pull-up power supply 602, the second end of the first transistor 210 is connected to the source driver chip 100 of the even column through the first node C, the source driver chip 100 of the odd column is connected to the pull-down power supply 601 through the second node D, and the first resistor 220 is connected to the first node C and the second node D. The first transistor 210 can be an N-type metal oxide field effect transistor (NMOS).

[0059] When polarity partitioning is not required, the picture detection module 300 outputs a low-level signal to the control end of the first transistor 210, the first transistor 210 is turned off, the pull-down power supply 601 outputs a low-level signal to all source driver chips 100, and the display panel 20 is in a conventional polarity mode; when polarity partitioning is required, the picture detection module 300 outputs a high-level signal to the control end of the first transistor 210, the first transistor 210 is turned on, and the pull-up power supply 602 pulls the first node C to a high level, that is, the pull-up power supply 602 outputs a high-level signal to the source driver chips 100 of the even-numbered columns, and the display panel 20 is in a polarity symmetric mode.

[0060] See also Figure 1 As shown, the inversion signal control module 500 includes a second transistor 510 and a second resistor 520, the control end of the second transistor 510 is connected to the first node C through the second resistor 520, the first end of the second transistor 510 is connected to the pull-up power supply 602, and the second end of the second transistor 510 is connected to the inversion time extension module 400. The second transistor 510 can be an N-type metal oxide field effect transistor.

[0061] When polarity partitioning is not required, the pull-down power supply 601 pulls the first node C to a low level, the second transistor 510 is turned off, the inversion time extension module 400 has no control signal output, and the display panel 20 performs a polarity inversion once per frame, and the polarity inversion time remains unchanged; when polarity partitioning is required, the pull-up power supply 602 pulls the first node C to a high level, the second transistor 510 is turned on, and the inversion time extension module 400 outputs a second inversion control signal P2 to the display panel 20, extending the polarity inversion time of the display panel 20. For example, the display panel 20 performs a polarity inversion once per frame, and changes to a polarity inversion once every two frames, three frames, four frames, or eight frames.

[0062] The second transistor 510 is controlled by the voltage of the first node C, that is, when the display panel 20 switches to the polarity symmetric mode, the inversion time extension module 400 is controlled to output the second inversion control signal P2, which does not affect the normal polarity mode.

[0063] It should be noted that the second transistor 510 can be connected to the polarity partition control module 200 and controlled by the voltage of the first node C in the polarity partition control module 200, but is not limited thereto. The second transistor 510 can also be directly connected to the picture detection module 300, depending on the specific situation.

[0064] In some embodiments, the inversion signal control module 500 includes a second transistor 510 and a comparison unit 530, a first input terminal of the comparison unit 530 is connected to the first node C, a second input terminal of the comparison unit 530 is connected to the second node D, an output terminal of the comparison unit 530 is connected to the control terminal of the second transistor 510, a first terminal of the second transistor 510 is connected to the pull-up power supply 602, and a second terminal of the second transistor 510 is connected to the inversion time extension module 400, as shown in FIG. Figure 5 The comparison unit 530 includes a comparator or an operational amplifier.

[0065] When polarity partitioning is not required, the pull-down power supply 601 pulls the first node C and the second node D to a low level, the voltages of the two input terminals of the comparison unit 530 are the same, the comparison unit 530 outputs a low level signal to the control terminal of the second transistor 510, the second transistor 510 is turned off, the reversal time extension module 400 has no control signal output, and the polarity reversal time remains unchanged; when polarity partitioning is required, the pull-down power supply 601 pulls the second node D to a low level, the pull-up power supply 602 pulls the first node C to a high level, the voltages of the two input terminals of the comparison unit 530 are different, the comparison unit 530 outputs a high level signal to the control terminal of the second transistor 510, the second transistor 510 is turned on, and the reversal time extension module 400 outputs a second reversal control signal P2 to the display panel 20, thereby extending the polarity reversal time of the display panel 20.

[0066] In some embodiments, the inversion signal control module 500 includes a second transistor 510 and an OR gate circuit 540, the first input terminal A of the OR gate circuit 540 is connected to the first node C, the second input terminal B of the OR gate circuit 540 is connected to the second node D, the output terminal Y of the OR gate circuit 540 is connected to the control terminal of the second transistor 510, the first terminal of the second transistor 510 is connected to the pull-up power supply 602, and the second terminal of the second transistor 510 is connected to the inversion time extension module 400.

[0067] When polarity partitioning is not required, the pull-down power supply 601 pulls the first node C and the second node D to a low level. Figure 6 and Figure 7 As shown, when the first input terminal A and the second input terminal B of the OR gate circuit 540 are both at a low level, the output terminal Y of the OR gate circuit 540 outputs a low level signal to the control terminal of the second transistor 510, the second transistor 510 is turned off, the reversal time extension module 400 has no control signal output, and the polarity reversal time remains unchanged; when polarity partitioning is required, the pull-down power supply 601 pulls the second node D to a low level, the pull-up power supply 602 pulls the first node C to a high level, the output terminal Y of the OR gate circuit 540 outputs a high level signal to the control terminal of the second transistor 510, the second transistor 510 is turned on, and the reversal time extension module 400 outputs a second reversal control signal P2 to the display panel 20, thereby extending the polarity reversal time of the display panel 20.

[0068] See also Figure 1 and Figure 5 As shown, the inversion time extension module 400 includes a third transistor 410 and a frequency divider 441, the control end of the third transistor 410 is connected to the pull-up power supply 602 through the inversion signal control module 500, the first end of the third transistor 410 is connected to the picture detection module 300, and the second end of the third transistor 410 is connected to the source driver chip 100 through the frequency divider 441. The frequency divider 441 is used to extend the cycle of the inversion control signal output by the picture detection module 300, thereby extending the polarity inversion time of the display panel 20. The third transistor 410 can be an N-type metal oxide field effect transistor.

[0069] The inversion time extension module 400 extends the period of the first inversion control signal P1 output by the image detection module 300. The display panel 20 performs polarity inversion once in each frame, and changes it to perform polarity inversion once every two frames, four frames or eight frames. There is no need to generate an additional inversion control signal to control the polarity inversion of the display panel 20, which can reduce the manufacturing cost of the driving module 10.

[0070] It should be noted that the first end of the third transistor 410 is connected to the picture detection module 300, and the second end of the third transistor 410 is connected to the source driver chip 100 through the divider 441, but is not limited to this. The first end of the third transistor 410 can also be connected to the picture detection module 300 through the divider 441, and the second end of the third transistor 410 is connected to the source driver chip 100, depending on the specific situation.

[0071] In some embodiments, the inversion time extension module 400 further includes a frequency detection unit 420, a level conversion unit 430, and a selection unit 440. The display panel 20 has an array substrate row driving circuit (GOA), and the frequency detection unit 420 is connected to the array substrate row driving circuit (GOA), or the driving module 10 further includes a gate driving chip not shown, and the frequency detection unit 420 is connected to the gate driving chip. The array substrate row driving circuit or the gate driving chip outputs a frame start signal (STV) or a clock signal (CLK) to the frequency detection unit 420, and the frequency detection unit 420 obtains the refresh frequency of the display panel 20 according to the frame start signal or the clock signal.

[0072] The selection unit 440 includes a plurality of different frequency dividers 441 and a plurality of different selection transistors 442. The frequency dividers 441 correspond to the selection transistors 442 one by one. The turn-on voltage of the selection transistor 442 is positively correlated with the frequency reduction multiple of the frequency divider 441. The first end of the selection transistor 442 is connected to the picture detection module 300 through the frequency divider 441, the second end of the selection transistor 442 is connected to the third transistor 410, and the control ends of all the selection transistors 442 are connected to the level conversion unit 430. The level conversion unit 430 is also connected to the frequency detection unit 420. The level conversion unit 430 is used to output a control voltage that is positively correlated with the refresh frequency to control one of the selection transistors 442 to turn on. The selection transistors 442 can all be N-type metal oxide field effect transistors.

[0073] The greater the frequency reduction factor of the frequency divider 441, the greater the cycle length of the second inversion control signal P2 converted from the first inversion control signal P1, and the greater the turn-on voltage of the selection transistor 442 that controls the operation of the frequency divider 441. For example, the frequency of the first inversion control signal P1 is 120Hz, and the frequency divider 441 converts the first inversion control signal P1 into the second inversion control signal P2 with a frequency of 60Hz; the frequency of the first inversion control signal P1 is 240Hz, and another frequency divider 441 converts the first inversion control signal P1 into the second inversion control signal P2 with a frequency of 60Hz. Figure 8 shown.

[0074] The frequency reduction factor of the divider 441 in the selection unit 440 is positively correlated with the refresh frequency of the display panel 20. The higher the refresh frequency of the display panel 20, the easier it is to produce obvious bright lines or dark lines. The larger the number of polarity reversal interval frames, the more obvious bright lines or dark lines that may be produced can be eliminated, thereby improving the display effect.

[0075] It should be noted that the first transistor 210, the second transistor 510, the third transistor 410 and the selection transistor 442 may all be N-type metal oxide field effect transistors, but are not limited to this. One or more of the first transistor 210, the second transistor 510, the third transistor 410 and the selection transistor 442 may also be P-type metal oxide field effect transistors, depending on the specific circumstances.

[0076] In some embodiments, the level conversion unit 430 is also connected to the reference power supply 603, and the control voltage V output by the level conversion unit 430 is:

[0077] V = V0 × q × F;

[0078] Wherein, V0 is the voltage of the reference power supply 603, F is the refresh frequency of the display panel 20, and q is an adjustable proportional coefficient.

[0079] The proportional coefficient q can be externally modified and input, so as to facilitate setting the control voltage V for different display panels 20, thereby controlling the frequency reduction multiple of the frequency divider 441 in the selection unit 440. The selection unit 440 includes a plurality of different selection transistors 442, and the turn-on voltage range of all the selection transistors 442 can be greater than the range of the control voltage V when the proportional coefficient q is 1. When the proportional coefficient q is adjusted, the period extension range of the second inversion control signal P2 converted from the first inversion control signal P1 can be adjusted. For example, when the proportional coefficient q is 1, the second inversion control signal P2 controls the display panel 20 to perform a polarity inversion once every two or four frames, and when the proportional coefficient q is 1.5, the second inversion control signal P2 controls the display panel 20 to perform a polarity inversion once every four or eight frames.

[0080] In some embodiments, the picture detection module 300 is a timing controller (TCON), which includes a waveform recognition unit 310, which is connected to the common electrode of the display panel 20 and the polarity partition control module 200. The waveform recognition unit 310 is used to control the polarity partition control module 200 to conduct the source driver chip 100 of the even column and the pull-up power supply 602 when the common electrode voltage Vcom exceeds the preset interval. It should be noted that the picture detection module 300 can be a timing controller, but is not limited thereto. The picture detection module 300 can also be an additional detection module, which can be determined according to the specific situation.

[0081] When the pixel voltage is offset during lateral crosstalk, it will cause coupling fluctuation of the common electrode voltage Vcom, such as Fig. 9 As shown, in the waveform recognition unit 310, an interval value is set according to the common electrode voltage Vcom, that is, a positive and negative trigger value m1 and m2 are set. When it is recognized that the common electrode voltage Vcom exceeds the preset interval (greater than m1 or less than m2, indicating that the lateral crosstalk is serious and the picture effect is poor), a high-level signal is output to the source driver chip 100 of the even-numbered columns, and the display panel 20 switches to the polarity symmetric mode. The pixel voltages and common voltages of the adjacent first display area 21 and the second display area 22 are coupled in opposite directions, thereby offsetting the coupling and improving or eliminating the lateral crosstalk. On the contrary, when the common electrode voltage Vcom does not exceed the preset interval, the display panel 20 is in the normal polarity mode.

[0082] In some embodiments, the timing controller can detect the display screen and control the display panel 20 to a conventional polarity mode or a polarity symmetric mode according to the display screen. When using the timing controller to detect the display screen, some complex screens may not be detected, and the detection must be performed based on the pixel arrangement structure and number. The existing known lateral crosstalk screens may not be complete. If a new screen has lateral crosstalk later, then the pixel structure of this screen is different from the existing one, and the timing controller cannot detect it either. In addition, the lateral crosstalk phenomenon of different liquid crystals is inconsistent, and the unified setting cannot be fully compatible, which requires more debugging time.

[0083] In this embodiment, the waveform recognition unit 310 is connected to the common electrode of the display panel 20 and the polarity partition control module 200. The waveform recognition unit 310 switches the display panel 20 to a conventional polarity mode or a polarity symmetric mode according to the common electrode voltage Vcom. Compared with the solution of using a timing controller to detect the display screen, it can be generally used to detect different lateral crosstalk phenomena.

[0084] Embodiment 2

[0085] See also Fig.10 As shown, the display device in this embodiment includes the driving module 10 and the display panel 20 disclosed in the first embodiment, and the display panel 20 is connected to the source driving chip 100 of the driving module 10 .

[0086] In this embodiment, the display device includes a driving module 10, which includes a plurality of source driving chips 100, a polarity partition control module 200, a picture detection module 300, an inversion time extension module 400 and an inversion signal control module 500. Each source driving chip 100 is connected to a plurality of columns of data lines of the display panel 20, the source driving chips 100 of the odd columns are connected to the pull-down power supply 601, and the source driving chips 100 of the even columns are connected to the pull-up power supply 602 and the pull-down power supply 601 through the polarity partition control module 200. The picture detection module 300 is connected to the display panel 20 and the polarity partition control module 200, and is used to detect the display panel 20. The display panel 20 is used to determine whether polarity partitioning is required. When polarity partitioning is required, the image detection module 300 controls the polarity partitioning control module 200 to conduct the source driver chips 100 of the even columns and the pull-up power supply 602, so that the polarities of the display areas controlled by the adjacent source driver chips 100 are symmetrical. The reversal time extension module 400 is connected to all the source driver chips 100 to extend the interval time of polarity reversal of the display panel 20. The reversal signal control module 500 is connected to the polarity partitioning control module 200 or the image detection module 300 to control the reversal time extension module 400 to conduct with the source driver chip 100 when polarity partitioning is required. Since the degree of visibility of bright lines or dark lines is related to the interval time of polarity reversal, when polarity partitioning is required, the interval time of polarity reversal is extended by the reversal time extension module 400, which can improve or eliminate lateral crosstalk, and can also alleviate or eliminate the problem of bright lines or dark lines, thereby improving the display effect of the display device.

[0087] The terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0088] In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0089] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0090] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A driving module, comprising a plurality of source driving chips, each of which is connected to a plurality of columns of data lines of a display panel, characterized in that: The driving module also includes: A polarity partition control module, wherein the source driver chips of the odd columns are connected to a pull-down power supply, and the source driver chips of the even columns are connected to a pull-up power supply and the pull-down power supply through the polarity partition control module, and the pull-down power supply includes a ground terminal; A picture detection module connected to the display panel and the polarity partition control module, used to detect whether the display panel needs to be polarized, and when polarity partition is needed, control the polarity partition control module to turn on the source driver chips and the pull-up power supply of the even-numbered columns, so that the polarities of the display areas controlled by the adjacent source driver chips are symmetrical; A reversal time extension module, connected to all the source driver chips, for extending the interval time of polarity reversal of the display panel; The inversion signal control module is connected to the polarity partition control module or the picture detection module, and is used to control the inversion time extension module to be turned on with the source driver chip when polarity partition is required.

2. The driving module according to claim 1, characterized in that: The polarity partition control module includes a first transistor and a first resistor, the control end of the first transistor is connected to the picture detection module, the first end of the first transistor is connected to the pull-up power supply, the second end of the first transistor is connected to the source driver chip of the even column through a first node, the source driver chip of the odd column is connected to the pull-down power supply through a second node, and the first resistor connects the first node and the second node.

3. The driving module according to claim 2, characterized in that: The inversion signal control module includes a second transistor and a second resistor, the control end of the second transistor is connected to the first node through the second resistor, the first end of the second transistor is connected to the pull-up power supply, and the second end of the second transistor is connected to the inversion time extension module.

4. The driving module according to claim 2, characterized in that: The inversion signal control module includes a second transistor and a comparison unit, wherein a first input end of the comparison unit is connected to the first node, a second input end of the comparison unit is connected to the second node, an output end of the comparison unit is connected to a control end of the second transistor, a first end of the second transistor is connected to the pull-up power supply, and a second end of the second transistor is connected to the inversion time extension module.

5. The driving module according to claim 2, characterized in that: The inversion signal control module includes a second transistor and an OR gate circuit, wherein a first input end of the OR gate circuit is connected to the first node, a second input end of the OR gate circuit is connected to the second node, an output end of the OR gate circuit is connected to a control end of the second transistor, a first end of the second transistor is connected to the pull-up power supply, and a second end of the second transistor is connected to the inversion time extension module.

6. The driving module according to claim 1, characterized in that: The inversion time extension module includes a third transistor and a frequency divider, the control end of the third transistor is connected to the pull-up power supply through the inversion signal control module, the first end of the third transistor is connected to the picture detection module, the second end of the third transistor is connected to the source driver chip through the frequency divider, or the first end of the third transistor is connected to the picture detection module through the frequency divider, and the second end of the third transistor is connected to the source driver chip.

7. The driving module according to claim 6, characterized in that: The inversion time extension module also includes a frequency detection unit, a level conversion unit and a selection unit. The frequency detection unit is connected to the level conversion unit. The frequency detection unit is used to obtain the refresh frequency of the display panel. The selection unit includes a plurality of different frequency dividers and a plurality of different selection transistors. The frequency dividers correspond to the selection transistors one by one. The turn-on voltage of the selection transistor is positively correlated with the frequency reduction multiple of the frequency divider. The first end of the selection transistor is connected to the picture detection module through the frequency divider, the second end of the selection transistor is connected to the third transistor, and the control ends of all the selection transistors are connected to the level conversion unit. The level conversion unit is used to output a control voltage positively correlated with the refresh frequency.

8. The driving module according to claim 7, characterized in that: The level conversion unit is also connected to a reference power supply, and the control voltage V output by the level conversion unit is: V = V0 × q × F; Wherein, V0 is the voltage of the reference power supply, F is the refresh frequency of the display panel, and q is an adjustable proportional coefficient.

9. The driving module according to claim 1, characterized in that: The picture detection module includes a timing controller, which includes a waveform recognition unit. The waveform recognition unit is connected to the common electrode of the display panel and the polarity partition control module. The waveform recognition unit is used to control the polarity partition control module to turn on the source driver chip and the pull-up power supply of the even column when the common electrode voltage exceeds a preset interval.

10. A display device, characterized in that: include: Display panel; The driving module according to any one of claims 1 to 9, connected to the display panel.

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