Memory module and operating method of controller of memory module

Abstract

The invention discloses a memory module and an operating method of a controller of the memory module. An example CXL (Computing Fast Link)-based memory module includes a memory device and a controller. The memory device includes a plurality of volatile memory cells, and stores data or reads stored data. The controller communicates with the host device through the CXL interface and controls the memory device. The controller includes: an error correction code (ECC) circuit generating a first codeword by adding a parity check vector generated based on Reed-Solomon encoding to data received from a host device; an error injection circuit generating an error symbol and generating a second codeword by injecting the error symbol into at least a portion of the first codeword; and a memory device interface that controls the memory device such that the second codeword into which the error symbol is injected is stored in the memory device. The controller determines a number of error symbols injected into the second codeword.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0097628 filed on July 26, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0153770 filed on November 8, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a memory module and an operating method of a controller of the memory module. Background Art

[0003] Semiconductor memory devices are used to store data, and are classified as volatile memory devices or nonvolatile memory devices.

[0004] A volatile memory device, such as a dynamic random access memory (DRAM), is provided with data to be stored from a host device. The data received from the host device may be poisoned data. For example, the reliability of the data may be questionable due to an error in a cache memory of the host device or in an internal data transmission path of the host device. In this case, the host device may send additional information reporting data poisoning along with the data to be sent to the DRAM for storage in the DRAM. For example, a poisoning flag may be sent along with the poisoned data.

[0005] When receiving a read request for poisoned data from a host device, the volatile memory device sends a poison flag together. For this reason, the volatile memory device manages the data together with the poison flag. Therefore, it is desirable that a volatile memory device with high integration effectively manages the poison flag. Summary of the invention

[0006] The present disclosure relates to a semiconductor memory device capable of effectively managing a poisoning flag.

[0007] In some embodiments, a memory module based on CXL (Compute Express Link) may include a memory device and a controller; the memory device includes a plurality of volatile memory cells and stores data or reads stored data; the controller communicates with a host device through a CXL interface and controls the memory device. The controller may include: an error correction code (ECC) circuit that generates a first codeword by adding a parity check vector generated based on Reed-Solomon encoding to data received from the host device; an error injection circuit that generates an error codeword and generates a second codeword by injecting the error codeword into at least a portion of the first codeword; and a memory device interface that controls the memory device so that the second codeword injected with the error codeword is stored in the memory device, and the controller may variably determine the number of error codewords.

[0008] In some embodiments, an operating method of a controller for controlling a memory device may include: receiving, at the controller, an instruction for storing data from a host device together with a poison flag through a CXL (Compute Quick Link) interface, adding, at the controller, a parity check vector generated based on Reed-Solomon (RS) encoding to data received from the host device to generate a first codeword, at the controller, injecting at least one error codeword into at least a portion of the first codeword to generate a second codeword, and controlling the memory device at the controller so that the second codeword into which the at least one error codeword is injected is stored, and the number of the at least one error codeword can be variably determined.

[0009] In some embodiments, a computing device may include: a central processing unit (CPU) that performs computing; a memory device that includes a plurality of volatile memory cells; and a controller that communicates with the central processing unit through a CXL (Compute Express Link) interface and controls the memory device based on a command and an address sent by the central processing unit. The memory device may store data in the memory cell or read data from the memory cell under the control of the controller, and the controller may determine the number of error code elements based on the address, and may inject the error code elements into at least a portion of a code word generated based on received data received from the central processing unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating an example of a memory module.

[0012] Figure 2 is a block diagram illustrating an example of a memory controller.

[0013] Figure 3 is a block diagram illustrating an example of a memory controller.

[0014] Figure 4 : is a diagram describing an example erasure table in which erasure information is recorded.

[0015] Figure 5A , Figure 5B and Figure 5C is an example diagram describing the injection of error code elements.

[0016] Figure 6 is a block diagram showing a configuration of an example of an error correction code (ECC) circuit.

[0017] Figure 7 is an example diagram showing a poisoning flag and an uncorrectable error (UE) flag.

[0018] Figure 8 is a diagram illustrating an example of a storage device.

[0019] Fig. 9 It is shown Figure 8 An example diagram of a portion of a memory bank array.

[0020] Fig.10 is a diagram showing an example of a configuration of an on-die ECC engine.

[0021] Fig.11 is a flowchart illustrating an example of the operation of a controller that controls a memory module.

[0022] Fig.12 is a flow chart illustrating an example of an operation in which a controller controlling a memory module sets a poison flag and a UE flag. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will be described in detail and clearly to the extent that a person having ordinary skill in the art can easily implement the present disclosure.

[0024] Figure 1 is a block diagram illustrating an example of a memory module.

[0025] The memory module 10 may store poisoned data received from the host device in the memory device 200. When the poisoned data is read from the memory device 200, the memory module 10 may manage the poisoning information so that the controller 100 can check whether the read data is poisoned data. The memory module 10 may effectively store the poisoning information in the memory device 200 without using additional storage space. To this end, the controller 100 may inject an error symbol into at least a portion of a codeword obtained by performing error correction code (ECC) encoding on the data received from the host device. The codeword injected with the error symbol may be sent to the memory device 200 to be stored in the memory device 200. Therefore, no additional storage space is required to store the poisoning information. In addition, the controller 100 may inject an error symbol that allows the error range (or error level) to exceed the error correction capability of the error correction circuit, so that when the poisoned data is read, the poisoned data may not be lost due to mis-correction of the controller 100. The controller 100 may inject error symbols whose number is adaptively changed into the codeword so as not to cause miscorrection. That is, the number of error symbols injected into the codeword may be variably determined.

[0026] Will refer to Figure 1 Give a detailed description. Figure 1 , the memory module 10 may include a controller 100 and a memory device 200 .

[0027] The memory module 10 may be a CXL (Compute Express Link) DRAM device. For example, the memory module 10 may be connected to a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence (AI) accelerator, a storage device, etc. of a host device based on a PCIe (Peripheral Component Interconnect Express) interface. The memory module 10 may support a cache coherent interconnect.

[0028] The controller 100 may control the memory device 200. For example, the controller 100 may control the memory device 200 according to a request of a processor supporting various applications such as server applications, personal computer (PC) applications, and mobile applications. The controller 100 may communicate with a host device including a processor by using a CXL protocol, and may control the memory device 200 according to a request of the processor. For example, the controller 100 may communicate with the host device on a PCIe bus based on a CXL.IO protocol, and may control the memory device 200 based on a CXL.Memory protocol.

[0029] The controller 100 and the memory device 200 may be implemented in one package. Alternatively, the controller 100 and the memory device 200 may communicate with each other on the same bus connected to a host device, and may be implemented in different packages.

[0030] In order to control the memory device 200, the controller 100 may transmit a command and / or an address to the memory device 200. In addition, the controller 100 may transmit data to the memory device 200 or may receive data from the memory device 200. The data may be a codeword CW.

[0031] The memory device 200 may receive a codeword from the controller 100 and may store the codeword thus received. The memory device 200 may read the stored codeword in response to a request of the controller 100, and may send the read data to the controller 100. For example, the memory device 200 may be configured to receive a command and / or an address from the controller 100, access an area of ​​the memory cell array 220 selected by the address, and perform an operation indicated by the command for the selected area. For example, the memory device 200 may perform a write operation, a read operation, and an erase operation.

[0032] In some embodiments, the memory device 200 may include a volatile memory cell. For example, the memory device 200 may include various DRAM devices (such as double data rate synchronous dynamic random access memory (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR4X SDRAM, LPDDR5 SDRAM, graphic double data rate synchronous graphic random access memory (GDDR SGRAM), GDDR2 SGRAM, GDDR3 SGRAM, GDDR4 SGRAM, GDDR5 SGRAM, and GDDR6 SGRAM).

[0033] Furthermore, in some embodiments, the memory device 200 may be a stacked memory device in which DRAM dies are stacked (such as high bandwidth memory (HBM), HBM2, or HBM3).

[0034] Furthermore, in some embodiments, the memory device 200 may include an SRAM device, a NAND flash memory device, a NOR flash memory device, a resistive random access memory (RRAM) device, a ferroelectric random access memory (FRAM) device, a phase change random access memory (PRAM) device, a tunneling random access memory (TRAM) device, a magnetic random access memory (MRAM) device, etc.

[0035] The memory device 200 may include a control logic circuit 210 and a memory cell array 220 .

[0036] The control logic circuit 210 may control the operation of the memory device 200. For example, the control logic circuit 210 may generate a control signal so that the memory device 200 performs a write operation or a read operation.

[0037] The memory cell array 220 may include a plurality of memory banks, each memory bank including a memory cell for storing data. For ease of description, it is assumed in the specification that each memory bank includes a DRAM cell. However, this is provided as an example, and in addition to the DRAM cell, each of the plurality of memory banks may be implemented to include any other volatile memory cell. In addition, the plurality of memory banks may be implemented to include the same type of memory cells, or may be implemented to include different types of memory cells.

[0038] The controller 100 may include an ECC circuit 110 , an error injection circuit 120 , and a memory module interface 130 .

[0039] The ECC circuit 110 may add parity information to data received from the host device. For example, the ECC circuit 110 may perform ECC encoding on the received data to generate a parity vector PRT in which parity information is composed of parity symbols, and may add the generated parity vector PRT to the data DT to generate a first codeword CW1. In some embodiments, the ECC circuit 110 may perform ECC encoding based on a Reed-Solomon (RS) code.

[0040] The error injection circuit 120 may inject the error symbol ER_SYM into the first codeword CW1 to record poisoning information at the first codeword CW1 generated by the ECC circuit 110. The error injection circuit 120 may generate the second codeword CW2 injected with the error symbol ER_SYM by injecting the error symbol ER_SYM into at least a portion of the area of ​​the first codeword CW1 where the data DT is recorded, or into at least a portion of the area of ​​the first codeword CW1 where the parity check vector PRT is recorded. In some embodiments, the error injection circuit 120 may inject the error symbol ER_SYM into the first codeword CW1 in response to a flag value of a poison flag PF sent by a host device. For example, when the poison flag PF together with the data is set by the host device (e.g., set to "1"), the error injection circuit 120 may inject the error symbol ER_SYM into the first codeword CW1.

[0041] The memory module interface 130 may send a command CMD, an address ADDR, and a second codeword CW2 to the memory device 200. The command CMD may indicate writing the second codeword CW2 into the memory cell array 220, and the address ADDR may be a page address of the memory cell array 220 to which the second codeword CW2 is to be written.

[0042] The ECC circuit 110 may perform ECC decoding on a codeword read from the memory device 200 in response to a read command of a host device.

[0043] When the read codeword is the second codeword CW2 into which the error codeword ER_SYM is injected, the ECC circuit 110 may determine whether the error codeword ER_SYM is injected. When it is determined that the error codeword ER_SYM is injected into the second codeword CW2 thus read, the ECC circuit 110 may generate a set (i.e., set to "1") poison flag PF. The controller 100 may send the set poison flag PF to the host device together with the data decoded from the second codeword CW2. In some embodiments, when the ECC decoding result of the second codeword CW2 into which the error codeword ER_SYM is injected indicates that an uncorrectable error (UE) has occurred, the controller 100 may determine that the error codeword ER_SYM is injected into the second codeword CW2.

[0044] The error injection circuit 120 may adaptively determine the number of error symbols ER_SYM to be injected into the first codeword CW1. That is, the number of error symbols ER_SYM may be variable. For example, the error injection circuit 120 may determine the number of error symbols that allow the error range (or error level) to exceed the error correction capability associated with performing ECC decoding of the ECC circuit 110.

[0045] For example, the ECC circuit 110 may perform decoding based on the RS code. In detail, the ECC circuit 110 may correct the codeword based on error-and-erasure decoding using erasure information.

[0046] In the case of a finite field or Galois field GF (2 m In the Reed-Solomon (RS) algorithm defined by , a code element consists of m bits and the maximum code length is (2 m -1), the correction capability associated with "P" which is the number of parity check symbols has a floor function value of P / 2. For example, assuming that by GF(2 8 ) defined by , the codeword consists of 8 bits, the number of data codewords is 32, and the number of parity codewords is 8. In this case, when error-only decoding is used, any 4 error codewords within the codeword length of 40 can be corrected. However, when error and erasure decoding using error and erasure information is used, the maximum number of correctable codewords increases to 6 (i.e., 4 erasure codewords and 2 error codewords).

[0047] For example, when using GF(2 8 ) defined by Reed-Solomon (RS) (K=32 and P=8), a codeword into which 3 error symbols are injected to store poisoning information may be written into the memory device 200, and a symbol error in a correctable range may occur in the read codeword. In this case, unlike the intention of injecting the error symbol ER_SYM after ECC encoding, an erroneous correction of a correctable error (CE) indicating that the ECC decoding result has occurred may be caused. Therefore, a cleared poison flag (i.e., set to "0") indicating that the data to be sent is not poisoned data may be sent to the host device. In this case, there may be a possibility of system freeze occurring at the host device.

[0048] In the case of performing error decoding based on RS code, the error injection circuit 120 may inject “amount of which is or more (P is the number of parity check symbols)" error symbols to record poisoning information. In some embodiments, as a floor function Output the largest integer less than or equal to R.

[0049] Specifically, in the case of using error and erasure decoding, since erasure information as advance information about symbol errors is given, a larger number of errors can be corrected compared to error decoding. Therefore, the probability of occurrence of miscorrection increases.

[0050] When the ECC circuit 110 performs error and erasure decoding based on the RS code, the error injection circuit 120 may inject error symbols to record poisoning information, and the number of error symbols varies according to the amount of erasure information.

[0051] Therefore, unlike the conventional method of injecting a uniform number of error symbols, the memory module 10 can solve the problem that poisoning information is not maintained due to miscorrection in the process of performing ECC decoding. Even in error and erasure decoding using erasure information, poisoning information can be prevented from being removed due to miscorrection. That is, the memory module 10 can inject error symbols "whose number is adaptively changed to exceed the error correction capability range of the ECC circuit 110" into the codeword, and therefore, the ability to maintain the codeword in which the poisoning information is recorded can be improved. That is, the number of error symbols injected into the codeword can be variably determined.

[0052] Figure 2 is a block diagram illustrating an example of a controller. Figure 2 The controller 100a can be connected with Figure 1 The controller 100 corresponds to the controller 100. Figure 1 and Figure 2The controller 100 a is described. The controller 100 a may be a CXL memory controller that performs communication based on the CXL protocol.

[0053] Reference Figure 2 , the controller 100 a may include an I / O interface 410 , a central processing unit (CPU) 420 , a direct memory access (DMA) interface 430 , a clock and reset generator 440 , a double data rate (DDR) subsystem 450 , and the CXL subsystem 300 .

[0054] The I / O interface 410 is a communication interface for performing communication with an external peripheral device. According to some embodiments, the I / O interface 410 may be a UART (Universal Asynchronous Receiver / Transmitter) interface, a JTAG (Joint Test Action Group) slave interface, a GPIO (General Purpose Input / Output) interface, an SPI (Serial Peripheral Interface) master interface, an I3C master interface, etc.

[0055] The CPU 420 may control the overall operation of the controller 100 a .

[0056] DMA interface 430 performs external peripheral device Figure 1 Direct access to the memory device 200.

[0057] The clock and reset generator 440 may generate a clock and may provide the generated clock to the DDR subsystem 450. Figure 1 A memory device 200 is provided.

[0058] DDR subsystem 450 may include a DDR4 and / or DDR5 controller, a DDR4 and / or DDR5 physical layer, and a phase-locked loop (PLL). DDR subsystem 450 may interface with Figure 1 The DDR subsystem 450 may be a Figure 1 The memory module interface 130 is provided.

[0059] The CXL subsystem 300 may include a CXL controller 320 , a PCIe physical layer (PHY) 330 , and a memory controller 500 .

[0060] The CXL subsystem 300 may communicate with a host device or any other CXL device on a PCIe bus according to a CXL protocol through the PCIe physical layer 330. The CXL protocol may be a CXL.IO protocol.

[0061] The CXL controller 320 may communicate with the memory controller 500, and may provide interfaces of the CXL transaction layer and the CXL link layer to the memory controller 500. In addition, the CXL controller 320 may provide interfaces of the PCIe transaction layer and the PCIe data link layer to the memory controller 500. The CXL controller 320 may transmit a response of the memory controller 500 to the PCIe physical layer 330, and may provide a message received from a host device or any other CXL device through the PCIe physical layer 330 to the memory controller 500.

[0062] The CXL controller 320 can communicate with the DDR subsystem 450 through Figure 1 The memory device 200 associated with the memory controller 500 sends a message (eg, command and address) to the Figure 1 A memory device 200 is provided.

[0063] The memory controller 500 may include an ECC circuit 510, erasure information 520, an error injection circuit 530, and a BIST (built-in self-test) logic 540. The ECC circuit 510 and the error injection circuit 530 may correspond to Figure 1 The ECC circuit 110 and the error injection circuit 120 are provided.

[0064] The ECC circuit 510 may receive data from the host device through the CXL controller 320, may perform ECC encoding on the received data to generate parity information, and may add the generated parity information to the received data to generate a codeword. For example, the ECC circuit 510 may generate the parity information by performing ECC encoding based on a Reed-Solomon (RS) code.

[0065] In some embodiments, the ECC circuit 510 may receive data and a poison flag from a host device. The ECC circuit 510 may provide the generated codeword and the poison flag to the error injection circuit 530. According to some embodiments, the poison flag may be provided to the error injection circuit 530 directly from the CXL controller 320. In addition, according to some embodiments, the ECC circuit 510 may check the poison flag; when the poison flag is a cleared poison flag, the ECC circuit 510 may provide the codeword to the memory device 200.

[0066] In response to the poisoning flag, the error injection circuit 530 may inject an error symbol into the codeword provided from the ECC circuit 510. The error injection circuit 530 may inject an error symbol “whose number is adaptively changed to exceed the error correction capability range of the ECC circuit 510” into the codeword. For example, when the ECC circuit 510 performs error decoding based on the RS code, the error injection circuit 530 may inject an error symbol “whose number is When the ECC circuit 510 performs error and erasure decoding based on the RS code, the error injection circuit 530 may determine the number of error symbols based on the erasure information to record the poisoning information, may generate an error vector by using the error symbols of the number determined thereby, and may add the generated error vector to the codeword. The error injection circuit 530 may provide the codeword to which the error vector is added to the memory device 200 to write the codeword to which the error vector is added.

[0067] The ECC circuit 510 may determine whether the codeword provided from the memory device 200 is a codeword into which error information is injected. The ECC circuit 510 may determine the codeword into which error information is injected by comparing a syndrome generated based on the codeword with a syndrome generated based on an error vector. When the codeword is a codeword into which error information is injected, the ECC circuit 510 may set a poison flag (e.g., the poison flag may be set to "1"). The controller 100a may send the set poison flag to the host device together with the data. Optionally, the controller 100a may send only information including the poison flag to the host device as a response to a data read request. According to some embodiments, the controller 100a may send a set UE flag to the host device together with the poison flag.

[0068] The ECC circuit 510 may correct an error by decoding a codeword provided from the memory device 200. The ECC circuit 510 may perform error decoding based on an RS code, or may perform error and erasure decoding based on an RS code.

[0069] In some embodiments, the erasure information 520 may be generated based on information about a test operation performed before production of the memory module is completed. In some embodiments, the erasure information 520 may be updated by the BIST logic 540 at each initial operation of the memory module.

[0070] The BIST logic 540 may store the erasure information 520 in a memory. The erasure information 520 may be stored in a read-only memory (ROM) of the controller 100 a. The erasure information 520 stored in the ROM may be loaded into a static RAM (SRAM) of the controller 100 a and may be used by the ECC circuit 510 and / or the error injection circuit 530.

[0071] The BIST logic 540 may be implemented using the BIOS (Basic Input Output System) of the controller 100a, or may be implemented using a single logic circuit. The BIST logic 540 may be enabled in the initial operation of the memory module, and may detect errors in each cell of the memory device 200. The BIST logic 540 may store the erase information 520 including the location and number of cells where errors are detected in the form of an erase table in the ROM. In some embodiments, when a VRT (Variable Retention Time) defect is detected, the BIST logic 540 may determine the defective cell by the following processes: 1) applying power to the memory device 200 so that the memory device 200 is initialized, 2) filling all cells with charge, 3) changing the cell refresh time so that errors are forced to appear in the cell, and 4) reading the cell data. In addition, the BIST logic 540 may detect cell errors caused by wear and degradation by various cell defect algorithms.

[0072] Therefore, refer to Figure 2 The controller 100a described can determine the number of error symbols so that the error range (or error level) exceeds the error correction capability range of the ECC circuit 110 associated with performing ECC decoding, thereby accurately identifying the codeword injected with error information without the possibility of miscorrection even in the case where the codeword injected with error information is read from the memory device 200. In addition, even in the case where the ECC circuit 510 performs error and erasure decoding based on the RS code, the controller 100a can determine the number of error symbols without the possibility of miscorrection by using the erasure information stored in advance.

[0073] Figure 3 is a block diagram showing an example of a memory controller 500a. The memory controller 500a may be connected to Figure 2 The memory controller 500 corresponds to the memory controller 500. Figure 2 Additional descriptions that are the same or similar are given to avoid redundancy.

[0074] Reference Figure 3 , the memory controller 500a may include an ECC circuit 510a, erase information 520a, an error injection circuit 530a, and a BIST logic 540a.

[0075] The ECC circuit 510a may receive the poison flag PF and the data DT to be written into the memory device 200 from the host device through the CXL controller 320a. The ECC circuit 510a may perform ECC encoding on the data DT to generate parity information, and may add the parity information to the data DT to generate the first codeword CW1. The ECC encoding may be an encoding based on an RS code. When the ECC circuit 510a performs encoding based on an RS code, the parity information may be a parity vector composed of a plurality of parity codewords. The first codeword CW1 may be composed of a parity codeword and a data codeword obtained by encoding the data DT. The ECC circuit 510a may provide the first codeword CW1 thus generated to the error injection circuit 530a. According to some embodiments, when the poison flag PF provided from the host device is a cleared poison flag PF, the ECC circuit 510a may directly provide the first codeword CW1 to the memory device 200.

[0076] The BIST logic 540a may be enabled in the initial operation of the memory module, and may detect errors in each cell of the memory device 200. In some embodiments, the BIST logic 540a may be repeatedly enabled in each initial operation of the memory module. Whenever the BIST logic 540a is enabled, the BIST logic 540 may record the error information EI of the cell "determined to be an error cell in the ROM" as the erasure information 520a. Therefore, the erasure information 520a may be updated in each initial operation of the memory module.

[0077] When the ECC circuit 510a performs error and erasure decoding based on the RS code, the error injection circuit 530a can determine the number of error code elements that "allow the error range (or error level) to exceed the error correction capability of the ECC circuit 510a associated with the error and erasure decoding" based on the pre-stored erasure information 520a.

[0078] The error injection circuit 530 a may include an error symbol number calculator 531 , an error vector generator 532 , and an error injection codeword generator 533 .

[0079] The error symbol number calculator 531 may determine the number of error symbols for which the "allowable error range (or error level) exceeds the error correction capability of the ECC circuit 510a associated with error and erasure decoding" with reference to the erasure count No. of ES of the erasure information 520a. For example, when the ECC circuit 510a performs error and erasure decoding based on the RS code, the error symbol number calculator 531 may determine the number of error symbols as or more (P is the number of parity symbols, N_Erasure is the number of erasures). In this case, the number of error symbols may be proportional to the number of parity symbols (expressed as "P"); as the erasure count No. of ES (i.e., N_Erasure) included in the erasure information 520a increases, the number of error symbols may decrease. In addition, the number of error symbols may be less than the number of parity symbols (expressed as "P").

[0080] The error vector generator 532 may generate an error vector based on the number of error symbols thus determined. The length (or size) of the error vector may be equal to the length (or size) of the first codeword CW1, or may be equal to the length of the parity check vector added to the first codeword CW1. The error vector generator 532 may inject as many non-zero valued symbols as the number of determined error symbols at a specific position of the error vector, and may inject zero-valued symbols into the remaining symbols of the error vector. The non-zero value may be pre-set in the ROM. In some embodiments, when the number of error symbols is multiple, the error symbols may include the same non-zero value. In some embodiments, the error symbols may be injected at a symbol position that does not correspond to the erase position of the erasure information 520a among the multiple symbol positions of the error vector.

[0081] The error injection codeword generator 533 may generate the second codeword CW2 by injecting the error vector generated by the error vector generator 532 into the first codeword CW1 provided from the ECC circuit 510a. The injection of the error vector may be achieved by an addition operation of the first codeword CW1 and the error vector in units of codewords. The error injection codeword generator 533 may provide the second codeword CW2 thus generated to the memory module.

[0082] Figure 4 is a diagram describing an example erasure table in which erasure information is recorded. Figure 2 Erasure information 520 and / or Figure 3 The erasure information 520a can be recorded in the erasure table. Figure 1 , Figure 2 , Figure 3 and Figure 4 Describe the erase table.

[0083] The erase table may be stored in ROM and may be loaded into the SRAM of the controller at the initial operation of the memory module.

[0084] The erase table may include memory addresses, erase locations, and erase quantities.

[0085] In some implementations, the memory address may be Figure 1 The physical address of the memory device 200. Figure 4An example showing that the memory address of the erase table is a physical address of the memory device 200. For example, the physical address of the memory device 200 may be a starting address of a memory block. In some embodiments, the memory address may be a starting address of a cache line of an SRAM of a host device. For example, when a specific block address of a cache of a host device is set to correspond to a block address of a memory device, or when a specific set of caches of a host device is set to correspond to a block address of a memory device, a cache line (or cache block) is associated with a physical address of the memory device. Therefore, the memory address of the erase table may be set based on a cache line.

[0086] The erase position may be the erased position information in the memory block or cache block of the corresponding memory address. The erased position information may be in units of code elements. For example, when the memory address is the starting address of a specific memory block (e.g., 0x001FFFFF), the erase position may represent the position of the code element corresponding to the unit with an error among all the code elements that can be stored in the relevant block. Therefore, in the case where the erase positions are 1 and 3, when all the code elements that can be stored in the memory block with the starting address of "0x001FFFFF" are "0" to "n" in sequence, the units corresponding to the second code element and the fourth code element may correspond to the erase position.

[0087] The erase count indicates the erase count existing in the memory device corresponding to the memory address.

[0088] When decoding a codeword, Figure 1 The ECC circuit 110, Figure 2 The ECC circuit 510 and Figure 3 The ECC circuit 510a may perform error and erasure decoding with reference to an erased location corresponding to a memory address from which a codeword is read.

[0089] Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a can determine the number of error code elements to be injected into the codeword by referring to the number of erases corresponding to the memory address requested to be written from the host device. In addition, Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a may refer to the erased position corresponding to the memory address requested to be written, and inject an error symbol at a position of the error vector that is not the erased position.

[0090] Figure 5A , Figure 5B and Figure 5Cis an example diagram describing the injection of error code elements. The injection of error code elements can be Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a is executed. Figure 4 and FIG. 5A to FIG. 5C Describe the injection of error symbols. Under the assumption that ECC coding is based on Reed-Solomon (RS) code decoding in symbol units, refer to Figure 4 and FIG. 5A to FIG. 5C Give a description.

[0091] Figure 1 The ECC circuit 110, Figure 2 The ECC circuit 510 and Figure 3 The ECC circuit 510a may generate a parity vector 612 / 622 / 632 including parity information by performing ECC encoding on data 611 / 621 / 631 requested by the host device to be written to the memory device. Figure 1 The ECC circuit 110, Figure 2 The ECC circuit 510 and Figure 3 The ECC circuit 510a can generate a first codeword CW1 by adding a parity check vector 612 / 622 / 632 to the data 611 / 621 / 631. FIG. 5A to FIG. 5C The example shown in Figure 1 The ECC circuit 110, Figure 2 The ECC circuit 510 and Figure 3 The ECC circuit 510a may generate encoded data by encoding the data 611 / 621 / 631. Figure 1 The ECC circuit 110, Figure 2 The ECC circuit 510 and Figure 3 The ECC circuit 510a may generate a first codeword CW1 by adding a parity check vector 612 / 622 / 632 to the encoded data.

[0092] Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a can refer to Figure 4 The number of error code elements is determined by the number of erasures in the erasure table. FIG. 5A to FIG. 5C An example in which the number of error symbols is 2 is described.

[0093] Reference Figure 5A , refer to Figure 4 The erase position of the erase table, Figure 1 The error injection circuit 120, Figure 2The error injection circuit 530 and Figure 3 The error injection circuit 530a may inject a non-zero valued error symbol at a position of the error vector 613 that does not correspond to an erasure position. Figure 5A An example is shown in which the number of erasures is 2 and the erasure positions include a first position 611_1 and a second position 611_2. Figure 5A An example is shown in which the number of error symbols is 2. When the erasure position corresponds to two positions among the positions of the data 611, reference is made to Figure 5A A description is given. However, since the second codeword CW2 into which the error symbol is injected is transmitted to the memory device and stored in the data area, the erasure positions may correspond to some positions of the parity check vector 612. Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a may generate an error vector 613 whose length is equal to the length of the first codeword CW1. Non-zero-valued error symbols may be injected at positions 614_1 and 614_2 that "do not correspond to the first position 611_1 and the second position 611_2 that are erasure positions" of the generated error vector 613, respectively. Zero-valued symbols may be injected into the remaining symbols of the error vector 613. Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a can generate the second codeword CW2 injected with the error codeword by performing an addition operation on the generated error vector 613 and the first codeword CW1 in units of codewords. Figure 5A , the second codeword CW2 may include data 616 and a parity check vector 615. Therefore, the values ​​of the symbols 617_1 and 617_2 corresponding to the positions 614_1 and 614_2 of the error symbols among the symbols of the second codeword CW2 may be determined by adding the first codeword CW1 and the error vector 613. In this case, the remaining symbols among the symbols of the second codeword CW2 that do not correspond to the positions 614_1 and 614_2 of the error symbols may be the same as the remaining symbols of the first codeword CW1.

[0094] Reference Figure 5B , Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a may inject a non-zero valued error symbol at a position of the error vector 623 “corresponding to a position of the parity check vector 622 of the first codeword CW1 ”. Figure 5B An example in which the number of error symbols is 2 is shown. Figure 1 The error injection circuit 120, Figure 2The error injection circuit 530 and Figure 3 The error injection circuit 530a may generate an error vector 623 whose length is equal to the length of the first codeword CW1. Non-zero-valued error symbols may be injected at positions 624_1 and 624_2 "corresponding to the positions of the parity check vector 622 of the first codeword CW1" of the generated error vector 623, respectively. Zero-valued symbols may be injected into the remaining symbols of the error vector 623. Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a can generate the second codeword CW2 injected with the error codeword by performing an addition operation on the generated error vector 623 and the first codeword CW1 in units of codewords. Figure 5B , the second codeword CW2 may include data 625 and a parity check vector 627. Therefore, the values ​​of the symbols 626_1 and 626_2 “corresponding to the positions 624_1 and 624_2 of the error symbols” among the symbols of the second codeword CW2 may be determined by adding the first codeword CW1 and the error vector 623. In this case, the remaining symbols “not corresponding to the positions 624_1 and 624_2 of the error symbols” among the symbols of the second codeword CW2 may be the same as the remaining symbols of the first codeword CW1.

[0095] Reference Figure 5C , Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a may generate an error vector 633 whose length is equal to the length of the parity check vector 632 of the first codeword CW1. Figure 5C An example in which the number of error symbols is 2 is shown. Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a may inject non-zero-valued error symbols at two locations 634_1 and 634_2 of the error vector 633. Symbols of zero value may be injected into the remaining symbols of the error vector 633. Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a can generate the second codeword CW2 injected with error codewords by performing an addition operation on the generated error vector 633 and the parity check vector 632 of the first codeword CW1 in units of codewords. Figure 5C, the second codeword CW2 may include data 635 and a parity check vector 637. For example, the values ​​of the codewords 636_1 and 636_2 “corresponding to the two positions 634_1 and 634_2 of the error vector 633” among the codewords of the second codeword CW2 may be determined by adding the first codeword CW1 and the error vector 633.

[0096] Despite FIG. 5B to FIG. 5C , but some positions of the parity check vector 622 / 632 may be erased positions. In this case, Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a may inject error symbols at positions of the error vector 623 / 633 that “do not correspond to erasure positions”.

[0097] Since the error symbol is inserted at a position of the error vector that does not correspond to the erasure position, even when Figure 1 The ECC circuit 110, Figure 2 The ECC circuit 510 and Figure 3 When the ECC circuit 510a performs error and erasure decoding, an error symbol that allows an error range (or error level) exceeding the error correction capability may also be injected into the second codeword CW2. Therefore, the poisoning information retention capability of the second codeword CW2 can be guaranteed.

[0098] Figure 6 is a block diagram showing a configuration of an example of the ECC circuit 510 b. Figure 6 The ECC circuit 510b can be used with Figure 1 The ECC circuit 110, Figure 2 The ECC circuit 510 and Figure 3 Corresponding to the ECC circuit 510a.

[0099] Reference Figure 6 , the ECC circuit 510 b may include an ECC encoder 511 and an ECC decoder 512 .

[0100] The ECC encoder 511 may perform ECC encoding on the data DT to generate a parity check vector PRT, and may add the parity check vector PRT to the data DT to generate a first codeword CW1. The ECC encoder 511 may generate the first codeword CW1 by concatenating the parity check vector PRT and the data DT. It is assumed that the data DT is data in units of codewords. The first codeword CW1 thus generated may be provided to Figure 1 The error injection circuit 120, Figure 2 The error injection circuit 530 and Figure 3 The error injection circuit 530a.

[0101] The ECC decoder 512 may perform ECC decoding based on error and erasure decoding. The ECC decoder 512 may be provided with the third codeword CW3. When an error is detected from the third codeword CW3, the ECC decoder 512 may recover the error-corrected data DT from the third codeword CW3, and may provide the recovered data DT and the cleared UE flag to the host device. When an uncorrectable error is detected from the third codeword CW3, the ECC decoder 512 may provide the data DT in which the error detected from the third codeword CW3 is not corrected and the set UE flag to the host device.

[0102] Reference Figure 6 , the ECC decoder 512 may include a syndrome calculator 513 , a poisoning detector 515 , an error corrector 517 , and a poisoning flag generator 518 .

[0103] The syndrome calculator 513 may generate a syndrome SDR based on the third codeword CW3 by using the parity check matrix H-MATRIX. The parity check matrix H-MATRIX may be stored in a separate memory 514 such as a ROM.

[0104] The error corrector 517 may correct one or more symbol errors by performing ECC decoding on the third codeword CW3 based on the syndrome SDR, and may output data DT. The error corrector 517 may be a Reed-Solomon (RS) decoder that performs decoding based on a Reed-Solomon (RS) code. The error corrector 517 may be based on Figure 4 Error and erasure decoding is performed based on the erasure positions EP of the erasure table. When an uncorrectable error is detected from the third codeword CW3, the error corrector 517 may output a set UE flag.

[0105] The poison detector 515 can determine whether the third codeword CW3 is a codeword into which an error symbol is injected based on the syndrome SDR and the poison syndrome PSDR. For example, when the syndrome SDR is consistent with the poison syndrome PSDR among the plurality of poison syndromes stored in the poison syndrome set 516, the poison detector 515 can determine that the error symbol is injected into the third codeword CW3. The poison syndrome PSDR can be a syndrome generated by calculating the parity check matrix H-MATRIX and each error vector that can be generated. For example, a number of error vectors each including two error symbols having non-zero values ​​can be generated from the error vectors having a codeword length "n". In some embodiments, the poison detector 515 may refer to the address ADDR of the memory device where the third codeword CW3 is read, and may detect the poison syndrome PSDR based on the address ADDR corresponding to the third codeword CW3. Figure 4The number of error symbols is determined based on the number of erasures in the erasure table and the number of parity symbols of the third codeword CW3. Therefore, the poison detector 515 can compare the syndrome SDR with the poison syndrome PSDR "corresponding to the determined number of error symbols" among the multiple poison syndromes.

[0106] The poison detector 515 may send a comparison result PI of the poison syndrome PSDR and the syndrome SDR to the poison flag generator 518. When the comparison result PI of the poison syndrome PSDR and the syndrome SDR indicates that the third codeword CW3 is a poisoned codeword, the poison flag generator 518 may set the poison flag PF to "1"; when the comparison result PI of the poison syndrome PSDR and the syndrome SDR indicates that the third codeword CW3 is not a poisoned codeword, the poison flag generator 518 may set the poison flag PF to "0". The generated poison flag PF may be provided to the host device.

[0107] Will refer to Figure 6 and Figure 7 Describe the poison sign and UE sign.

[0108] Figure 7 is an example diagram showing a poisoning flag and an uncorrectable error (UE) flag.

[0109] When the codeword read from the memory device is a normal codeword in which no error occurs, the poison detector 515 may set the poison flag to '0', and the error corrector 517 may set the UE flag to '0'.

[0110] When the codeword read from the memory device is a codeword in which an uncorrectable error occurs, the poison detector 515 may set the poison flag to '0', and the error corrector 517 may set the UE flag to '1'.

[0111] When the codeword read from the memory device is a codeword into which an error symbol is injected, the poison detector 515 may set the poison flag to '1', and the error corrector 517 may set the UE flag to '1'.

[0112] The error injection circuit can inject an error codeword whose allowable error range (or error level) exceeds the error correction capability of the ECC decoder into the poisoned codeword, so that the codeword injected with the error codeword may not be corrected by the ECC decoder. In other words, the codeword injected with the error codeword can stably maintain the poisoning information. Therefore, since the read codeword is the codeword injected with the error codeword, the error corrector 517 may not be able to correct the error of the read codeword. In this case, the error corrector 517 can set the UE flag to "1".

[0113] Figure 8 is a block diagram illustrating an example of the memory device 200 . Figure 8 The memory device 200 may be connected with Figure 1 Corresponding to the memory device 200.

[0114] Reference Figure 8 , the memory device 200 may include a control logic circuit 210, an address register 255, a memory bank control circuit 230, a refresh control circuit 257, a row address multiplexer 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory cell array 220, a sense amplifier unit 225, an input / output (I / O) selection circuit 290, an on-die ECC engine 285 and a data input / output buffer 280.

[0115] The memory cell array 220 may include a plurality of bank arrays 220_1 to 220_n. Each of the plurality of bank arrays 220_1 to 220_n may include a plurality of memory cells. For example, each of the plurality of memory cells may be formed at an intersection of a corresponding word line and a corresponding bit line.

[0116] The row decoder 260 may include a plurality of sub-row decoders 260_1 to 260_n. Each of the plurality of sub-row decoders 260_1 to 260_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 220_1 to 220_n.

[0117] The sense amplifier unit 225 may include a plurality of sense amplifiers 225_1 to 225 — n. Each of the plurality of sense amplifiers 225_1 to 225 — n may be connected to a corresponding bank array among the plurality of bank arrays 220_1 to 220 — n.

[0118] The column decoder 270 may include a plurality of sub-column decoders 270_1 to 270_n. Each of the plurality of sub-column decoders 270_1 to 270_n may be connected to a corresponding bank array among the plurality of bank arrays 220_1 to 220_n through a corresponding sense amplifier.

[0119] A plurality of bank arrays 220_1 to 220_n, a plurality of sense amplifiers 225_1 to 225_n, a plurality of sub-column decoders 270_1 to 270_n, and a plurality of sub-row decoders 260_1 to 260_n may constitute a plurality of banks. For example, a first bank array 220_1, a first sense amplifier 225_1, a first sub-column decoder 270_1, and a first sub-row decoder 260_1 may constitute a first bank.

[0120] The address register 255 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the controller 100. The address register 255 may provide the received bank address BANK_ADDR to the bank control circuit 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.

[0121] The bank control circuit 230 may generate a bank control signal in response to the bank address BANK_ADDR. A sub-row decoder corresponding to the bank address BANK_ADDR among the plurality of sub-row decoders 260_1 to 260_n may be activated in response to the bank control signal. A sub-column decoder corresponding to the bank address BANK_ADDR among the plurality of sub-column decoders 270_1 to 270_n may be activated in response to the bank control signal.

[0122] The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 255, and may receive a refresh row address REF_ADDR from the refresh control circuit 257. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to each of the plurality of sub-row decoders 260_1 to 260_n.

[0123] In response to a refresh signal from the control logic circuit 210, the refresh control circuit 257 may sequentially increase or decrease the refresh row address REF_ADDR in the normal refresh mode.

[0124] A sub row decoder selected by the bank control circuit 230 among the plurality of sub row decoders 260_1 to 260_n may activate a word line corresponding to the row address RA from the row address multiplexer 240. For example, the selected sub row decoder may apply a word line driving voltage to the word line corresponding to the row address RA.

[0125] The column address latch 250 may receive the column address COL_ADDR from the address register 255 and may temporarily store the received column address COL_ADDR. In addition, for example, in a burst mode, the column address latch 250 may sequentially increase the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored column address COL_ADDR or the sequentially increased column address COL_ADDR to each of the plurality of sub-column decoders 270_1 to 270_n.

[0126] A sub-column decoder activated by the bank control circuit 230 among the plurality of sub-column decoders 270_1 to 270 — n may activate a sense amplifier corresponding to a bank address BANK_ADDR and a column address COL_ADDR through an input / output gating circuit 290 .

[0127] The input / output gating circuit 290 may include a circuit for gating input / output data. In addition, the input / output gating circuit 290 may include a data latch for storing codewords output from the plurality of memory bank arrays 220_1 to 220_n and a write driver for writing data into the plurality of memory bank arrays 220_1 to 220_n.

[0128] In some embodiments, in a read operation, the fourth codeword CW4 read from the “memory bank array selected from the plurality of memory bank arrays 220_1 to 220_n” may be sensed by a sense amplifier corresponding to the selected memory bank array, and may be stored in a data latch of the input / output strobe circuit 290. In addition, ECC decoding may be performed on the fourth codeword CW4 stored in the data latch by the on-die ECC engine 285, and as a result of the ECC decoding, the second codeword CW2 may be provided to the data input / output buffer 280. The data input / output buffer 280 may generate a data signal DQ based on the second codeword CW2, and may provide the data signal DQ to the controller 100 together with the strobe signal DQS.

[0129] In some embodiments, in a write operation, the second codeword CW2 to be written to the "memory bank array selected from the plurality of memory bank arrays 220_1 to 220_n" may be received by the data input / output buffer 280 as a data signal DQ. The data input / output buffer 280 may convert the data signal DQ into the second codeword CW2 to be provided to the on-die ECC engine 285. The on-die ECC engine 285 may generate a parity bit (or parity data) based on the second codeword CW2, and may provide a fourth codeword CW4 including the second codeword CW2 and the parity bit to the input / output gating circuit 290. The input / output gating circuit 290 may write the fourth codeword CW4 into the selected memory bank array.

[0130] According to some embodiments, the second codeword CW2 provided to the data input / output buffer 280 may include data provided by the host device, Figure 1 The ECC circuit 110 generates parity information based on the data and Figure 1 That is, the on-die ECC engine 285 may generate a fourth codeword CW4 by performing ECC encoding on the entire second codeword CW2 including data provided from the host device, parity information, and error symbols.

[0131] In a write operation, the data input / output buffer 280 may convert the data signal DQ into a second codeword CW2 to be provided to the on-die ECC engine 285. In a read operation, the data input / output buffer 280 may convert the second codeword CW2 from the on-die ECC engine 285 into the data signal DQ.

[0132] The control logic circuit 210 may control the operation of the memory device 200. For example, the control logic circuit 210 may generate a control signal so that the memory device 200 performs a write operation, a read operation, and a refresh operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the controller 100 and a mode register (MRS) 212 for setting an operation mode of the memory device 200.

[0133] The command decoder 211 may decode the command CMD to generate internal command signals such as an internal activation signal IACT, an internal precharge signal IPRE, an internal read signal IRD, and an internal write signal IWR. In addition, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a chip select signal and a command / address signal.

[0134] Fig. 9 It is shown Figure 8 An example diagram of a portion of a memory bank array. Fig. 9 The memory bank array 220_1 may be connected to, for example, Figure 8 Corresponding to the first memory bank array 220_1.

[0135] Reference Fig. 9 , the first memory module array 220_1 may include a plurality of word lines WL0 to WLm, a plurality of bit lines BL0 to BLn, and a plurality of memory cells MC disposed at intersections of the word lines WL0 to WLm and the bit lines BL0 to BLn.

[0136] In some embodiments, each memory cell MC may be a DRAM cell. For example, each memory cell MC may include a cell transistor connected to a word line and a bit line, and a cell capacitor connected to the cell transistor.

[0137] Each word line extending along the row direction may be referred to as a “row” of the first memory bank array 220_1 . Each bit line extending along the column direction may be referred to as a “column” of the first memory bank array 220_1 .

[0138] The codewords injected with the error codewords can be stored in a plurality of memory cells MC. In addition, each error codeword can be stored in a plurality of memory cells MC. That is, since the codewords to be written into Figure 8The second code word CW2 in the memory bank array is a code word in units of code elements, and thus one code element can be stored in a plurality of memory cells MC consisting of a plurality of bits.

[0139] Fig.10 is an example diagram showing the configuration of an on-die ECC engine. Fig.10 The on-die ECC engine 285 can be used with, for example Figure 8 The on-die ECC engine 285 corresponds to.

[0140] The on-die ECC engine 285 may include an on-die ECC encoder 285_1 and an on-die ECC decoder 285_2. Fig.10 2 is shown together with the on-die ECC engine 285. The first memory bank array 220_1 may include a normal cell array NCA and a redundant cell array RCA.

[0141] The on-die ECC encoder 285_1 may generate parity bits OD_PRT associated with write data WDQ to be stored in the normal cell array NCA of the first memory bank array 220_1. The parity bits OD_PRT may be stored in the redundant cell array RCA of the first memory bank array 220_1.

[0142] The on-die ECC decoder 285_2 may perform ECC decoding of the read data RDQ by using the read data RDQ and the parity bits OD_PRT read from the first bank array 220_1. The on-die ECC decoder 285_2 may correct at least one error bit and may output corrected data CDQ.

[0143] According to some embodiments, each of the write data WDQ and the corrected data CDQ may be a second code word CW2. The second code word CW2 may include “data provided by the host device, Figure 1 The ECC circuit 110 generates parity information based on the data, and Figure 1 That is, the on-die ECC encoder 285_1 may generate the parity bit OD_PRT by performing ECC encoding on the entire second codeword CW2 “including the data provided from the host device, the parity information, and the error codeword”. The on-die ECC decoder 285_2 may perform ECC decoding on the read data RDQ, and may generate the second codeword CW2 including “the data provided from the host device, the parity information, and the error codeword” as the corrected data CDQ.

[0144] Fig.11 is a flowchart illustrating an example of the operation of a controller that controls a memory module. Fig.11The controller described in the following may be used with Figure 1 The controller 100 and / or Figure 2 Corresponding to the controller 100a.

[0145] In operation S110, the controller 100 / 100a may receive a request for storing data and a poison flag from the host device through the CXL interface. The poison flag may include information about whether the data to be stored is poisoned data. For example, a set poison flag may indicate that the data to be stored is poisoned data, and a cleared poison flag may indicate that the data to be stored is not poisoned data.

[0146] In operation S120 , the controller 100 / 100 a may generate a parity check vector by performing ECC encoding on received data based on a Reed-Solomon (RS) code, and may generate a first codeword by adding the generated parity check vector to the received data.

[0147] In operation S130, the controller 100 / 100a may generate an error vector to be injected into the first codeword. The error vector may include at least one error symbol. The controller 100 / 100a may determine the number of error symbols that allow the error range (or error level) to exceed the error correction capability of the ECC decoder. For example, when error decoding based on the RS code is performed, the controller 100 / 100a may determine the number of error symbols to be or more (P is the number of parity check symbols) to record poisoning information. When the ECC decoder performs error and erasure decoding based on the RS code, the controller 100 / 100a may determine the number of error symbols as or more (P is the number of parity symbols, and N_Erasure is the number of erasures). Therefore, the number of error symbols can be variably determined.

[0148] The controller 100 / 100a may determine the number of error symbols based on a cache line of an SRAM of a host device storing received data or an erase number associated with a physical address of a memory device to store received data. The erase number may be an erase number stored in an erase table.

[0149] The controller 100 / 100a may generate the second codeword by injecting a determined number of error symbols into at least a portion of the first codeword. The controller 100 / 100a may inject the error symbols into the data of the first codeword, or may inject the error symbols into the parity check vector of the first codeword. The controller 100 / 100a may generate the second codeword by injecting the error symbols into the first codeword via "symbol-based addition of the error vector and the first codeword".

[0150] The controller 100 / 100a may inject an error symbol at a position of the first codeword not associated with erasure information. That is, the controller 100 / 100a may inject an error symbol at a position of the error vector "not associated with erasure information among positions of the first codeword".

[0151] In operation S140 , the controller 100 / 100 a may control the memory device 200 so that the second codeword into which the error symbol is injected is stored in the memory cell array 220 .

[0152] Fig.12 FIG. 1 is a flowchart showing an example of an operation of a controller controlling a memory module to set a poison flag and a UE flag. Fig.12 The controller described in Figure 1 The controller 100 and / or Figure 2 Corresponding to the controller 100a.

[0153] In operation S210 , the controller 100 / 100 a may receive a request for reading a second codeword into which an error symbol is injected from a host device through a CXL interface.

[0154] In operation S220 , the controller 100 / 100 a may control the memory device to read the second codeword into which the error symbol is injected.

[0155] In operation S230 , the controller 100 / 100 a may calculate a syndrome of the second codeword into which the error symbol is injected.

[0156] In operation S240, the controller 100 / 100a may determine whether the syndrome of the second codeword is a syndrome of poisoned data. For example, the controller 100 / 100a may compare the syndrome of the second codeword with a plurality of poisoned syndromes "generated by calculating various types of error vectors and parity check matrices". When the comparison result indicates that any one of the poisoned syndromes is consistent with the syndrome of the second codeword, it may be determined that the syndrome of the second codeword is a syndrome of poisoned data. Therefore, the controller 100 / 100a may determine the second codeword as a codeword generated from poisoned data.

[0157] When it is determined that the syndrome of the second codeword is a syndrome of poisoned data, the controller 100 / 100 a may set a poison flag (eg, may set the poison flag to “1”) in operation S250 .

[0158] In operation S290 , the controller 100 / 100 a may set a UE flag in response to the poison flag being set.

[0159] When it is determined that the syndrome of the second codeword is not the syndrome of the poisoned data, in operation S260, the controller 100 / 100a may perform ECC decoding on the second codeword. The ECC decoding may be RS code-based decoding. The ECC decoding may be error and erasure decoding.

[0160] In operation S270, the controller 100 / 100a may determine whether the ECC decoding result indicates that an error is detected from the second codeword.

[0161] In operation S280, the controller 100 / 100a may determine whether an error detected from the second codeword is an uncorrectable error.

[0162] In operation S290 , the controller 100 / 100 a may set a UE flag in response to determining that the error detected from the second codeword is an uncorrectable error.

[0163] In operation S300, the controller 100 / 100a may clear the UE flag in response to determining that the error detected from the second codeword is a correctable error or that no error is detected from the second codeword.

[0164] A semiconductor memory device according to the present disclosure can effectively manage a poison flag.

[0165] Although this specification includes many specific implementation details, these should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Specific features described in this specification in the context of a single implementation may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable subcombination. In addition, although features may be described above as working in a particular combination, one or more features from a combination may be deleted from the combination in some cases, and the combination may indicate a subcombination or a variation of a subcombination.

[0166] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A memory module based on computing fast link, comprising: a memory device including a plurality of volatile memory cells, the memory device being configured to store data or read stored data; as well as a controller configured to communicate with a host device through a computing quick link interface and control the memory device, The controller includes: an error correction code circuit configured to generate a first codeword based on adding a parity check vector to data received from a host device, the parity check vector being generated based on Reed-Solomon coding; an error injection circuit configured to: generate an error symbol, and generate a second codeword based on injecting the error symbol into at least a portion of the first codeword; and a memory device interface configured to control the memory device so that the second codeword injected with the error symbol is stored in the memory device, The controller determines a number of error symbols injected into the second codeword.

2. The memory module based on computing fast link according to claim 1, wherein: The number of error symbols is determined based on a cache line storing the received data or erase information associated with a physical address of a memory device controlled by the host device to store the received data.

3. The memory module based on computing fast link according to claim 2, wherein: The number of erroneous symbols is inversely proportional to the number of erasures in the erasure information.

4. The memory module based on computing fast link according to claim 2, wherein: The number of erroneous symbols is proportional to the length of the parity check vector.

5. The memory module based on computing fast link according to claim 2, wherein: The error injection circuit is configured to inject error symbols at locations of the first codeword, the locations not associated with erasure information.

6. The memory module based on computing fast link according to claim 1, wherein: The error injection circuit is configured to inject an error symbol into the parity check vector of the first codeword.

7. The memory module based on computing fast link according to claim 1, wherein: The number of error symbols is smaller than the number of parity check symbols included in the parity check vector.

8. The memory module based on computing fast link according to claim 1, wherein: The error injection circuit is configured to generate an error symbol based on a poison flag, the poison flag being associated with the received data and being sent from the host device.

9. The memory module based on computing fast link according to claim 1, wherein: The memory device comprises: The on-die error correction code engine is configured to generate a third codeword to which a parity bit generated based on the second codeword is added.

10. The memory module based on computing fast link according to any one of claims 1 to 9, wherein: The memory device interface is configured to control the memory device based on the address received from the controller so that the second codeword injected with the error codeword is read, Wherein, the error correction code circuit is configured as: calculating a syndrome of the second codeword into which the error symbol is injected; and A set poison flag is generated based on associating the syndrome with the error symbol.

11. The memory module based on computing fast link according to claim 10, wherein: The error correction code circuit is configured as: comparing a syndrome of the second codeword with a poison syndrome associated with the address from a plurality of poison syndromes to generate a comparison result; and A set poison flag is generated based on the comparison result.

12. The memory module based on computing fast link according to any one of claims 1 to 9, wherein: The error injection circuit is configured as: generating an error vector, the error vector comprising an error symbol having a non-zero value and a plurality of symbols having a zero value; as well as An addition operation is performed on the error vector and the first codeword in units of symbols.

13. The memory module based on computing fast link according to claim 12, wherein: The error injection circuit is configured to perform an addition operation on the error vector and the parity check vector of the first codeword in units of symbols.

14. The memory module based on computing fast link according to claim 12, wherein: The size of the error vector is equal to the size of the first codeword or the size of the parity check vector.

15. An operating method of a controller configured to control a memory device, the operating method comprising: receiving, at the controller via the computing quick link interface, an indication to store data from the host device with a poison flag; adding a parity check vector to data received from a host device at a controller to generate a first codeword, the parity check vector being generated based on Reed-Solomon coding; At a controller, injecting at least one error symbol into at least a portion of the first codeword to generate a second codeword; as well as controlling the memory device at the controller so that the second codeword injected with the at least one error symbol is stored, The number of error symbols injected into the second codeword is determined by a controller.

16. The operating method according to claim 15, wherein: The step of injecting the at least one error symbol comprises: determining the number of error symbols based on a cache line of a host device storing the data or erase information associated with a physical address of a memory device, the host device instructing the data to be stored at the physical address of the memory device; and The at least one error symbol is generated based on the number of error symbols.

17. The operating method according to claim 16, wherein: The number of erroneous symbols is inversely proportional to the number of erasures in the erasure information and is directly proportional to the length of the parity check vector.

18. The operating method according to claim 16, wherein: The step of injecting the at least one error symbol comprises: The at least one error symbol is injected at a location of the first codeword, the location not associated with erasure information.

19. The operating method according to any one of claims 15 to 18, comprising: receiving, from a host device via a computing fast link interface, an indication of reading a second codeword into which error symbols were injected; Controlling the memory device to read the second codeword into which the error codeword is injected; Calculating a syndrome of a second codeword into which the error symbol is injected; generating a set poison flag based on the syndrome being a syndrome associated with the at least one erroneous symbol; as well as Data and a set poison flag are sent to a host device, the data being obtained based on performing Reed-Solomon decoding on the second codeword into which the error symbols are injected.

20. A computing device comprising: CPU; a memory device comprising a plurality of volatile memory cells; as well as The controller is configured as: Communicates with the central processing unit via a compute fast link interface; as well as Controls memory devices based on commands and addresses sent by the CPU, The memory device is configured to: store data in the plurality of volatile memory cells corresponding to the addresses or read data from the plurality of volatile memory cells corresponding to the addresses under the control of the controller, The controller is configured as follows: determining a number of error symbols based on the address; and The number of error symbols is injected into at least a portion of a codeword generated based on data received from a central processor.

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