Embedded resistor thin film material with extremely low resistance temperature coefficient and preparation method

Abstract

The invention relates to an embedded resistance thin film material with an extremely low resistance temperature coefficient, the material comprises a substrate, an insertion layer and a resistance layer, the embedded resistance thin film material with the extremely low resistance temperature coefficient is deposited on the substrate by adopting a sputtering method, and the embedded resistance material with the extremely low resistance temperature coefficient is obtained by changing the annealing temperature. The temperature coefficient of the resistor can be increased by 38 times at most, the thermal stability of the embedded resistor thin film material is improved, and then the embedded resistor thin film material which is wide in application range, high in repeatability, simple in process and easy to control in the preparation process is obtained.

Description

Technical Field

[0001] The invention relates to a thin film resistor material, in particular to an embedded resistor thin film material with an extremely low resistance temperature coefficient, and belongs to the technical field of electronic materials and electronic components. Background Art

[0002] With the development of electronic technology, electronic products are also tending to be miniaturized and portable, which puts higher requirements on the PCB (Printed Circuit Board) of electronic products, requiring PCB to have a higher integration density, so as to improve the miniaturization of electronic devices. The large number of passive devices on the surface of PCB is the main reason hindering the miniaturization of PCB. With the continuous increase of electronic components carried on the surface, not only the space on the PCB surface is tight, but the previous surface mount technology SMT (Surface Mounting Technology) will also inevitably cause an increase in the number of solder joints, thus affecting the reliability of the connection of electronic devices. Embedding passive devices inside the PCB can not only save a lot of surface space of PCB, improve the integration of PCB, promote the miniaturization of PCB, but also reduce the number of solder joints and ensure the reliability of electronic products. Therefore, in order to break through the technical limitations of SMT and improve the integration of electronic devices, embedding technology continues to develop.

[0003] The Temperature Coefficient of Resistance (TCR) refers to the relative rate of change of resistance with temperature, usually expressed as the change in resistivity per degree Celsius (℃), which reflects the sensitivity of the material's resistance to temperature changes. A low temperature coefficient of resistance can ensure the stability of the circuit in an environment with large temperature changes, reduce the risk of circuit failure, and extend the service life of the equipment. In many electronic devices, changes in the resistance value of the resistor element may affect the performance of the entire circuit. In order to maintain the accuracy and stability of the circuit, it is necessary to control the characteristics of the resistance changing with temperature, and the temperature coefficient of resistance can be regulated by changing the structure of the resistor.

[0004] Embedded resistors have high requirements for stability in applications, and chromium silicon carbon materials combine the characteristics of metals, semiconductors and ceramics, and can show good oxidation resistance and corrosion resistance at high temperatures. Through annealing, the temperature coefficient of resistance of chromium silicon carbon materials can gradually change from negative to positive as the annealing temperature increases. At the same time, chromium silicon carbon materials perform well in high-frequency applications, can reduce the attenuation of electrical performance in signal transmission, and are suitable for use in radio frequency and microwave communication systems; nickel-phosphorus alloys have the characteristics of corrosion resistance, high resistivity, and good stability, and the TCR is positive after annealing. The chromium silicon carbon and nickel-phosphorus are stacked in a design, and the TCR values ​​compensate each other, and the value after annealing is extremely low. Combining the characteristics and advantages of the two materials, a new type of resistor material with more stable resistance performance will be produced.

[0005] At present, Japan and the United States are the leaders in PCB embedded capacitors, resistor raw materials, product design and manufacturing technologies. The main commercial products include nickel-phosphorus resistor materials prepared by electroplating method of Ohmega-ply Company in the United States, nickel-phosphorus resistor materials made by addition method of Mac Demid Company, nickel-chromium resistor materials made by sputtering method of Gould Company, etc. These resistor products have their own advantages, and their performance still has room for improvement.

[0006] The development of embedded thin-film resistors in China is still in its infancy. The main research method for the resistance value and electrical properties of embedded resistors is to change the doping ratio of the resistor material. However, this method is difficult to accurately control the resistance value and is difficult to repeat in reproduction. In addition, copper is often used in the production and development of electronic components. There will be mutual diffusion between copper and resistor materials, which affects the electrical performance of the device. However, by changing the thickness ratio of the resistor material, the resistance value can be accurately controlled, and the repeatability is high during production, and the introduction of nickel-phosphorus alloy can effectively block the diffusion between copper and resistor materials. Therefore, in response to the above problems in the development of embedded resistor products, it is very important to develop a double-layer film resistor material and industrial production preparation method based on thickness ratio and annealing temperature control, preventing mutual diffusion between resistor materials and copper, a wide resistance adjustment range, and stable electrical properties. Summary of the invention

[0007] The present invention aims at the existing technical problems in the field of embedded resistors and proposes a double-layer film resistor structure and a high-temperature annealing scheme, which can expand the resistance range of the resistor and improve the stability of the electrical performance of the resistor.

[0008] In order to achieve the above object, the technical solution of the present invention is as follows: an embedded resistor thin film material with an extremely low resistance temperature coefficient, the material comprising a substrate, a resistor layer, and an insertion layer, the insertion layer being arranged between the substrate and the resistor layer, i.e., substrate (Al2O3)-insertion layer (nickel phosphorus)-resistance layer (chromium silicon carbon). The material composition and structure of the embedded resistor are studied.

[0009] Wherein, in terms of thickness, in the embedded resistor material with extremely low resistance temperature coefficient, the total thickness of the film is 60 to 180 nanometers, of which the thickness of the resistor layer is 30 to 150 nanometers, and the thickness of the insertion layer is 2 to 30 nanometers.

[0010] The substrate is one or more of a ceramic substrate, a metal substrate, or a silicon substrate.

[0011] The material of the resistance layer is CrSiC alloy, which contains 25% chromium, 50% silicon and 25% carbon in atomic percentage. Under this ratio, the CrSiC material still maintains a relatively stable resistance value in a complex electromagnetic environment and under different temperature and humidity conditions, thereby ensuring the accuracy of the instrument measurement. The negative value of the temperature coefficient of the CrSiC alloy with this ratio can reach -699.9ppm / K when it is not annealed, and the electrical film stability is low. However, due to the addition of the C element, the movement of electrons between the lattices is interfered. Compared with the CrSi alloy, the square resistance of the film has been greatly improved.

[0012] The material of the insertion layer is NiP alloy, which is 70% nickel and 30% phosphorus by atomic percentage. The NiP alloy at this ratio can achieve precise manufacturing of resistors with specific resistance values ​​through sputtering deposition. The NiP material at this ratio can be well combined with the substrate, improving the stability of the embedded resistor in the circuit board, and is not prone to delamination and falling off.

[0013] NiP alloy (7:3) and CrSiC alloy (1:2:1) have different electrical properties. NiP alloy has good conductivity and relatively low temperature coefficient of resistance, while CrSiC alloy can provide more stable resistance characteristics, especially in high temperature and high frequency environments. By inserting nickel-phosphorus film into the chromium-silicon-carbon lower layer through magnetron sputtering, the resistance value of the embedded resistor can be accurately controlled in a wider range to meet the different requirements of various complex circuits for resistance values. NiP alloy (7:3) has a low temperature coefficient of resistance, while CrSiC alloy (1:2:1) can maintain stable resistance value over a wide temperature range. When NiP (7:3) film is used as an insertion layer of CrSiC (1:2:1) film, it can be controlled to obtain a lower temperature coefficient, ensuring the accuracy of the resistance value in more extreme temperature environments.

[0014] This embedded resistor film with an extremely low temperature coefficient of resistance uses a chromium silicon carbon film as the main material and a nickel phosphorus film as an insertion layer film; on the one hand, the nickel phosphorus film can significantly improve the crystal structure of chromium silicon carbon and enhance the thermal stability of the film when used as an insertion layer. On the other hand, after inserting the nickel phosphorus layer, the probability of electrons being scattered at the interface is increased, thereby causing a sharp increase in the resistivity and square resistance of the nickel phosphorus-chromium silicon carbon double-layer structure film of the same thickness. When the proportion of the nickel phosphorus layer increases, the nickel phosphorus layer becomes dominant, achieving ultra-low square resistance, thereby achieving a wider square resistance adjustment range.

[0015] A method for preparing an embedded resistor material with an extremely low temperature coefficient of resistance, the method comprising the following steps:

[0016] Step 1: Select chromium silicon carbon and nickel phosphorus as the basic materials for double-layer thin film resistors. Chromium silicon carbon has the characteristics of high square resistance. After high-temperature annealing, the temperature coefficient gradually increases and changes from negative to positive at 500°C. The temperature coefficient of nickel phosphorus material quickly changes to positive after annealing. The double-layer structure film is achieved by inserting nickel phosphorus material at the bottom of the chromium silicon carbon film to adjust the film temperature coefficient.

[0017] Step 2: Substrate selection: Al2O3 was selected as the sputtering substrate, and the substrate was ultrasonically cleaned in anhydrous acetone, anhydrous ethanol, and deionized water for 10 minutes respectively, and then dried with a nitrogen gun for later use.

[0018] Step 3: sputtering deposition is performed on the substrate by magnetron sputtering to obtain a corresponding double-layer thin film material, wherein the atomic percentage of the chromium silicon carbon target is 1:2:1, and the atomic percentage of the nickel phosphorus target is 7:3; wherein the purity of the chromium silicon carbon target is 99.9%, and the purity of the nickel phosphorus target is 99.9%; the chromium silicon carbon target and the nickel phosphorus target are placed at different cathode palladium positions, respectively, and the substrate is fixed on a rotating workbench in the main sputtering chamber;

[0019] During sputtering, argon gas was introduced, and the pressure in the main chamber was controlled at about 0.9 Pa through the flow valve and the ventilation valve, and the rotation speed of the sample rotating workbench was set to 10 rpm. Before sputtering, the chromium silicon carbon target and the nickel phosphorus target were pre-sputtered for 5 minutes respectively to prevent oxidation on the target surface or dust accumulation on the surface from contaminating the film sample.

[0020] During the sputtering process, the substrate temperature is kept at room temperature;

[0021] During the sputtering process, the sputtering power of the chromium silicon carbon target is selected to be 50 W, and the sputtering power of the nickel phosphorus target is selected to be 50 W. By changing the sputtering time, the sputtering thickness of each layer of the film is adjusted, and the proportion of each part in the double-layer structure film is changed.

[0022] High vacuum annealing regulation: The film temperature coefficient and electrical properties are adjusted by high vacuum annealing at 200℃~500℃ for 30 minutes.

[0023] After annealing, the square resistance of the chromium silicon carbon-nickel phosphorus double-layer film changes significantly from that without insertion. When the annealing temperature is 200℃, the square resistance of the buried resistor film changes from 485.25Ω / sq to 31.38Ω / sq after the introduction of the nickel phosphorus insertion layer; when the annealing temperature is 300℃, the square resistance of the buried resistor film changes from 545.39Ω / sq to 32.28Ω / sq after the introduction of the nickel phosphorus insertion layer; when the annealing temperature is 400℃, the square resistance of the buried resistor film changes from 745.37Ω / sq ​​to 68.62Ω / sq after the introduction of the nickel phosphorus insertion layer; when the annealing temperature is 500℃, the square resistance of the buried resistor film changes from 1776.77Ω / sq ​​to 56.54Ω / sq after the introduction of the nickel phosphorus insertion layer. It can be seen that after inserting the nickel phosphorus layer, the resistance range of the embedded resistor is broadened.

[0024] This embedded resistor film with an extremely low temperature coefficient of resistance uses a chromium silicon carbon film as the main material and a nickel phosphorus film as an insertion layer film; on the one hand, the nickel phosphorus film can significantly improve the crystal structure of chromium silicon carbon and enhance the thermal stability of the film when used as an insertion layer. On the other hand, after inserting the nickel phosphorus layer, the probability of electrons being scattered at the interface is increased, thereby causing a sharp increase in the resistivity and square resistance of the nickel phosphorus-chromium silicon carbon double-layer structure film of the same thickness. When the proportion of the nickel phosphorus layer increases, the nickel phosphorus layer becomes dominant, achieving ultra-low square resistance, thereby achieving a wider square resistance adjustment range.

[0025] A non-coherent interface is formed at the interface of the nickel-phosphorus-chromium-silicon-carbon double-layer structure film, the crystallinity of the film decreases, the grains become smaller, and the surface area of ​​the grain boundary increases, resulting in a greatly increased probability of electrons being scattered by the grain boundary. This is one of the reasons why the resistance value of the nickel-phosphorus-chromium-silicon-carbon double-layer structure film increases sharply compared with the chromium-silicon-carbon single-layer film.

[0026] The nickel-phosphorus-chromium-silicon-carbon double-layer film is initially in an amorphous state, and the atoms in the film are loosely arranged. After annealing at 200°C, the impurities and defects inside the film are reduced, the electron scattering mechanism is transformed into phonon scattering, and the temperature coefficient of the film changes from negative to positive; when the annealing temperature is between 200°C and 300°C, the electron and phonon scattering inside the film reaches a certain equilibrium state, and the resistance and temperature coefficient of the film remain almost unchanged; when annealed at 300°C to 400°C, a chromium-silicon-carbon-nickel-phosphorus alloy layer is formed at the resistor interface of the nickel-phosphorus-chromium-silicon-carbon double-layer film, and the chromium-silicon-carbon-nickel-phosphorus alloy has a resistance temperature coefficient of 0.1% when the annealing condition is 0-500°C. The temperature coefficient is negative. Therefore, the thin film resistor after annealing at 400℃ is equivalent to a resistor with a negative resistance temperature coefficient (chromium silicon carbon nickel phosphorus layer) connected in parallel with a resistor with a positive resistance temperature coefficient (chromium silicon carbon layer, nickel phosphorus layer) to achieve temperature coefficient compensation. Therefore, the overall resistance temperature coefficient of the thin film resistor suddenly drops from a positive value when annealed at 300℃ to a negative value when annealed at 400℃. When annealed at 400℃ to 500℃, the atomic diffusion at the interface tends to saturation, the thickness of the chromium silicon carbon nickel phosphorus alloy layer is stable, and the overall resistance temperature coefficient of the film further changes to a positive value with the growth of crystals in the chromium silicon carbon and nickel phosphorus films.

[0027] Compared with the current existing technology, the ultra-low temperature coefficient thin film resistor material in the present invention has a wider resistance range. The insertion of the nickel-phosphorus layer makes up for the lack of resistance value of the chromium-silicon-carbon material in the low resistance range, and significantly improves its temperature coefficient. After the original sample is annealed at 500°C, the resistance temperature coefficient changes from negative to positive in the temperature range of -55 to 125°C. When the chromium-silicon-carbon-nickel-phosphorus thickness ratio is 30nm:30nm, the best TCR sample is obtained after annealing at 500°C, and the TCR value is -4.87ppm / K.

[0028] Magnetron sputtering deposition can achieve precise control of film thickness and obtain extremely thin and uniform films. After reducing the thickness of the nickel-phosphorus insertion layer, the square resistance of the double-layer film is improved. When the chromium-silicon-carbon-nickel-phosphorus thickness ratio is 5nm:30nm, after annealing at 500℃, the square resistance can be increased from 64.5Ω / sq when the chromium-silicon-carbon-nickel-phosphorus thickness ratio is 30nm:30nm to 269.6Ω / sq, and the TCR value changes from -4.87ppm / K to -4.97ppm / K, indicating that this scheme can well achieve wide range control of square resistance, and the film temperature coefficient is extremely low, which can solve the lack of temperature stability of embedded resistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic diagram of the structure of a magnetron sputtering apparatus used in the present invention.

[0030] Figure 2 The structure diagram of embedded resistor with extremely low resistance temperature coefficient.

[0031] Figure 3 This is a structural diagram of the buried resistor device when the four-terminal method is used for testing in the present invention.

[0032] Figure 4 The temperature coefficient and resistance value of single-layer chromium silicon carbon film and single-layer nickel phosphorus film with different thicknesses and the change of film temperature coefficient at room temperature after insertion.

[0033] Figure 5 This is a graph showing the relationship between the temperature coefficient of 30nm+30nm nickel-phosphorus-chromium silicon-carbon double-layer film, single-layer 30nm chromium silicon-carbon film, single-layer 30nm nickel-phosphorus film, and single-layer chromium silicon carbon nickel-phosphorus film as a function of annealing temperature. DETAILED DESCRIPTION

[0034] In order to deepen the understanding of the present invention, the present invention is described in detail below with reference to the accompanying drawings.

[0035] Example: See Figure 1 (Sputtering image in the sputtering chamber), chromium silicon carbon and nickel phosphorus ultra-low resistance temperature coefficient film. The double-layer structure thin film resistor adjusts the proportion of the two materials by changing the thickness of chromium silicon carbon. The double-layer thin film resistor also includes a substrate, on which the resistance film is deposited, and the substrate is selected as an Al2O3 substrate.

[0036] Experiments have shown that the chromium silicon carbon-nickel phosphorus double-layer structure thin film resistor has a wide range of square resistance variation, and has good electrical stability in the temperature range of -55 to 125°C through annealing. It has high application value and a wide range of applications.

[0037] A method for preparing a chromium-silicon-carbon-nickel-phosphorus double-layer structured embedded thin film resistor with an extremely low temperature coefficient comprises the following steps:

[0038] Step S110: providing a substrate. The substrate is Al2O3, and the substrate is ultrasonically cleaned in anhydrous acetone, anhydrous ethanol, and deionized water for 10 minutes, and then blown dry with a nitrogen gun for standby use.

[0039] Step S120: sputtering and depositing on the substrate by magnetron sputtering to obtain a corresponding double-layer thin film material, wherein the atomic percentage of the chromium-silicon-carbon target is 1:2:1, and the atomic percentage of the nickel-phosphorus target is 7:3; wherein the purity of the chromium-silicon-carbon target is 99.9%, and the purity of the nickel-phosphorus target is 99.9%; the chromium-silicon-carbon target and the nickel-phosphorus target are respectively placed at different cathode palladium positions, and the substrate is fixed on a rotating workbench in the main sputtering chamber;

[0040] During sputtering, argon gas was introduced, and the pressure in the main chamber was controlled at about 0.9 Pa through the flow valve and the ventilation valve, and the rotation speed of the sample rotating workbench was set to 10 rpm. Before sputtering, the chromium silicon carbon target and the nickel phosphorus target were pre-sputtered for 5 minutes respectively to prevent oxidation on the target surface or dust accumulation on the surface from contaminating the thin film sample. The substrate baffle was closed during pre-sputtering.

[0041] During the sputtering process, the substrate temperature is kept at room temperature;

[0042] During the sputtering process, the sputtering power of the chromium silicon carbon target is selected to be 50 W, and the sputtering power of the nickel phosphorus target is selected to be 50 W. By changing the sputtering time, the sputtering thickness of each layer of the film is adjusted, and the proportion of each part in the double-layer structure film is changed.

[0043] After sputtering, the film is annealed in a high vacuum state, the annealing temperature range is 200-500°C, the annealing time is 30 minutes, and the annealed ultra-low resistance temperature coefficient thin film resistor material is taken out after cooling.

[0044] The above is a method for preparing an embedded resistor material with an extremely low temperature coefficient, which has a simple process and high repeatability, is conducive to industrial promotion, and the prepared film has good uniformity and precise thickness, and is easy to accurately adjust the resistance value.

[0045] Embodiment 1:

[0046] Fabrication of embedded thin film resistors

[0047] (1) An Al2O3 substrate with a size of 1 cm×1 cm was ultrasonically cleaned in anhydrous acetone, anhydrous ethanol, and deionized water for 10 minutes, and dried with a nitrogen gun for later use.

[0048] (2) During sputtering, argon gas is introduced, and the air pressure in the main chamber is controlled at about 0.9 Pa through the flow valve and the ventilation valve. The rotation speed of the sample rotating workbench is set to 10 rpm. Before sputtering, the chromium silicon carbon target and the nickel phosphorus target are pre-sputtered for 5 minutes respectively to prevent oxidation of the target surface or dust accumulation on the surface from contaminating the thin film sample. The substrate baffle is closed during pre-sputtering. After the pre-sputtering is completed, the substrate baffle is opened for thin film sputtering deposition. First, the nickel phosphorus film is sputtered on the substrate with a sputtering power of 50 W and a sputtering time of 7 minutes and 30 seconds. Then, the chromium silicon carbon film is sputtered on the nickel phosphorus film. The sputtering power is selected to be 50 W, and the sputtering time is 7 to 36 minutes; a nickel phosphorus-chromium silicon carbon double-layer film structure thin film resistor is formed, and the substrate temperature is kept at room temperature.

[0049] (3) After the sputtering is completed, the nickel phosphorus-chromium silicon carbon double-layer film structure resistor is subjected to a high-temperature annealing step, that is, the film is annealed at 200°C, 300°C, 400°C, and 500°C for 30 minutes in a high vacuum state.

[0050] Target material selection: The resistance layer material is selected as CrSiC alloy, which is recorded by atomic percentage, chromium accounts for 25%, silicon accounts for 50%, and carbon accounts for 25%. The insertion layer material is NiP alloy, which is recorded by atomic percentage, nickel accounts for 70% and phosphorus accounts for 30%.

[0051] Substrate cleaning: Select a ceramic substrate as the substrate, place the substrate in a flower column, and use acetone, alcohol, and deionized water to ultrasonically clean it for 10 minutes in sequence, with an ultrasonic machine frequency of 40 Hz;

[0052] Photolithography. Using photoresist AZ5510 and reverse photolithography process, a resistor pattern with a size of 300nm×600nm is made on the substrate;

[0053] Sample transfer. The substrate with the resistive pattern after photolithography is sent into the sputtering chamber, and the transfer process is kept in a vacuum state;

[0054] Sample sputtering growth. Argon gas was introduced, and the gas flow meter and the vent valve were adjusted to maintain the chamber pressure at about 0.9 Pa. The sample rotation was 10 rpm. The sputtering power of the NiP target was 50 W, the sputtering time was 7 minutes and 30 seconds, and the sputtering power of the CrSiC target was 50 W, the sputtering time ranged from 7 to 37 minutes, and sputtering deposition was performed successively.

[0055] The sputtered sample was placed in a flower cage and ultrasonically debonded with NMP (N-methylpyrrolidone, 1-Methyl-2-pyrrolidinone) for 20 minutes at an ultrasonic frequency of 80 Hz. An electronic device with a very low temperature coefficient of resistance was obtained, such as Figure 2 shown.

[0056] Comparative Example 1:

[0057] (1) An Al2O3 substrate with a size of 1 cm×1 cm was ultrasonically cleaned in anhydrous acetone, anhydrous ethanol, and deionized water for 10 minutes, and dried with a nitrogen gun for later use.

[0058] (2) During sputtering, argon gas is introduced, and the air pressure in the main chamber is controlled at about 0.9 Pa through the flow valve and the ventilation valve. The rotation speed of the sample rotating workbench is set to 10 rpm. Before sputtering, the chromium silicon carbon target is pre-sputtered for 5 minutes to prevent oxidation of the target surface or dust accumulation on the surface from contaminating the thin film sample. The substrate baffle is closed during pre-sputtering. After the pre-sputtering is completed, the substrate baffle is opened for thin film sputtering deposition. A chromium silicon carbon film is sputtered and deposited on the substrate. The sputtering power is selected to be 50 W, and the sputtering time is 7 to 36 minutes to form a chromium silicon carbon single-layer film of different thicknesses.

[0059] (3) After the sputtering is completed, the chromium silicon carbon single-layer thin film structure resistor is subjected to a high-temperature annealing step, that is, the thin film is annealed at 200° C., 300° C., 400° C., and 500° C. for 30 minutes in a high vacuum state.

[0060] Comparative Example 2:

[0061] (1) An Al2O3 substrate with a size of 1 cm×1 cm was ultrasonically cleaned in anhydrous acetone, anhydrous ethanol, and deionized water for 10 minutes, and dried with a nitrogen gun for later use.

[0062] (2) During sputtering, argon gas is introduced, and the air pressure in the main chamber is controlled at about 0.9 Pa through the flow valve and the ventilation valve. The rotation speed of the sample rotating workbench is set to 10 rpm. Before sputtering, the nickel-phosphorus target is pre-sputtered for 5 minutes to prevent oxidation of the target surface or dust accumulation on the surface from contaminating the thin film sample. The substrate baffle is closed during pre-sputtering. After the pre-sputtering is completed, the substrate baffle is opened for thin film sputtering deposition. A nickel-phosphorus film is sputtered and deposited on the substrate. The sputtering power is selected to be 50 W, and the sputtering time is 7 minutes and 30 seconds to form a 30 nm single-layer film.

[0063] (3) After the sputtering is completed, the chromium silicon carbon single-layer thin film structure resistor is subjected to a high-temperature annealing step, that is, the thin film is annealed at 200° C., 300° C., 400° C., and 500° C. for 30 minutes in a high vacuum state.

[0064] Comparative Example 3:

[0065] (1) An Al2O3 substrate with a size of 1 cm×1 cm was ultrasonically cleaned in anhydrous acetone, anhydrous ethanol, and deionized water for 10 minutes, and dried with a nitrogen gun for later use.

[0066] (2) During sputtering, argon gas is introduced, and the air pressure in the main chamber is controlled at about 0.9 Pa through the flow valve and the ventilation valve. The rotation speed of the sample rotating workbench is set to 10 rpm. Before sputtering, the chromium silicon carbon target and the nickel phosphorus target are pre-sputtered for 5 minutes respectively to prevent oxidation of the target surface or dust accumulation on the surface from contaminating the thin film sample. The substrate baffle is closed during pre-sputtering. After the pre-sputtering is completed, the substrate baffle is opened for thin film sputtering deposition. The chromium silicon carbon and nickel phosphorus target materials are sputtered on the substrate at the same time. The target sputtering power is 50 W to form a chromium silicon carbon-nickel phosphorus co-sputtering thin film structure.

[0067] (3) After the sputtering is completed, the chromium silicon carbon-nickel phosphorus co-sputtered thin film structure resistor is subjected to a high temperature annealing step, that is, the film is annealed at 200°C, 300°C, 400°C, and 500°C in a high vacuum state.

[0068] Anneal at 37°C for 30 minutes.

[0069] The double-layer film in Example 1 and the film in Comparative Example 1 were subjected to photolithography to obtain the embedded resistor device required for the four-terminal test method, such as Figure 3 shown.

[0070] The obtained thin film resistor device was tested by a high and low temperature vacuum detection station (KT-Z160T-RL), and the variable temperature test was carried out at a vacuum level below 100Pa. Figure 2 As shown, four probes are connected to the four ends of the resistor to be measured, among which ports 1 and 2 are connected to the Keithley 2450 digital source meter, a constant current I is passed between them, and the Keithley 2450 digital source meter is used to record the voltage change U between ports 34 (or 35, 56, 46) during the temperature change process. The measured voltage value is compared with the current value passed through ports 1 and 2 to obtain the resistance value of the corresponding resistor device. The effective length of the resistor is L, the width is W, and the film thickness is t. According to the formula Calculate the sheet resistance R of the corresponding embedded resistor device sq The temperature range of the resistance measurement is -55℃~125℃. A node is set every 25℃ and each node is maintained for 6 minutes to ensure that the sample reaches the target temperature. According to the temperature coefficient formula The resistance temperature coefficient of the material at each temperature point with respect to the normal temperature T0 (T0 = 25°C) is obtained. The relationship between the temperature coefficient and the square resistance value of Example 1 and the change of the film thickness is shown as follows: Figure 4 shown.

[0071] The relationship curves of the square resistance of Example 1 and Comparative Example 1 as a function of the annealing temperature are plotted; the relationship curves of the temperature coefficient of Example 1 and Comparative Example 1 as a function of the annealing temperature are plotted, such as Figure 4 shown.

[0072] At room temperature, four-probe tests were performed on the embedded resistor samples of the nickel-phosphorus-chromium-silicon-carbon double-layer thin film structure with different chromium-silicon-carbon thicknesses in Example 1 to obtain a curve showing the relationship between the film resistivity of the relevant structure and the annealing temperature, and a curve showing the relationship between the film temperature coefficient of the relevant structure and the annealing temperature. Figure 5 shown.

[0073] The temperature coefficient images of Example 1 and Comparative Examples 1 to 2 without annealing are plotted as follows: Figure 4 shown.

[0074] Figure 4 The overall resistance temperature coefficient of the film in Example 1 is basically unchanged. The temperature coefficient range of the chromium silicon carbon single-layer film with different thicknesses is: -699.9 to -652.5 ppm / K. The thermal stability of the film without the nickel phosphorus layer is poor.

[0075] Figure 4It can be seen that after the nickel-phosphorus layer is sputtered, the temperature coefficient range changes from -699.9 to -652.5 ppm / K to -188.85 to -148.8 ppm / K, and the lowest can reach -148.8 ppm / K, indicating that the thermal stability of the film has been significantly improved.

[0076] Figure 5 It can be seen that when the annealing temperature is 200℃, the temperature coefficient of the buried barrier film increases from -329.84ppm / K to 521.41ppm / K after the introduction of the nickel-phosphorus insertion layer; when the annealing temperature is 300℃, the temperature coefficient of the buried barrier film increases from -423.56ppm / K to 512.41ppm / K after the introduction of the nickel-phosphorus insertion layer; when the annealing temperature is 400℃, the temperature coefficient of the buried barrier film increases from -263.15ppm / K to -96.94ppm / K after the introduction of the nickel-phosphorus insertion layer; when the annealing temperature is 500℃, the temperature coefficient of the buried barrier film changes from 94.66ppm / K to -4.87ppm / K after the introduction of the nickel-phosphorus insertion layer. It can be seen that the introduction of the insertion layer can significantly improve the thermal stability of the single-layer buried barrier film, and when the nickel-phosphorus-chromium-silicon-carbon thickness ratio is 1:1, the TCR is the smallest, which is -4.87ppm / K.

[0077] When the film thickness ratio is 30:30 (nm), the temperature coefficient changes from -188.41ppm / K before annealing to -4.87ppm / K after annealing at 500℃. The resistance temperature coefficient is reduced by 38 times, and the thermal stability is significantly improved. When the thickness ratio of chromium silicon carbon and nickel phosphorus films is 1:1, after annealing at 500℃, a new alloy layer is generated at the interface of the double-layer resistor, and the internal grain growth changes, so that its TCR can reach the optimal state.

[0078] The above experimental data can fully illustrate that adding suitable materials under the chromium silicon carbon resistor layer material helps to promote the stability of the electrical properties of the embedded thin film resistor material, maintain stable electrical properties in a wide temperature range (-55 ~ 125 ℃), and has a wide range of applications.

[0079] It should be noted that the above embodiments are not intended to limit the protection scope of the present invention, and equivalent changes or substitutions made on the basis of the above technical solutions all fall within the protection scope of the claims of the present invention.

Claims

1. An embedded resistor thin film material with extremely low resistance temperature coefficient, characterized in that: The material includes a substrate, a resistive layer, and an insertion layer, wherein the insertion layer is disposed between the substrate and the resistive layer.

2. The embedded resistor material with extremely low temperature coefficient of resistance according to claim 1, characterized in that: in, The substrate is set to Al2O3, the insertion layer is set to nickel phosphorus, and the resistance layer is set to chromium silicon carbon.

3. The embedded resistor material with extremely low temperature coefficient of resistance according to claim 1, characterized in that: In terms of thickness, in the embedded resistor material with an extremely low temperature coefficient of resistance, the total thickness of the film is 60 to 180 nanometers, of which the thickness of the resistor layer is 30 to 150 nanometers and the thickness of the insertion layer is 30 nanometers.

4. The embedded resistor thin film material with extremely low resistance temperature coefficient according to claim 1, characterized in that: The substrate is one or more of a ceramic substrate, a metal substrate, or a silicon substrate.

5. The embedded resistor thin film material with extremely low resistance temperature coefficient according to claim 1, characterized in that: The material of the resistance layer is CrSiC alloy, which contains 25% chromium, 50% silicon and 25% carbon in atomic percentage.

6. The embedded resistor thin film material with extremely low resistance temperature coefficient according to claim 1, characterized in that: The material of the insertion layer is NiP alloy, which contains 70% nickel and 30% phosphorus in atomic percentage.

7. The method for preparing the embedded resistor thin film material with extremely low resistance temperature coefficient according to any one of claims 1 to 6, characterized in that: The method comprises the following steps: Step 1: Select and install the sputtering targets corresponding to the resistor layer material and the insert layer material. Step 2: Select the substrate, Step 3: Use the photolithography process to make a resistor pattern on the substrate. Step 4: Place the substrate with the resistor pattern into the sputtering chamber, keep the chamber in a vacuum state, and perform the sputtering operation at a pressure of 10-5Pa. Step 5: Introduce argon gas and adjust the gas flow meter and the vent valve to keep the cavity pressure at around 0.9 Pa. Step 6: Start coating, use the target material corresponding to the resistance layer material for sputtering coating, so that it is deposited on the selected substrate; use the target material corresponding to the insertion layer material for sputtering coating, so that it is deposited on the resistance layer, the thickness of each deposited layer in the film is adjusted by the sputtering time or sputtering power, the chromium silicon carbon sputtering power is 50W, the sputtering time is 7 minutes and 36 seconds, 15 minutes and 12 seconds, 22 minutes and 48 seconds, 30 minutes and 24 seconds, 37 minutes and 58 seconds, the nickel phosphorus sputtering power is 50W, and the sputtering time is 7 minutes and 30 seconds, wherein the chromium silicon carbon-nickel phosphorus double-layer structure film structure is measured by thickness, with 2 to 30 nanometers of nickel phosphorus as the insertion layer film and 30 to 150 nanometers of chromium silicon carbon film as the top film.

8. The method for preparing an embedded resistor thin film material with an extremely low resistance temperature coefficient according to claim 7, characterized in that: When the sputtering method is used to perform the sputtering deposition step on the resistance layer material and the insertion layer material, the sputtering power of the target material corresponding to the resistance layer is 10 to 50W, and the sputtering power of the target material corresponding to the insertion layer is 10 to 50W.

9. The method for preparing an embedded resistor thin film material with an extremely low resistance temperature coefficient according to claim 7, characterized in that: After forming a resistor layer-insertion layer structure film on a substrate by sputtering, the obtained film needs to be subjected to high-temperature annealing. The high-temperature annealing process is carried out in a high vacuum environment or a protective gas atmosphere, with a specific temperature of 200°C to 500°C and a time of 30 minutes; the protective gas is an inert gas, including argon, nitrogen or helium.

10. The method for preparing an embedded resistor thin film material with an extremely low resistance temperature coefficient according to claim 7, characterized in that: In the step of forming a thin film of a resistor layer-insertion layer structure on a substrate by sputtering, the substrate is kept at room temperature during the sputtering process.

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