Semiconductor processing method, computer readable storage medium and terminal

Abstract

The embodiment of the invention relates to the field of semiconductor manufacturing, and provides a semiconductor manufacturing method, a computer readable storage medium and a terminal.The semiconductor manufacturing method comprises the steps that a wafer is provided, and the surface of the wafer has a first curvature; performing a deposition process on the wafer to form a compensation layer on the surface of the wafer; the wafer with the compensation layer has a second curvature, and the second curvature is smaller than the first curvature; wherein in the deposition process step, the flow of source gas in the deposition process is gradually increased. The semiconductor processing method provided by the embodiment of the invention at least can improve the warping of the wafer and improve the integration density.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor manufacturing, and in particular to a semiconductor process method, a computer-readable storage medium, and a terminal. Background Art

[0002] The processing of semiconductor products mainly includes wafer manufacturing (Front-End) and packaging (Back-End) testing. The production line of wafer manufacturing can be divided into 7 independent production areas: Thermal Process, Photolithography, Etch, Ion Implant, Dielectric Deposition, Chemical Mechanical Polishing (CMP), and Metallization. Packaging testing can be divided into cutting, cleaning, etching, metallization, packaging, and testing.

[0003] In the back-end packaging process of the wafer manufacturing process, due to the different internal stresses of the silicon substrate and the metal material, the wafer is prone to warping due to internal stress. After epitaxial growth, the warping still remains, which will bring difficulties to the subsequent device processing. In addition, although the internal stress and warping can be relieved by the stress relief film layer, it is necessary to improve the efficiency of the process method and the yield of the semiconductor structure under the conditions of limited thickness space and preparation cost. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor process method, a computer-readable storage medium, and a terminal, which are at least beneficial to improving the warpage of the wafer and increasing the integration density.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor process method, including: providing a wafer, the surface of the wafer having a first curvature; performing a deposition process on the wafer to form a compensation layer on the surface of the wafer; the wafer with the compensation layer has a second curvature, and the second curvature is smaller than the first curvature; wherein, in the deposition process step, the flow rate of the source gas of the deposition process gradually increases.

[0006] In some embodiments, the deposition process on the wafer includes: performing a first deposition process on the wafer to form a first compensation layer on the surface of the wafer; performing a second deposition process on the wafer to form a second compensation layer on the surface of the wafer; wherein a first flow rate of the source gas of the first deposition process is less than a second flow rate of the source gas of the second deposition process.

[0007] In some embodiments, the first flow rate presents an increasing trend; or the first flow rate is equal to a first constant value.

[0008] In some embodiments, the second flow rate presents an increasing trend or the second flow rate is equal to a second constant value.

[0009] In some embodiments, a ratio of the second flow rate to the first flow rate ranges from 2 to 6.

[0010] In some embodiments, the first flow rate ranges from 5 g / min to 10 g / min.

[0011] In some embodiments, the second flow rate ranges from 10 g / min to 30 g / min.

[0012] In some embodiments, the first deposition process includes at least a first stage and a second stage in succession, and a first sub-flow rate of the first stage is less than or equal to a second sub-flow rate of the second stage.

[0013] In some embodiments, either the first sub-flow or the second sub-flow presents an increasing trend; or, either the first sub-flow or the second sub-flow is equal to a fourth constant value.

[0014] In some embodiments, along a direction perpendicular to the wafer surface, a thickness of the first compensation layer ranges from 200 to 500 nm.

[0015] In some embodiments, performing a deposition process on the wafer includes: performing a third deposition process on the wafer to form a compensation layer on the surface of the wafer, and a third flow rate of the source gas in the third deposition process presents an increasing trend.

[0016] In some embodiments, the third deposition process includes a first interval and a second interval in succession, and a first flow rate increase rate of the first interval is greater than a second flow rate increase rate of the second interval.

[0017] In some embodiments, the size of the first flow growth rate presents an increasing region or the first flow growth rate is equal to a third constant value.

[0018] In some embodiments, the third flow rate range of the first interval is 5 g / min to 15 g / min.

[0019] In some embodiments, the fourth flow rate range of the second interval is 15 g / min to 40 g / min.

[0020] According to some embodiments of the present disclosure, on the other hand, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the semiconductor process method as described in any one of the above embodiments is implemented.

[0021] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a terminal, wherein the terminal includes a processor and a memory, wherein the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the terminal executes the semiconductor process method as described in any one of the above embodiments.

[0022] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0023] In the semiconductor process method provided by the embodiment of the present disclosure, a deposition process is performed on a wafer to form a compensation layer on the surface of the wafer. The wafer with the compensation layer has a second curvature, and the second curvature is smaller than the first curvature. The stress on the surface of the wafer is relieved by depositing the compensation layer. In the steps of the deposition process, the flow rate of the resent gas in the deposition process gradually increases, and the stress of the compensation layer can be increased by controlling the flow rate, thereby avoiding the formation of a thick compensation layer and reducing the integration density of the semiconductor structure. In addition, by changing the flow rate of the deposition process, a balance is achieved between the stress of the compensation layer itself and the stress of the wafer, so as to make the second curvature smaller than the first curvature as much as possible, thereby avoiding the situation where the compensated wafer has compressive stress or tensile stress, thereby causing the chip to warp upward or downward. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A flowchart of a semiconductor process method provided by an embodiment of the present disclosure;

[0026] Figure 2 to Figure 7 A schematic diagram of a semiconductor structure corresponding to each step of a semiconductor manufacturing method provided in an embodiment of the present disclosure;

[0027] Figure 8A data diagram showing the corresponding relationship between the flow rate of source gas and the stress of the compensation layer in a deposition process in a semiconductor process method provided by an embodiment of the present disclosure;

[0028] Figures 9 to 15 A data graph showing the flow rate of source gas and time corresponding to a deposition process in a semiconductor process method provided by an embodiment of the present disclosure;

[0029] Fig.16 A structural block diagram of a terminal provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] As known from the background art, the wafers prepared by the current semiconductor manufacturing process are relatively thick and have a warping problem.

[0031] The disclosed embodiment provides a semiconductor process method, wherein a deposition process is performed on a wafer to form a compensation layer on the surface of the wafer, wherein the wafer having the compensation layer has a second curvature, and the second curvature is smaller than the first curvature, and the stress on the surface of the wafer is relieved by depositing the compensation layer. In the steps of the deposition process, the flow rate of the resent gas in the deposition process is gradually increased, and the stress of the compensation layer can be increased by controlling the flow rate, thereby avoiding a thicker thickness of the formed compensation layer and reducing the integration density of the semiconductor structure. In addition, by changing the flow rate of the deposition process, a balance is achieved between the stress of the compensation layer itself and the stress of the wafer, thereby making the second curvature smaller than the first curvature as much as possible, thereby avoiding the situation where the compensated wafer has compressive stress or tensile stress, thereby causing the chip to warp upward or downward.

[0032] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0033] Figure 1 A flowchart of a semiconductor process method provided by an embodiment of the present disclosure; Figure 2 to Figure 7 A schematic diagram of a semiconductor structure corresponding to each step of a semiconductor manufacturing method provided in an embodiment of the present disclosure; Figure 8 A data diagram showing the corresponding relationship between the flow rate of source gas and the stress of the compensation layer in a deposition process in a semiconductor process method provided by an embodiment of the present disclosure; Figures 9 to 15 This is a data graph showing the flow rate of source gas and time corresponding to a deposition process in a semiconductor process method provided by an embodiment of the present disclosure.

[0034] refer to Figures 1 to 15According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor process method to improve the warpage problem of a wafer in a limited thickness space.

[0035] The semiconductor process method provided in the embodiment of the present disclosure can be applied to thin film preparation equipment in a variety of process equipment. The thin film preparation equipment can be a chemical vapor deposition equipment and a physical vapor deposition equipment. The chemical vapor deposition process includes atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), laser induced chemical vapor deposition (LCVD), metal organic chemical vapor deposition (MOCVD), plasma chemical vapor deposition (PECVD), etc. The chemical vapor deposition equipment can be a chemical vapor deposition equipment of any manufacturer. For example, the chemical vapor deposition equipment can be any one of a TEL-HPTI chamber, a TEL-SFD / ASFD TIN / TSN / TION chamber or a MOCVD chamber. The embodiment of the present disclosure is described by taking the process equipment as a TEL-HPTI chamber as an example.

[0036] In some embodiments, the process equipment includes a double dual slot load lock (DDSL), a transfer chamber, a process chamber (PC), and an RPSC unit. The DDSL is used to cool down the incoming wafer or structure or the wafer of the structure that has been coated; the transfer chamber is used to complete the vacuum robot arm to take the wafer from the DDSL and put it into the reaction chamber under a vacuum environment, and take out the wafer that has been coated in the reaction chamber and put it into the DDSL; the PC is the film forming process chamber of the process equipment; the RPSC unit is used to clean the PC chamber.

[0037] In some embodiments, the components of the device include a shower head, an O-ring, or an RPSC tube. The shower head is used to spray the source material. A plurality of step-shaped shower holes are arranged on the shower head. The shower holes are composed of a circular hole with a larger diameter at the top and a circular hole with a smaller diameter at the bottom. By gradually increasing one or more parameters of the step depth, the aperture of the large hole, and the aperture of the small hole from the center to the edge of the shower head plate, the impedance of the shower head plate is gradually reduced from the center to the edge, and the expected air flow is gradually increased, so that the impedance distribution of the shower head plate is adjusted, and the air flow distribution in the process chamber is adjusted. The O-ring is used to ensure that the chamber is in a sealed state; the RPSC tube is used to transmit cleaning gas to clean the PC chamber.

[0038] The process equipment further includes: a first gas supply component for supplying a first reaction gas; a second gas supply component for supplying a second reaction gas; and a third gas supply component for supplying an inert gas.

[0039] refer to Figure 1 as well as Figure 2 The semiconductor process method includes: providing a wafer 100, wherein a surface of the wafer 100 has a first curvature.

[0040] In some embodiments, the wafer 100 may be a pure substrate in a conventional design or a wafer that has been subjected to other semiconductor process technology and has a certain thin film formed on the surface of the substrate. The material of the substrate may be a semiconductor material, and the semiconductor material includes any one of single crystal silicon, silicon germanium, silicon carbide, germanium, polycrystalline silicon or doped single crystal silicon.

[0041] It is worth noting that curvature refers to the degree of curvature of a long rolled piece (profile, rod, tube) in the length direction. The chord height of the curvature per meter is the curvature per meter; the ratio of the total chord height of the total length of the curvature to the total length is the total curvature. In the embodiment of the present disclosure, the distance S between the highest point and the lowest point of the wafer 100 represents the magnitude of the curvature. Therefore, the first distance S1 is used to represent the magnitude of the first curvature.

[0042] The process method further includes: providing a carrier 101, and the crystal is located on the carrier 101. The surface of the wafer 100 has a first curvature, which may refer to the wafer 100 having a tensile stress, that is, the side of the wafer 100 away from the carrier 101 is concave and bent toward the carrier 101. The first curvature of the wafer 100 may refer to the wafer 100 having a compressive stress, that is, the side of the wafer 100 away from the carrier 101 is convex and bent toward the carrier 101.

[0043] In some embodiments, the wafer 100 has an array area, a peripheral area, and a cutting area, and the array area, the peripheral area, and the cutting area have transistors, metal interconnect structures, interlayer dielectrics (ILD) and / or intermetal dielectrics (IMD) (not shown). Among them, the metal interconnect structure can be a metal interconnect layer in a general back-end manufacturing process, such as M1 / M2 / M3 and other metal interconnect layers, and its material can be an aluminum-copper alloy, which can be formed by a physical vapor deposition manufacturing process or various chemical vapor deposition manufacturing processes, and then patterned by a photolithography manufacturing process. Different metal interconnect layers can be electrically interconnected by vias (via, not shown). The metal interconnect structure is exposed on the surface of the wafer 100.

[0044] refer to Figure 3 The process method includes: performing a deposition process on a wafer 100 to form a compensation layer 110 on a surface of the wafer 100; the wafer 100 with the compensation layer 110 has a second curvature, which is smaller than the first curvature. The compensation layer 110 covers the metal interconnection structure.

[0045] In this way, the wafer 100 with the compensation layer 110 has a second curvature, which is smaller than the first curvature, and the stress on the surface of the wafer 100 is relieved by depositing the compensation layer 110. In the steps of the deposition process, the flow rate of the source gas in the deposition process is gradually increased, and the stress of the compensation layer 110 can be increased by controlling the flow rate, thereby avoiding the formation of a thick compensation layer 110 and reducing the integration density of the semiconductor structure.

[0046] In some embodiments, the material of the compensation layer 110 includes silicon oxide, silicon nitride or TEOS (tetraethylorthosilicate). When the material of the compensation layer 110 is TEOS, the thickness and quality of the silicon oxide can be controlled by reaction conditions (such as temperature, pressure and reaction time), thereby ensuring the high quality of the prepared silicon oxide. In addition, TEOS reacts at a lower temperature and is cheaper, thereby saving costs and improving production efficiency.

[0047] Based on this, the first reaction gas is TEOS gas, and the second reaction gas is oxygen. The first gas supply component is used to provide TEOS gas; the second gas supply component is used to provide oxygen.

[0048] In some embodiments, reference Figure 8 , the stress of the compensation layer 110 is inversely correlated with the flow rate of the first reaction gas in the deposition process. That is, the greater the flow rate of the first reaction gas, the smaller the stress of the compensation layer 110.

[0049] Based on this, the embodiment of the present disclosure designs a deposition process step in which the flow rate of the source gas in the deposition process gradually increases. In this way, within a limited thickness, the stress of the compensation layer 110 itself and the stress of the wafer 100 are balanced by changing the flow rate of the deposition process, so as to make the second curvature smaller than the first curvature as much as possible, thereby avoiding the situation where the wafer 100 after compensation has compressive stress or tensile stress, thereby causing the chip to warp upward or downward.

[0050] The second curvature is represented by the second distance S2. It can be understood that the second distance S2 can refer to Figure 3 The distance between the highest point far from the stage and the lowest point close to the stage shown in the figure can also be referred to as Figure 4 The distance between the highest point away from the stage and the lowest point close to the stage is shown.

[0051] In some embodiments, the compensation layer 110 has a second stress, which is a compressive stress or a tensile stress, thereby improving the degree of warpage of the wafer 100. The wafer 100 itself has a first stress, and the compensation layer 110 reduces the curvature of the wafer 100 when the tensile stress or the compressive stress is applied, thereby reducing the warpage of the wafer 100, thereby eliminating the warpage phenomenon, obtaining a flat composite wafer 100, and making a high-precision lithography process possible.

[0052] The second curvature approaches 0 infinitely, or deviates by 5% above or below, thereby ensuring that the warpage of the wafer 100 is small or there is no warpage to meet the process requirements.

[0053] In some embodiments, reference Figure 3 , the second stress magnitude of the compensation layer 110 may be smaller than the first stress magnitude of the wafer 100, thereby relieving the stress of the wafer 100 but the wafer 100 still has a second curvature less than 5%. Figure 5 , the second stress of the compensation layer 110 can be equal to the first stress of the wafer 100, that is, the second curvature is equal to 0. Figure 4 The second stress of the compensation layer 110 may be greater than the first stress of the wafer 100 , thereby relieving the stress of the wafer 100 while the wafer 100 warps in the opposite direction, and the wafer 100 has a second curvature less than 5%.

[0054] In some embodiments, the deposition process on the wafer 100 includes: Figure 6 , a first deposition process is performed on the wafer 100 to form a first compensation layer 111 on the surface of the wafer 100 .

[0055] The first compensation layer 111 has a third curvature, and the magnitude of the third curvature is represented by a third distance S3.

[0056] In some embodiments, the thickness of the first compensation layer 111 is in the range of 200 to 500 nm along the direction perpendicular to the surface of the wafer 100. The thickness of the first compensation layer 111 may be 200 nm to 245 nm, 245 nm to 286 nm, 286 nm to 331 nm, 331 nm to 375 nm, 375 nm to 412 nm, 412 nm to 459 nm, or 459 nm to 500 nm. The thickness range of the first compensation layer 111 is used to ensure that there is enough high-stress compensation layer 110 to offset the stress of the wafer 100, thereby improving the warpage problem. The thickness range of the first compensation layer 111 is also used to ensure that the thickness of the entire first compensation layer 111 is small, thereby preventing the proportion of the high-stress first compensation layer 111 from being small, thereby reducing various adverse effects on the integrated circuit. The first compensation layer 111 is thin, so that it has better adhesion with the metal (such as aluminum) on the wafer 100, and it is not easy to be stripped from the wafer 100.

[0057] refer to Figure 7 , a second deposition process is performed on the wafer 100 to form a second compensation layer 112 on the surface of the wafer 100; wherein the first flow rate of the source gas in the first deposition process is less than the second flow rate of the source gas in the second deposition process. In this way, the warpage of the wafer 100 is improved macroscopically by the first deposition process, and then the warpage of the wafer 100 is microscopically regulated by the second deposition process, thereby accurately improving the warpage of the wafer 100, avoiding hidden cracks of the wafer 100 and errors in subsequent alignment, thereby reducing the yield of the semiconductor process.

[0058] In some embodiments, the thickness of the first compensation layer 111 is less than the thickness of the second compensation layer 112 , thereby reducing the impact of high-stress film layers on integrated circuits and improving the yield of integrated circuits and semiconductor structures.

[0059] The second compensation layer 112 has a large thickness and a high film density, thereby improving the insulation performance and reducing the leakage current. Since the second compensation layer 112 is deposited on the first compensation layer 111, the combination between the two is still reliable. Therefore, the compensation layer 110 manufactured by the manufacturing method provided by the embodiment of the present disclosure not only maintains good insulation performance, but also is not easy to fall off from the wafer 100, thereby ensuring the performance stability of the final product.

[0060] In some embodiments, the ratio of the second flow rate to the first flow rate is in the range of 2 to 6. The ratio of the second flow rate to the first flow rate may be 2.1, 2.8, 3.3, 3.7, 4.1, 4.5, 5, 5.28 or 6. When the ratio of the second flow rate to the first flow rate is within the above range, it can be ensured that the first compensation layer 111 accounts for a small proportion and has a high stress, thereby reducing the proportion of the high stress film layer, thereby reducing the impact of the high stress film layer on the wafer 100 and the integrated circuit, and avoiding problems such as hidden cracks and damage to the wafer 100.

[0061] In some embodiments, the first flow rate ranges from 5 g / min to 10 g / min. The first flow rate can be 5.2 g / min, 5.79 g / min, 6.23 g / min, 6.81 g / min, 7.25 g / min, 7.9 g / min, 8.3 g / min, 8.9 g / min or 10 g / min. When the first flow rate is within any of the above ranges or values, the first compensation layer 111 formed by deposition has a higher stress, which can offset the stress of the wafer 100, so that the wafer 100 is improved from the first curvature to the second curvature. The first flow rate is also used to ensure that the first compensation layer 111 can offset the stress of the wafer 100, while the thickness of the first compensation layer 111 is small, thereby reducing the impact of the high-stress first compensation layer 111 on the wafer 100.

[0062] In some embodiments, the second flow rate ranges from 10 g / min to 30 g / min. The second flow rate can be 10.2 g / min, 13.2 g / min, 15.6 g / min, 18.1 g / min, 21.2 g / min, 23.2 g / min, 25.8 g / min, 28.4 g / min or 30 g / min. When the second flow rate is within any of the above ranges or values, the stress of the second compensation layer 112 is low stress or neutral stress.

[0063] In some embodiments, the difference between the first curvature and the third curvature is greater than the difference between the second curvature and the third curvature, so as to ensure that the compensation layer 110 can offset the stress of the wafer 100 , thereby improving the warping problem of the wafer 100 .

[0064] In some embodiments, the duration of the first deposition process is t1, and the thickness of the first compensation layer is controlled by controlling the duration of the first deposition process.

[0065] In some embodiments, reference Fig. 9 , the first flow rate is equal to the first constant value N1, and the second flow rate is equal to the second constant value N2. Fig.10 or Fig.11 , the first flow rate shows an increasing trend, and the second flow rate is equal to the second constant value N2. Fig.12, the first flow rate is equal to the first constant value N1, and the second flow rate shows an increasing trend. The first flow rate shows an increasing trend, and the second flow rate shows an increasing trend.

[0066] The embodiment of the present disclosure does not limit the growth rate of the first flow and the growth rate of the second flow, that is, the integral of the first flow is a constant value, decreasing or increasing, and the integral of the second flow is a constant value, decreasing or increasing, which are all within the protection scope of the embodiment of the present disclosure.

[0067] In some embodiments, reference Fig.13 The first deposition process includes at least a first stage T1 and a second stage T2, wherein the first sub-flow rate of the first stage T1 is less than or equal to the second sub-flow rate of the second stage T2. The thickness of the high stress film layer is further reduced, thereby reducing the adverse effects on the integrated circuit.

[0068] In some embodiments, either the first subflow or the second subflow presents an increasing trend; or, either the first subflow or the second subflow is equal to the fourth constant value N4. Fig.13 , the first sub-flow is equal to the fourth constant value N4, and the second sub-flow presents an increasing trend. Fig.14 , the first subflow presents an increasing trend, and the second subflow is equal to the fourth constant value N4. For another example, the first subflow and the second subflow both present an increasing trend. For another example, the first subflow is equal to the fourth constant value N4, the second subflow is equal to the sixth constant value N6, and the sixth constant value N6 is greater than the fourth constant value N4.

[0069] In some embodiments, a low-frequency RF power source is used for ionization during the first deposition process. By using a low-frequency RF power source to ionize the raw material gas, not only the reaction efficiency is improved, but also the deposited first compensation layer 111 can have better density, that is, the insulation performance of the first compensation layer 111 can be improved. In this way, the insulation performance of the compensation layer can be improved and the leakage current can be reduced.

[0070] In some embodiments, reference Figure 3 as well as Fig.15 The deposition process for the wafer 100 includes: performing a third deposition process on the wafer 100 to form a compensation layer 110 on the surface of the wafer 100, and the third flow rate of the source gas in the third deposition process presents an increasing trend. In this way, the compensation layer 110 is formed through a single deposition process, which reduces the complexity of the process and saves the waiting time between multiple deposition processes, thereby improving the process efficiency.

[0071] In some embodiments, the third deposition process includes a first interval T3 and a second interval T4 in succession, and a first flow rate increase rate of the first interval T3 is greater than a second flow rate increase rate of the second interval T4.

[0072] In some embodiments, the magnitude of the first flow rate increase presents an increasing region or the first flow rate increase is equal to a third constant value.

[0073] In some embodiments, the third flow rate range of the first interval T3 is 5 g / min to 15 g / min.

[0074] In some embodiments, the fourth flow rate range of the second interval T4 is 15 g / min to 40 g / min.

[0075] In some embodiments, the device also includes a flow monitor, which is used to monitor the flow rates of the first reaction gas, the second reaction gas, and the inert gas throughout the entire process, thereby ensuring that the flow rate of the source gas is discharged according to a preset design, and further ensuring that the source gas content in the chamber satisfies the requirement that the compensation layer 110 has a relatively thin thickness and a relatively large stress, thereby solving the warping problem of the wafer 100 and reducing the thickness of the wafer 100, thereby increasing the integration density of the integrated circuit in the vertical direction.

[0076] In some embodiments, after forming the compensation layer 110, annealing / curing is performed, which converts the low-density compensation layer 110 into a high-density compensation layer 110. According to some embodiments of the present disclosure, the annealing is performed in an oxygen-containing environment. The annealing temperature may be higher than about 200° C., for example, in a temperature range between about 200° C. and about 700° C. During the thermal treatment, an oxygen-containing process gas is introduced into the process chamber in which the wafer 100 is placed. The oxygen-containing process gas may include oxygen (O 2 ), ozone (O 3 ) or a combination thereof. Steam (H 2 O) can also be used, and can be used without oxygen or ozone, or can be used in combination with oxygen and / or ozone. During annealing, the compensation layer 110 protects the main part of the wafer 100 from oxidation. And the compensation layer 110 is dense (has a high density), and thus improves its ability to prevent water and oxygen from penetrating.

[0077] In some embodiments, the material of the compensation layer 110 is TEOS, and the annealing step is used to transform the TEOS into dense silicon oxide.

[0078] In the semiconductor process method provided by the embodiment of the present disclosure, a deposition process is performed on a wafer 100 to form a compensation layer 110 on the surface of the wafer 100. The wafer 100 having the compensation layer 110 has a second curvature, which is smaller than the first curvature. The stress on the surface of the wafer 100 is relieved by depositing the compensation layer 110. In the steps of the deposition process, the flow rate of the source gas in the deposition process is gradually increased, and the stress of the compensation layer 110 can be increased by controlling the flow rate, thereby avoiding the formation of a thicker thickness of the compensation layer 110 and reducing the integration density of the semiconductor structure. In addition, by changing the flow rate of the deposition process, a balance is achieved between the stress of the compensation layer 110 itself and the stress of the wafer 100, so as to make the second curvature smaller than the first curvature as much as possible, thereby avoiding the situation where the compensated wafer 100 has compressive stress or tensile stress, thereby causing the chip to warp upward or downward.

[0079] Accordingly, according to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the semiconductor process method as described in any one of the above embodiments is implemented.

[0080] In some embodiments, the computer-readable storage medium may include, but is not limited to, a floppy disk, an optical disk, a compact disk-read only memory CD-ROM, a magneto-optical disk, a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphic double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or it may be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc., a magnetic card or an optical card, a flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions. In addition, the computer-readable storage medium may be a product that is not connected to a computer device, or it may be a component that is connected to a computer device for use.

[0081] Fig.16 A structural block diagram of a terminal provided in one embodiment of the present disclosure.

[0082] Accordingly, some embodiments of the present disclosure provide a terminal according to another aspect, Fig.16The terminal 20 includes a processor 22 and a memory 21, the memory 21 is used to store computer programs, and the processor 22 is used to execute the computer programs stored in the memory 21, so that the terminal 20 executes the semiconductor process method as any one of the above embodiments.

[0083] In some embodiments, the processor 22 may be a general-purpose processor, including one or more central processing units (CPUs), network processors (NPs), etc.; it may also be a microcontroller unit (MCU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The memory 21 may include, but is not limited to, a high-speed random access memory, a non-volatile memory, such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. Random access memory includes dynamic random access memory DRAM, synchronous dynamic random access memory SDRAM, double data rate synchronous dynamic random access memory DDR SDRAM, low power double data rate synchronous dynamic random access memory LPDDR SDRAM, graphic double data rate synchronous dynamic random access memory GDDR SDRAM, double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, thyristor random access memory TRAM, etc.; non-volatile memory includes phase change random access memory PRAM, magnetic random access memory MRAM, resistive random access memory RRAM, etc., magnetic card or optical card, flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions.

[0084] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor manufacturing method, characterized in that: include: Providing a wafer, wherein a surface of the wafer has a first curvature; Performing a deposition process on the wafer to form a compensation layer on the surface of the wafer; The wafer with the compensation layer has a second curvature, and the second curvature is smaller than the first curvature; Wherein, in the deposition process step, the flow rate of the source gas of the deposition process is gradually increased.

2. The semiconductor process method according to claim 1, characterized in that: The deposition process on the wafer includes: performing a first deposition process on the wafer to form a first compensation layer on the surface of the wafer; A second deposition process is performed on the wafer to form a second compensation layer on the surface of the wafer; wherein a first flow rate of the source gas in the first deposition process is less than a second flow rate of the source gas in the second deposition process.

3. The semiconductor process method according to claim 2, characterized in that: The first flow rate presents an increasing trend; or the first flow rate is equal to a first constant value.

4. The semiconductor process method according to claim 2 or 3, characterized in that: The second flow rate presents an increasing trend or the second flow rate is equal to a second constant value.

5. The semiconductor process method according to claim 2 or 4, characterized in that: The ratio of the second flow rate to the first flow rate ranges from 2 to 6.

6. The semiconductor process method according to claim 3 or 5, characterized in that: The first flow rate ranges from 5 g / min to 10 g / min.

7. The semiconductor process method according to claim 4 or 5, characterized in that: The second flow rate ranges from 10 g / min to 30 g / min.

8. The semiconductor process method according to claim 2, wherein: The first deposition process at least includes a first stage and a second stage in succession, and a first sub-flow rate of the first stage is less than or equal to a second sub-flow rate of the second stage.

9. The semiconductor process method according to claim 8, characterized in that: Either the first sub-flow or the second sub-flow presents an increasing trend; or either the first sub-flow or the second sub-flow is equal to a fourth constant value.

10. The semiconductor process method according to claim 2, wherein: Along a direction perpendicular to the wafer surface, the thickness of the first compensation layer ranges from 200 to 500 nm.

11. The semiconductor process method according to claim 1, wherein: The deposition process performed on the wafer includes: performing a third deposition process on the wafer to form a compensation layer on the surface of the wafer, and a third flow rate of the source gas in the third deposition process presents an increasing trend.

12. The semiconductor process method according to claim 11, characterized in that: The third deposition process includes a continuous first interval and a second interval, and a first flow rate increase rate of the first interval is greater than a second flow rate increase rate of the second interval.

13. The semiconductor process method according to claim 12, wherein: The magnitude of the first flow growth rate presents an increasing region or the first flow growth rate is equal to a third constant value.

14. The semiconductor process method according to claim 12, wherein: The third flow rate range of the first interval is 5 g / min to 15 g / min.

15. The semiconductor process method according to claim 12, wherein: The fourth flow rate range of the second interval is 15 g / min to 40 g / min.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the semiconductor process method according to any one of claims 1 to 15 is implemented.

17. A terminal, characterized in that: The terminal includes a processor and a memory, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the terminal executes the semiconductor process method according to any one of claims 1 to 15.

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