Patterning method of semiconductor structure and semiconductor structure

Abstract

The invention provides a patterning method of a semiconductor structure and the semiconductor structure. The patterning method comprises the following steps: providing a substrate; depositing a protective layer on one side of the substrate; depositing a carbon film on one side, deviating from the substrate, of the protective layer through a spin coating process to form a hard mask layer; the hard mask layer is etched, and etching is stopped at the protection layer; and performing through hole etching by taking the hard mask layer as a mask. The carbon thin film is deposited through the spin coating process to form the hard mask layer, and the hard mask layer is used as a hard mask used during patterning, so that the higher process node requirement of the subsequent process of a chip in the semiconductor manufacturing process is met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor process technology, and in particular to a patterning method of a semiconductor structure and a semiconductor structure. Background Art

[0002] As process nodes become smaller, trenches become deeper, and aspect ratios become larger, the existing TiN used as a hard mask for patterning can no longer meet process requirements and cannot meet the higher process node requirements of BEOL (Back-end of Line, the chip back-end process in semiconductor manufacturing), which is specifically reflected in the following points:

[0003] (1) When the TiN hard mask is used to pattern processes with a pitch below 80 nm, in order to solve the problem of insufficient through-hole metal yield caused by lithography-etching-lithography-etching (LELE) misalignment, a relatively thick TiN hard mask layer needs to be deposited, making the metal copper filling process more difficult.

[0004] (2) As the process node increases, the aspect ratio (A / R) becomes larger and larger (greater than 20:1), and the TiN hard mask becomes thicker and thicker, which will cause the photoresist to be too thick and collapse.

[0005] (3) When forming the TiN hard mask, time-dependent crystal growth (Titanium Chip on Film, TiCOF) residues may form between inline etching and metal deposition, which can hinder subsequent processes such as copper filling. Research and solution to this phenomenon is a direction for continuous optimization of semiconductor processes.

[0006] (4) As the deposition temperature increases, the resistivity of the TiN hard mask decreases, the surface roughness increases, and the step coverage deteriorates.

[0007] Based on this, it is necessary to provide a new patterning method for semiconductor structures to improve the defects of the prior art in which a TiN hard mask is used for patterning.

[0008] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0009] In response to the problems in the prior art, the purpose of the present application is to provide a patterning method and a semiconductor structure of a semiconductor structure, in which a carbon film is deposited by a spin coating process to form a hard mask layer, which serves as a hard mask for patterning to meet the higher process node requirements of the back-end chip process in the semiconductor manufacturing process.

[0010] The present application provides a method for patterning a semiconductor structure, comprising:

[0011] providing a substrate;

[0012] depositing a protective layer on one side of the substrate;

[0013] Depositing a carbon film on a side of the protective layer away from the substrate by a spin coating process to form a hard mask layer;

[0014] Etching the hard mask layer, and stopping the etching at the protective layer;

[0015] The through hole is etched using the hard mask layer as a mask.

[0016] In some embodiments, depositing a protective layer on one side of the substrate comprises the following steps:

[0017] Depositing a metal diffusion protection layer on one side of the substrate;

[0018] An oxide protection layer is deposited on a side of the metal diffusion protection layer facing away from the substrate.

[0019] In some embodiments, depositing a protective layer on one side of the substrate comprises the following steps:

[0020] Depositing a metal diffusion protection layer on one side of the substrate;

[0021] Depositing an intermetallic dielectric layer on a side of the metal diffusion protection layer facing away from the substrate;

[0022] An oxide protection layer is deposited on a side of the intermetallic dielectric layer away from the metal diffusion protection layer.

[0023] In some embodiments, the intermetallic dielectric layer is made of ultra-low dielectric constant material.

[0024] In some embodiments, etching the hard mask layer comprises the following steps:

[0025] forming a photoresist layer on a side of the hard mask layer away from the protective layer;

[0026] The hard mask layer is etched using the photoresist layer as a mask.

[0027] In some embodiments, forming a photoresist layer on a side of the hard mask layer away from the hard mask layer comprises the following steps:

[0028] forming a bottom anti-reflective coating on a side of the hard mask layer facing away from the protective layer;

[0029] A photoresist layer is formed on a side of the bottom anti-reflective coating layer away from the hard mask layer.

[0030] In some embodiments, after etching the hard mask layer using the photoresist layer as a mask, the following steps are further included:

[0031] A wet stripping process is used to remove the remaining photoresist layer and bottom anti-reflective coating.

[0032] In some embodiments, after etching the through hole using the hard mask layer as a mask, the following steps are further included:

[0033] Removal of polymer from the surface, bottom and sidewalls by chemical agents;

[0034] Clean the internal moisture and air by purging and baking.

[0035] In some embodiments, the polymer on the surface, bottom and sidewalls is removed by a chemical reagent, hydrogen fluoride, and the water vapor and air inside are purged by nitrogen purge and baking.

[0036] The embodiment of the present application also provides a semiconductor structure obtained by adopting the patterning method of the semiconductor structure.

[0037] The semiconductor structure patterning method and semiconductor structure provided in the present application have the following advantages:

[0038] By adopting this application, a carbon film is deposited through a spin coating process to form a hard mask layer as a hard mask used during patterning, and the good planarization characteristics and good gap filling ability of the spin carbon hard mask are utilized to achieve patterning of smaller contact holes, solve the problem of exposure glue backflow in narrow process windows with a size higher than 65nm, and the problem of difficult metal filling, etc., thereby meeting the higher process node requirements of chip back-end processes in semiconductor processes and effectively improving the performance of semiconductor devices. This patterning method can be used for any metal layer process of metal wiring in semiconductor devices, and is suitable for wide promotion and application.

[0039] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments with reference to the following drawings. The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without paying creative work.

[0041] Figure 1 is a flow chart of a method for patterning a semiconductor structure according to an embodiment of the present application;

[0042] Figure 2 is a schematic diagram of an embodiment of the present application after the contact hole manufacturing process is completed;

[0043] Figure 3 This is a schematic diagram of an embodiment of the present application after the protective layer is completed;

[0044] Figure 4 is a schematic diagram of an embodiment of the present application after a hard mask layer is formed;

[0045] Figure 5 is a schematic diagram of an embodiment of the present application after a photoresist layer is formed;

[0046] Figure 6 is a schematic diagram of a hard mask layer after photolithography according to an embodiment of the present application;

[0047] Figure 7 It is a schematic diagram of through-hole etching through a hard mask layer according to an embodiment of the present application. DETAILED DESCRIPTION

[0048] The example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present application will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. "Or" and "or" in the specification may both represent "and" or "or". Spatial relationship terms such as "on..." and the like can be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented to be "under..." other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptions used herein are interpreted accordingly.

[0049] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Although "first" or "second" etc. are used in this specification to represent certain features, they are only used to represent the role, and are not used as a limitation on the number and importance of specific features.

[0050] In the prior art, TiN thin film is generally used as a hard mask for patterning. However, as the process nodes become smaller, the grooves become deeper, and the aspect ratio becomes larger, the existing TiN used as a hard mask for patterning can no longer meet the process requirements and cannot meet the higher process node requirements of BEOL (Back-end of Line, the chip back-end process in the semiconductor process). Based on this, the embodiment of the present application provides a new patterning method for a semiconductor structure and a semiconductor structure obtained by using the patterning method, which meets the higher process node requirements of the chip back-end process in the semiconductor process by using spin carbon as a hard mask used for patterning.

[0051] like Figure 1 As shown, an embodiment of the present application provides a method for patterning a semiconductor structure, comprising:

[0052] S100: providing a substrate;

[0053] S200: depositing a protective layer on one side of the substrate;

[0054] In this embodiment, for example, the protective layer is deposited by using a chemical vapor deposition process (CVD);

[0055] S300: depositing a carbon film on a side of the protective layer away from the substrate by a spin coating process to form a hard mask layer;

[0056] Specifically, a carbon film is deposited on one side of the protective layer by a spin coating process in which the carbon film is deposited while rotating, so as to form a spin-on carbon (SOC) layer as a hard mask layer for pattern transfer;

[0057] The spin coating process, also known as the spin coating process, is a process that uses the centrifugal force generated by rotation to evenly spread sols, solutions or suspensions on the surface of the substrate to form a thin film. The basic principle is that when the substrate rotates at high speed driven by a motor, the coating material dripped on the substrate will be affected by the centrifugal force; the centrifugal force causes the coating material to diffuse from the center to the edge of the substrate, forming a uniform thin film on the surface of the substrate. As the solvent evaporates, the solute in the coating material gradually solidifies, and finally forms a solid film on the substrate.

[0058] S400: etching the hard mask layer, and stopping the etching at the protective layer;

[0059] S500: performing through-hole etching using the hard mask layer as a mask.

[0060] By adopting the present application, after depositing a protective layer on one side of the substrate through steps S100 and S200, a carbon film is deposited through a spin coating process to form a hard mask layer in step S300 as a hard mask used in patterning. SOC can form a uniform and smooth film on the surface of the protective layer, effectively fill the uneven areas at the microscopic level, and achieve an excellent flattening effect, which is crucial for the manufacture of semiconductor devices, because a flat surface helps the subsequent process steps such as photolithography and etching to be carried out accurately, and improves the performance and yield of the device; SOC has a relatively low dielectric constant, which can reduce the capacitance effect, reduce the delay and power consumption during signal transmission. In high-speed integrated circuits, materials with low dielectric constants help to increase signal transmission speed and reduce energy consumption; SOC has good thermal stability and can maintain stable physical and chemical properties at higher temperatures. In the semiconductor manufacturing process, it will undergo multiple high-temperature process steps, such as annealing, chemical vapor deposition, etc. The thermal stability of the SOC material ensures that it will not decompose or deteriorate during these processes, thereby ensuring the reliability of the device.

[0061] Compared with traditional chemical vapor deposition and physical vapor deposition (PVD), spin carbon has the characteristics of low cost, short process time and high production capacity, which is conducive to improving the preparation efficiency of semiconductor devices. The high corrosion resistance and good gap filling properties of spin carbon can achieve fine patterning with high aspect ratio (A / R). Spin carbon reacts easily with oxygen (O2) plasma and can be repeatedly deposited (reworked) to solve the problems caused by hard mask in the process, and solve the defect that TiN hard mask cannot be easily reworked in the prior art.

[0062] In the present application, based on the hard mask layer, etching is performed through steps S400 and S500 to achieve patterning of the semiconductor structure. The present application utilizes the good planarization characteristics and good gap filling capability of the spin carbon hard mask to achieve patterning of smaller contact holes, solve the problem of exposure glue backflow in narrow process windows with a size of more than 65nm, the problem of difficult metal filling, etc., thereby meeting the higher process node requirements of chip back-end processes in semiconductor processes and effectively improving the performance of semiconductor devices. The patterning method can be used for any metal layer process of metal wiring in semiconductor devices, and is suitable for wide promotion and application.

[0063] In one embodiment, the step S200 of depositing a protective layer on one side of the substrate comprises the following steps:

[0064] A metal diffusion protection layer is deposited on one side of the substrate; in this embodiment, the metal diffusion protection layer is deposited by a chemical vapor deposition process, and the metal diffusion protection layer is, for example, a SiCN (silicon carbide nitride) film, and SiCN has high hardness, high strength and good wear resistance, has good thermal stability, and can maintain a stable structure and performance in a high temperature environment; however, the present application is not limited thereto, and in other implementations, the metal diffusion protection layer may also be a film of other materials, which also falls within the protection scope of the present application;

[0065] An oxide protection layer is deposited on a side of the metal diffusion protection layer facing away from the substrate; in this embodiment, the oxide protection layer is deposited by a chemical vapor deposition process.

[0066] In another embodiment, an intermetallic dielectric layer is further provided between the metal diffusion protection layer and the oxide protection layer. The step S200: depositing a protection layer on one side of the substrate comprises the following steps:

[0067] Depositing a metal diffusion protection layer on one side of the substrate; in this embodiment, the metal diffusion protection layer is deposited by a chemical vapor deposition process, and the metal diffusion protection layer is, for example, a SiCN (silicon carbide nitride) film or a film of other materials;

[0068] An intermetallic dielectric layer is deposited on the side of the metal diffusion protection layer away from the substrate; in this embodiment, the intermetallic dielectric layer is deposited by a chemical vapor deposition process, and the intermetallic dielectric layer adopts a low dielectric constant material (Low-K material), and can further be an ultra-low dielectric constant material (ULK, Ultra Low-K); by providing the intermetallic dielectric layer, the RC delay performance of the semiconductor structure can be improved;

[0069] An oxide protection layer is deposited on a side of the intermetallic dielectric layer away from the metal diffusion protection layer. In this embodiment, the oxide protection layer is deposited by a chemical vapor deposition process.

[0070] In this embodiment, the step S400: etching the hard mask layer comprises the following steps:

[0071] forming a photoresist layer on a side of the hard mask layer away from the protective layer, the photoresist layer being used as a medium for pattern transfer;

[0072] The hard mask layer is etched using the photoresist layer as a mask; first, the desired pattern is projected onto the photoresist layer through photolithography. Then, the photoresist layer is exposed to light to cause a chemical reaction in the photosensitive agent, and then, the exposed photoresist layer is dissolved or retained through a development process, thereby forming a photoresist pattern corresponding to the desired pattern. Finally, the photoresist pattern is used as a mask to perform etching or deposition processes on the underlying hard mask layer to transfer the pattern to the underlying hard mask layer.

[0073] In this embodiment, forming a photoresist layer on a side of the hard mask layer away from the hard mask layer comprises the following steps:

[0074] A bottom anti-reflective coating (BARC) is formed on the side of the hard mask layer away from the protective layer. The main function of the bottom anti-reflective coating is to reduce reflection during photolithography, thereby improving the accuracy and quality of photolithography. By reducing reflected light, BARC can make the photolithography light more concentrated on the photoresist, thereby improving the resolution of photolithography. This is crucial for manufacturing semiconductor devices of smaller sizes; the reduction of reflected light can make the photolithography pattern clearer and sharper, reduce edge blur and jaggedness, and improve the quality and accuracy of the pattern;

[0075] A photoresist layer is formed on the side of the bottom anti-reflective coating layer facing away from the hard mask layer; a precise microstructure can be defined on the hard mask layer by exposing a specific pattern to the photoresist layer and then undergoing process steps such as development.

[0076] In this embodiment, after etching the hard mask layer using the photoresist layer as a mask, the following steps are also included:

[0077] The wet stripping process is used to remove the residual photoresist layer and bottom anti-reflective coating; wet stripping is an important process technology, which is mainly used to remove unwanted substances on the surface of specific materials. It is widely used in the fields of semiconductor manufacturing, electronic circuit production, etc. Its principle is to use a specific chemical solution to react with the substance to be removed to dissolve it or make it easy to separate. The advantage of wet stripping is that the degree of stripping can be controlled more accurately, and the damage to the underlying material is relatively small.

[0078] In this embodiment, after the step S500 of etching the through hole using the hard mask layer as a mask, the following steps are also included:

[0079] The polymer on the surface, bottom and sidewalls is removed by a chemical reagent; in this embodiment, the polymer on the surface, bottom and sidewalls is removed by a chemical reagent hydrogen fluoride (HF);

[0080] The internal water vapor and air are cleaned by purging and baking. In this embodiment, the internal water vapor and air are cleaned by nitrogen (N2) purging and baking to reduce the subsequent low-dielectric material (Low-K) material reaction.

[0081] The following combination Figures 2 to 7 The implementation process of the patterning method of the semiconductor structure of an embodiment is specifically introduced. The patterning method can be used for any metal layer process of metal wiring in a semiconductor device. Here, the process for the first copper metal layer is taken as an example. It is understandable that the various layer structures shown in the drawings and the following description are only examples, and are intended to more specifically illustrate the implementation method of the patterning method of the semiconductor structure in a specific application scenario, and are not intended to limit the scope of protection of this application.

[0082] like Figure 2 As shown, a substrate 10 is provided, and a contact hole (CT) 20 is formed in the substrate 10. Figure 3 As shown, on one side of the substrate 10, a SiCN film is sequentially deposited by chemical vapor deposition process as a metal diffusion protection layer 30, an intermetallic dielectric layer 40 and an oxide protection layer 50. The intermetallic dielectric layer 40 is made of a low dielectric constant material (Low-K material), and can further be an ultra-low dielectric constant material (ULK, Ultra Low-K); by providing the intermetallic dielectric layer 40, the RC delay performance of the semiconductor structure can be improved.

[0083] like Figure 4As shown, a carbon film is deposited on the side of the oxide protective layer 50 away from the intermetallic dielectric layer 40 by a spin coating process of deposition while rotating, forming a spin carbon (SOC) layer as a hard mask layer 60 for pattern transfer. By utilizing the good planarization characteristics and good gap filling ability of the spin carbon hard mask, the patterning of smaller contact holes can be achieved, and the problem of exposure and glue inversion of narrow process windows with a size of more than 65nm and the problem of difficult metal filling can be solved, thereby meeting the higher process node requirements of the chip back-end process in the semiconductor process. Carbon has good corrosion resistance, is insoluble and non-swelling in acids and alkalis, is resistant to high temperatures, has good electrical and thermal conductivity, good X-ray transmittance, and is very friendly to lithography. Compared with traditional chemical vapor deposition and physical vapor deposition (Physical Vapor Deposition, referred to as PVD), spin carbon has the characteristics of low cost, short process time, and high production capacity, which is conducive to improving the preparation efficiency of semiconductor devices. The high corrosion resistance and good gap filling properties of spin carbon can achieve fine patterning with a high aspect ratio (A / R). Spin-on carbon reacts more easily with oxygen (O2) plasma and can be repeatedly deposited (reworked) to solve problems caused by the hard mask during the process, thereby solving the defect that the TiN hard mask in the prior art cannot be easily reworked.

[0084] like Figure 5 As shown, a bottom anti-reflection coating 70 is formed on the side of the hard mask layer 60 away from the protective layer to reduce reflection during photolithography, thereby improving the accuracy and quality of photolithography and the quality and accuracy of patterns. A photoresist layer 80 is formed on the side of the bottom anti-reflection coating 70 away from the hard mask layer 60.

[0085] like Figure 6 As shown, the hard mask layer 60 is etched using the photoresist layer as a mask, and the etching stops at the oxide protection layer 50. The desired pattern is projected onto the photoresist layer 80 by photolithography. Then, the photoresist layer is exposed to light to cause a chemical reaction in the photosensitive agent, and then, the exposed photoresist layer is dissolved or retained by a development process, thereby forming a photoresist pattern corresponding to the desired pattern. Finally, using this photoresist pattern as a mask, the underlying hard mask layer 60 is etched or deposited to transfer the pattern to the underlying hard mask layer 60. Then, a wet stripping process is used to remove the remaining photoresist layer and the bottom anti-reflective coating.

[0086] like Figure 7As shown, the hard mask layer 60 is used as a mask for through-hole etching. Through-hole (via) etching refers to etching a small hole in a vertical direction, i.e., a through-hole, on a semiconductor material or other substrate by physical or chemical methods. Its main purpose is to establish an electrical connection channel between different material layers in order to achieve circuit interconnection. Then, the polymer on the surface, bottom and sidewall is removed by the chemical reagent hydrogen fluoride (HF), and the water vapor and air inside are cleaned by nitrogen (N2) purging and baking to reduce the subsequent low-dielectric material (Low-K) material reaction, thereby completing the patterning of the semiconductor structure.

[0087] The embodiment of the present application also provides a semiconductor structure obtained by using the patterning method of the semiconductor structure. The semiconductor structure can be applied to various semiconductor devices as a part of a semiconductor device. The semiconductor structure prepared by using the patterning method of the semiconductor structure can realize the patterning of smaller contact holes, solve the problem of exposure glue backflow in narrow process windows with a size of more than 65nm, the problem of metal filling difficulties, etc., meet the higher process node requirements of the chip back-end process in the semiconductor process, and effectively improve the performance of semiconductor devices.

[0088] In summary, by adopting the present application, a carbon film is deposited by a spin coating process to form a hard mask layer as a hard mask used in patterning, and the good planarization characteristics and good gap filling ability of the spin carbon hard mask are utilized to achieve patterning of smaller contact holes, solve the problem of exposure glue backflow in narrow process windows with a size higher than 65nm, the problem of difficult metal filling, etc., thereby meeting the higher process node requirements of chip back-end processes in semiconductor processes and effectively improving the performance of semiconductor devices. The patterning method can be used for any metal layer process of metal wiring in semiconductor devices, and is suitable for wide promotion and application.

[0089] The above content is a further detailed description of the present application in combination with specific preferred implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A method for patterning a semiconductor structure, characterized in that: include: providing a substrate; depositing a protective layer on one side of the substrate; Depositing a carbon film on a side of the protective layer away from the substrate by a spin coating process to form a hard mask layer; Etching the hard mask layer, and stopping the etching at the protective layer; The through hole is etched using the hard mask layer as a mask.

2. The method for patterning a semiconductor structure according to claim 1, wherein: Depositing a protective layer on one side of the substrate comprises the following steps: Depositing a metal diffusion protection layer on one side of the substrate; An oxide protection layer is deposited on a side of the metal diffusion protection layer facing away from the substrate.

3. The method for patterning a semiconductor structure according to claim 2, wherein: Depositing a protective layer on one side of the substrate comprises the following steps: Depositing a metal diffusion protection layer on one side of the substrate; Depositing an intermetallic dielectric layer on a side of the metal diffusion protection layer facing away from the substrate; An oxide protection layer is deposited on a side of the intermetallic dielectric layer away from the metal diffusion protection layer.

4. The method for patterning a semiconductor structure according to claim 3, characterized in that: The intermetallic dielectric layer is made of ultra-low dielectric constant material.

5. The method for patterning a semiconductor structure according to claim 1, wherein: Etching the hard mask layer comprises the following steps: forming a photoresist layer on a side of the hard mask layer away from the protective layer; The hard mask layer is etched using the photoresist layer as a mask.

6. The method for patterning a semiconductor structure according to claim 5, characterized in that: The step of forming a photoresist layer on a side of the hard mask layer away from the hard mask layer comprises the following steps: forming a bottom anti-reflective coating on a side of the hard mask layer facing away from the protective layer; A photoresist layer is formed on a side of the bottom anti-reflective coating layer away from the hard mask layer.

7. The method for patterning a semiconductor structure according to claim 6, wherein: After etching the hard mask layer using the photoresist layer as a mask, the following steps are also included: A wet stripping process is used to remove the remaining photoresist layer and bottom anti-reflective coating.

8. The method for patterning a semiconductor structure according to claim 1, wherein: After the through hole is etched using the hard mask layer as a mask, the following steps are also included: Removal of polymer from the surface, bottom and sidewalls by chemical agents; Clean the internal moisture and air by purging and baking.

9. The method for patterning a semiconductor structure according to claim 8, characterized in that: The polymer on the surface, bottom and sidewalls is removed by the chemical reagent hydrogen fluoride, and the water vapor and air inside are cleaned by nitrogen purging and baking.

10. A semiconductor structure, characterized in that: The method is obtained by using the patterning method of the semiconductor structure according to any one of claims 1 to 9.

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