Power semiconductor device packaging and sintering evaluation method and system

Abstract

The invention discloses a power semiconductor device packaging sintering evaluation method and system, and belongs to the technical field of semiconductor device packaging, and the method specifically comprises the steps: during sintering, recording data at preset intervals through an in-furnace temperature sensor and a time recorder to form a temperature-time curve; after sintering, preliminarily scanning the device through X rays, and marking the device to be unqualified if layering and large-size cavity defects exist; when no defect exists, determining starting and finishing temperatures and corresponding time points of the solid-phase reaction according to the curve, calculating effective sintering time, and judging whether the device is qualified or not according to a standard range set according to the device model and packaging process requirements; if the sintering time is not qualified, testing the electrical performance and the thermal performance of the device, setting a deviation threshold value, judging that the packaging sintering is qualified when the electrical performance and the thermal performance are normal and the sintering time meets the condition, otherwise, judging that the packaging sintering is not qualified; the method is based on multi-dimensional detection and analysis, the packaging and sintering quality of the power semiconductor device is comprehensively evaluated, and the reliability and performance of the device are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor device packaging, and in particular to a power semiconductor device packaging sintering evaluation method and system. Background Art

[0002] Power semiconductor devices play a vital role in modern power electronic systems. In their packaging process, the sintering process is a key link, which directly affects the electrical performance, reliability and thermal performance of the device. In the sintering process, sintering time is one of the key factors affecting the sintering quality. The appropriate sintering time can ensure a good connection between the chip and the substrate, and ensure the electrical performance, thermal performance and reliability of the device. However, there is currently a lack of accurate and efficient evaluation methods based on sintering time judgment, and it is difficult to determine whether the actual sintering time is within the optimal range. At the same time, it is difficult to accurately judge whether the sintering quality meets the requirements, which may lead to unstable device quality or failure of power semiconductor devices during use, reducing the service life and reliability of the product.

[0003] For example, a Chinese patent with the authorization announcement number CN114324427B discloses a power semiconductor device package sintering evaluation method, including: preparing a sample to be evaluated, wherein the sample to be evaluated includes a metal layer and a solder layer and a chip sequentially arranged on the metal layer; sintering the sample to be evaluated to obtain a sintered sample; performing a morphology analysis on the sintered sample according to a morphology analysis tool; performing a component analysis on the sintered sample after the morphology analysis according to a component analysis tool to obtain a component analysis result; and obtaining an evaluation result of the sample to be evaluated according to the component analysis result. The power semiconductor device package sintering evaluation method of this technical solution realizes the evaluation of the reliability of the sintering process from both microscopic and macroscopic aspects, and can ensure the reliability of the final sintering result.

[0004] The above existing technologies all have the following problems: they are mainly evaluated from the two aspects of microscopic morphology and macroscopic composition, and lack the monitoring and analysis of key parameters such as temperature and time during the sintering process; the morphology and composition analysis is carried out after the sintering is completed, which is a post-evaluation and lacks real-time and dynamic characteristics; the evaluation standards are not clear enough and lack comprehensive evaluation. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention proposes a power semiconductor device package sintering evaluation method and system. During sintering, data is recorded at preset intervals with the help of a temperature sensor and a time recorder in the furnace to form a temperature-time curve. After sintering, the device is first scanned by X-rays, and if there are stratification and large-sized void defects, it is marked as unqualified. If there are no defects, the starting and completion temperatures of the solid-phase reaction and the corresponding time points are determined according to the curve, and the effective sintering time is calculated. The qualification is determined in combination with the device model and the standard range set by the packaging process requirements. If the sintering time is unqualified, the device is tested for electrical and thermal properties, and a deviation threshold is set. When the electrical and thermal properties are normal and the sintering time meets the conditions, the package sintering is determined to be qualified, otherwise it is unqualified. This method is based on multi-dimensional detection and analysis, comprehensively evaluates the package sintering quality of power semiconductor devices, and improves the reliability and performance of the devices.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A power semiconductor device package sintering evaluation method, comprising:

[0008] Step S1: During the sintering process, the temperature value and the corresponding time point are recorded at preset time intervals by a temperature sensor and a time recorder installed in the device packaging sintering furnace to form temperature-time curve data;

[0009] Step S2: After sintering is completed, the device is preliminarily scanned using an X-ray detection device to check whether there are delamination and large-sized void defects. If there are no defects, the device is marked as sintered qualified;

[0010] Step S3: If there are defects, determine the solid phase reaction starting temperature and the sintering completion temperature from the collected temperature-time curve data, and determine the time point when the temperature reaches the solid phase reaction starting temperature and the sintering completion temperature according to the solid phase reaction starting temperature and the sintering completion temperature, and calculate the effective sintering time;

[0011] Step S4: according to the model of the power semiconductor device and the packaging process requirements, a standard effective sintering time range of the device is set, and the calculated effective sintering time is compared with the set standard effective sintering time range to determine whether the sintering time of the device is qualified;

[0012] Step S5: If the device sintering time is unqualified, the device is subjected to electrical and thermal performance tests, and a deviation threshold is set. If the electrical and thermal performance test results are both within the normal range, and the sintering time is within the qualified interval or exceeds but is less than the deviation threshold, the power semiconductor device is ultimately determined to be qualified for sintering. If the electrical or thermal performance test results are abnormal, and the sintering time is not within the qualified interval, the device is determined to be unqualified for sintering.

[0013] Specifically, the specific steps of step S3 include:

[0014] S3.1: Based on the temperature-time curve data collected during the sintering process, the temperature-time curve data corresponding to the defect-free device is screened out;

[0015] S3.2: Perform first-order difference calculation on the temperature-time curve data to obtain the temperature change between adjacent time points , where n represents the number of temperature-time data, and Represent the temperature values ​​of the i-th and i+1-th temperature data points respectively;

[0016] S3.3: Based on the first-order difference results and time interval Calculating the slope , generate a slope sequence of temperature change in each time interval;

[0017] S3.4: Set the slope change threshold and temperature stability threshold , starting from the heating stage of the temperature-time curve, find the slope The slope change threshold is exceeded for the first time point, and the corresponding temperature value is taken as the starting temperature of the solid phase reaction ;

[0018] S3.5: After the temperature reaches the peak value, analyze the temperature drop or fluctuation stage. When the temperature change amplitude at N consecutive time points is less than the temperature stability threshold When the temperature reaches a stable state, the corresponding temperature value is taken as the sintering completion temperature. .

[0019] Specifically, the specific steps of step S3 also include:

[0020] S3.6: Set the solid phase reaction starting temperature range to , starting from the heating stage of the temperature-time curve, traverse and check the temperature data points, the traversal method is:

[0021] like , then record the corresponding time point ;

[0022] like , then continue to check the next data point;

[0023] like , then trace back one data point, where and Respectively represent the minimum and maximum values ​​of the solid phase reaction starting temperature;

[0024] S3.7: Calculate the time point corresponding to the starting temperature of the solid phase reaction by traversal ,in, and Represent the temperature value and time of the i-1th temperature data point respectively.

[0025] Specifically, the specific steps of step S3 also include:

[0026] S3.8: If , then record the corresponding time point ;

[0027] like , then calculate the time point corresponding to the sintering completion temperature, the formula is: ;

[0028] S3.9: Based on the time point determined and , calculate the effective sintering time .

[0029] Specifically, the specific steps of step S5 include:

[0030] S5.1: Connect the device under test to the semiconductor parameter tester and set the test current to ;

[0031] S5.2: Apply a forward bias voltage, measure the voltage drop across the device, calculate the on-resistance according to Ohm's law, and compare the measured on-resistance with the standard on-resistance range of the device model to determine whether it is within the normal range;

[0032] S5.3: Set the temperature change rate threshold , apply a power load P to the device. If the device temperature reaches a stable state, by monitoring the temperature change rate, if , it is considered stable and the chip surface temperature is recorded and the package case heat sink temperature , where r represents the temperature change rate monitored in real time.

[0033] Specifically, the specific steps of step S5 include:

[0034] S5.4: Based on Calculate the thermal resistance and compare the calculated thermal resistance with the standard thermal resistance range of the device model to determine whether it is normal;

[0035] S55: Set the deviation threshold of sintering time according to the device's accuracy requirements and process tolerance ;

[0036] If the on-resistance is within the standard on-resistance range, the thermal resistance is also within the standard thermal resistance range, and , then the power semiconductor device package sintering qualification is determined;

[0037] If the on-resistance is not within the standard on-resistance range, or the thermal resistance is not within the standard thermal resistance range, or the sintering time is not within the standard range, or , it is determined that the power semiconductor device package sintering is unqualified.

[0038] A power semiconductor device packaging sintering evaluation system, comprising: a data acquisition module, a data analysis module, a comparison module, and a test module;

[0039] The data acquisition module is used to collect temperature and time data in real time during the sintering process, as well as preliminary scanning test results after the sintering is completed;

[0040] The data analysis module is used to analyze the collected temperature-time curve data, determine the solid phase reaction starting temperature point and the sintering completion temperature point, and calculate the effective sintering time;

[0041] The comparison module is used to set a standard effective sintering time range according to the model of the power semiconductor device and the packaging process requirements, and compare the calculated effective sintering time with the standard;

[0042] The test module is used to test the electrical and thermal properties of the device when the sintering time is unqualified, and to make a comprehensive judgment based on the test results and the deviation threshold.

[0043] Specifically, the data analysis module includes: a temperature curve analysis unit and a time calculation unit;

[0044] The temperature curve analysis unit is used to analyze the temperature-time curve data to determine the solid phase reaction starting temperature and the sintering completion temperature;

[0045] The time calculation unit is used to calculate the time when the temperature reaches the key temperature points determined by the temperature curve analysis unit to obtain the effective sintering time.

[0046] Specifically, the comparison module includes: a standard setting unit and a comparison determination unit;

[0047] The standard setting unit is used to set a standard effective sintering time range according to the device model and packaging process requirements;

[0048] The comparison and judgment unit is used to compare the calculated effective sintering time with the standard effective sintering time range to determine whether the sintering time is qualified.

[0049] An electronic device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of a power semiconductor device package sintering evaluation method are implemented.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] 1. The present invention proposes a power semiconductor device package sintering evaluation method. By real-time monitoring and recording of the temperature-time curve data during the sintering process, and using X-ray detection equipment to perform a preliminary scan of the device, the process can timely detect and mark devices with defects such as delamination and large-sized voids, thereby effectively avoiding further processing and use of unqualified devices and improving production efficiency and product quality.

[0052] 2. The present invention proposes a power semiconductor device package sintering evaluation method, which can more accurately evaluate the sintering quality of the device by comparing the calculated effective sintering time with the standard effective sintering time range, and combining the electrical and thermal performance test results and the deviation threshold for comprehensive judgment, thereby not only improving the accuracy of the judgment, but also further enhancing the reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A schematic diagram of a power semiconductor device packaging sintering evaluation method according to the present invention;

[0054] Figure 2 This is a principle flow chart of a power semiconductor device packaging sintering evaluation method of the present invention;

[0055] Figure 3 This is an architecture diagram of a power semiconductor device packaging sintering evaluation system of the present invention. DETAILED DESCRIPTION

[0056] Example 1

[0057] See also Figure 1 and Figure 2 , an embodiment of the present invention provides: a power semiconductor device package sintering evaluation method, comprising the following steps:

[0058] Step S1: During the sintering process, the temperature value and the corresponding time point are recorded at preset time intervals by a temperature sensor and a time recorder installed in the device packaging sintering furnace to form temperature-time curve data;

[0059] Among them, the temperature-time curve data can be expressed as , Indicates at a point in time The temperature value recorded at the time.

[0060] Furthermore, the specific steps of step S1 include:

[0061] (1) Clearly identify the installation location:

[0062] According to the measurement requirements, select the core environment point to install the temperature sensor to avoid the direct influence of strong electromagnetic interference sources and heat sources to ensure the measurement accuracy. At the same time, consider the sensor protection level to ensure that the installation location meets the safety requirements;

[0063] (2) Prepare installation tools and materials:

[0064] Including screwdrivers, wrenches, sealing washers, fixing screws and necessary mounting brackets. Check that the sensor has no damage on the outside, the cables are intact, and ensure that all parts are complete;

[0065] (3) Perform a pre-installation inspection:

[0066] Confirm that the sensor model matches the required measurement range, check whether the power supply voltage meets the requirements, and confirm whether the communication protocol between the sensor and the receiving device is consistent;

[0067] (4) Perform installation operations:

[0068] According to the sensor type, such as thermocouple and thermal resistor, choose the threaded connection installation method, use tools to fix the sensor in the predetermined position, and ensure that the tightening torque is appropriate. At the same time, pay attention to the direction and fixation of the cable to avoid mechanical damage and signal interference;

[0069] (5) Connecting time recorder:

[0070] Connect the time recorder to the temperature sensor to ensure that the time points can be accurately recorded, and set the preset time intervals to record the temperature values ​​on time;

[0071] (6) Start recording:

[0072] Start the sintering furnace and start the sintering process. At the same time, the temperature sensor and the time recorder start working to record the temperature value and the corresponding time point at a preset time interval. For example, the time recorder sends a signal to the temperature sensor every second, and the temperature sensor immediately measures the temperature in the current sintering furnace. The measured temperature value and the corresponding time point are packaged into a data recording unit. This unit can be a data structure containing two fields, time and temperature, such as an array [time value, temperature value];

[0073] (7) Stop data recording:

[0074] When the sintering process is finished and the temperature of the sintering furnace drops to a safe temperature, such as below 100°C, the data recording function of the temperature sensor and the time recorder is stopped.

[0075] Step S2: After sintering is completed, the device is preliminarily scanned using an X-ray detection device to check whether there are delamination and large-sized void defects. If there are no defects, the device is marked as sintered qualified;

[0076] Furthermore, the specific steps of step S2 include:

[0077] (1) Select X-ray detection equipment with appropriate performance and resolution to ensure that it meets the detection requirements, and calibrate and maintain the X-ray detection equipment to ensure the accuracy and reliability of the equipment. At the same time, check whether the power supply, interface, sensor and other components of the equipment are intact to ensure that the equipment can work normally;

[0078] (2) Properly place the sintered device in the inspection area of ​​the X-ray inspection equipment to ensure the stability of the device;

[0079] (3) According to the type and size of the device to be inspected, set the detection parameters of the X-ray inspection equipment, including the intensity of the X-ray source, detection angle, and scanning speed;

[0080] (4) Start the X-ray inspection equipment and begin scanning the device to be inspected. The detector receives the X-rays that pass through the device and converts them into electrical signals. The image processing system processes the electrical signals to generate an image of the inside of the device.

[0081] (5) The operator analyzes the quality and performance of the device based on the generated images, checks whether there are defects such as delamination and large-sized voids in the images, and records and classifies the defects found for subsequent processing;

[0082] (6) Evaluate the sintering quality of the device based on the analysis results. If the device has defects that affect performance, the device is marked as sintering failure, and the unqualified devices are recorded and appropriate treatment measures are taken, such as rework, scrapping, etc. If the device does not have defects that affect performance, the process ends.

[0083] Step S3: If there are defects, determine the solid phase reaction starting temperature and the sintering completion temperature from the collected temperature-time curve data, and determine the time point when the temperature reaches the solid phase reaction starting temperature and the sintering completion temperature according to the solid phase reaction starting temperature and the sintering completion temperature, and calculate the effective sintering time;

[0084] Step S4: according to the model of the power semiconductor device and the packaging process requirements, a standard effective sintering time range of the device is set, and the calculated effective sintering time is compared with the set standard effective sintering time range to determine whether the sintering time of the device is qualified;

[0085] Furthermore, the specific steps of step S4 include:

[0086] (1) Obtain the model of the power semiconductor device from the product specification or technical documentation, and find the corresponding packaging process requirements based on the model, including sintering temperature, sintering atmosphere, and sintering pressure parameters;

[0087] (2) Setting a standard effective sintering time range for a specific type of power semiconductor device based on packaging process requirements and industry experience;

[0088] (3) obtaining the calculated effective sintering time in step S2, and comparing the calculated actual effective sintering time with the set standard effective sintering time range;

[0089] (4) If the actual sintering time falls within the standard range, it is judged as qualified; otherwise, it is judged as unqualified.

[0090] Step S5: If the device sintering time is unqualified, the device is subjected to electrical and thermal performance tests, and a deviation threshold is set. If the electrical and thermal performance test results are both within the normal range, and the sintering time is within the qualified interval or exceeds but is less than the deviation threshold, the power semiconductor device is ultimately determined to be qualified for sintering. If the electrical or thermal performance test results are abnormal, and the sintering time is not within the qualified interval, the device is determined to be unqualified for sintering.

[0091] The specific steps of step S3 include:

[0092] S3.1: Based on the temperature-time curve data collected during the sintering process, the temperature-time data corresponding to the defect-free device is screened out;

[0093] Furthermore, the specific steps of S3.1 include:

[0094] (1) Collect temperature-time curve data from sensors in the sintering equipment, usually including timestamps and corresponding temperature values;

[0095] (2) Clean the collected data to remove outliers, missing values, or noise data;

[0096] (3) Extract key features from the temperature-time curve, such as the rate of temperature change and the range of temperature fluctuation;

[0097] (4) Analyzing the extracted features using a support vector machine method to detect whether there are defects. The support vector machine method is a prior art in the art and is not an inventive solution of the present application, and is not described in detail herein.

[0098] (5) Based on the results of defect detection, filter out the temperature-time data corresponding to defect-free devices and save these data.

[0099] S3.2: Perform first-order difference calculation on the temperature-time curve data to obtain the temperature change between adjacent time points , where n represents the number of temperature-time data, and Represent the temperature values ​​of the i-th and i+1-th temperature data points respectively;

[0100] S3.3: Based on the first-order difference results and time interval Calculating the slope , generate a slope sequence of temperature change in each time interval;

[0101] S3.4: Set the slope change threshold and temperature stability threshold , starting from the heating stage of the temperature-time curve, find the slope The slope change threshold is exceeded for the first time point, and the corresponding temperature value is taken as the starting temperature of the solid phase reaction ;

[0102] S3.5: After the temperature reaches the peak value, analyze the temperature drop or fluctuation stage. When the temperature change amplitude at N consecutive time points is less than the temperature stability threshold When the temperature reaches a stable state, the corresponding temperature value is taken as the sintering completion temperature. ;

[0103] S3.6: Set the solid phase reaction starting temperature range to , starting from the heating stage of the temperature-time curve, traverse and check the temperature data points, the traversal method is:

[0104] like , then record the corresponding time point ;

[0105] like , then continue to check the next data point;

[0106] like , then trace back one data point, where and Respectively represent the minimum and maximum values ​​of the solid phase reaction starting temperature;

[0107] S3.7: Calculate the time point corresponding to the starting temperature of the solid phase reaction by traversal ,in, and Respectively represent the temperature value and time of the i-1th temperature data point;

[0108] S3.8: If , then record the corresponding time point ;

[0109] like , then calculate the time point corresponding to the sintering completion temperature, the formula is: ;

[0110] S3.9: Based on the time point determined and , calculate the effective sintering time .

[0111] Specifically, the specific steps of step S5 include:

[0112] S5.1: Connect the device under test to the semiconductor parameter tester and set the test current to ;

[0113] S5.2: applying a forward bias voltage, measuring the voltage drop across the device, calculating the on-resistance according to Ohm's law, and comparing the measured on-resistance with the standard on-resistance range of the device of this model to determine whether it is within a normal range, wherein the Ohm's law calculation formula is a prior art content in this field, is not an inventive solution of the present application, and is not described in detail here;

[0114] S5.3: Set the temperature change rate threshold , apply a power load P to the device. If the device temperature reaches a stable state, by monitoring the temperature change rate, if , it is considered stable and the chip surface temperature is recorded and the package case heat sink temperature , where r represents the temperature change rate monitored in real time;

[0115] S5.4: Based on Calculate the thermal resistance and compare the calculated thermal resistance with the standard thermal resistance range of the device model to determine whether it is normal;

[0116] S55: Set the deviation threshold of sintering time according to the device's accuracy requirements and process tolerance ;

[0117] If the on-resistance is within the standard on-resistance range, the thermal resistance is also within the standard thermal resistance range, and , then the power semiconductor device package sintering qualification is determined;

[0118] If the on-resistance is not within the standard on-resistance range, or the thermal resistance is not within the standard thermal resistance range, or the sintering time is not within the standard range, or , it is determined that the power semiconductor device package sintering is unqualified.

[0119] Example 2

[0120] See also Figure 3 Another embodiment provided by the present invention is a power semiconductor device package sintering evaluation system, comprising:

[0121] Data acquisition module, data analysis module, comparison module, and test module;

[0122] Data acquisition module, used to collect temperature and time data in real time during the sintering process, as well as preliminary scanning test results after sintering is completed;

[0123] The data analysis module is used to analyze the collected temperature-time curve data, determine the solid phase reaction starting temperature point and the sintering completion temperature point, and calculate the effective sintering time;

[0124] A comparison module is used to set a standard effective sintering time range according to the model of the power semiconductor device and the packaging process requirements, and compare the calculated effective sintering time with the standard;

[0125] The test module is used to test the electrical and thermal properties of the device when the sintering time is unqualified, and make a comprehensive judgment based on the test results and the deviation threshold.

[0126] The data acquisition module includes: a recording unit and a scanning detection unit;

[0127] A recording unit, which is used to install a high-precision temperature sensor and a time recorder in the sintering furnace to record the temperature value and the corresponding time point at a preset time interval;

[0128] The scanning inspection unit is used to use X-ray inspection equipment to perform preliminary scanning on the device after sintering to check for defects such as delamination and large-sized voids.

[0129] The data analysis module includes: a temperature curve analysis unit and a time calculation unit;

[0130] Temperature curve analysis unit, used to analyze temperature-time curve data and determine the solid phase reaction starting temperature and sintering completion temperature;

[0131] The time calculation unit is used to calculate the time when the temperature reaches the key temperature points determined by the temperature curve analysis unit, and then obtain the effective sintering time.

[0132] The comparison module includes: a standard setting unit and a comparison judgment unit;

[0133] The standard setting unit is used to set the standard effective sintering time range according to the device model and packaging process requirements;

[0134] The comparison and judgment unit is used to compare the calculated effective sintering time with the standard effective sintering time range to judge whether the sintering time is qualified.

[0135] The test module includes: performance test unit and comprehensive judgment unit;

[0136] Performance testing unit, used to test the electrical and thermal performance of the device when the sintering time fails to meet the requirements;

[0137] The comprehensive judgment unit is used to make a comprehensive judgment based on the performance test results, sintering time and deviation threshold to determine whether the device packaging sintering is qualified.

[0138] Example 3

[0139] An electronic device includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of a power semiconductor device packaging sintering evaluation method are implemented. For details, please refer to the above method embodiment, which will not be repeated here.

[0140] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0141] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0142] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in the field may also change, modify, replace and modify the above-mentioned embodiments without departing from the purpose and scope of protection of the present invention, and all of these are within the protection of the present invention.

Claims

1. A method for evaluating sintering of power semiconductor device packaging, characterized in that: include: Step S1: During the sintering process, the temperature value and the corresponding time point are recorded at preset time intervals by a temperature sensor and a time recorder installed in the device packaging sintering furnace to form temperature-time curve data; Step S2: After sintering is completed, the device is preliminarily scanned using an X-ray detection device to check whether there are delamination and large-sized void defects. If there are no defects, the device is marked as sintered qualified; Step S3: If there are defects, determine the solid phase reaction starting temperature and the sintering completion temperature from the collected temperature-time curve data, and determine the time point when the temperature reaches the solid phase reaction starting temperature and the sintering completion temperature according to the solid phase reaction starting temperature and the sintering completion temperature, and calculate the effective sintering time; Step S4: according to the model of the power semiconductor device and the packaging process requirements, a standard effective sintering time range of the device is set, and the calculated effective sintering time is compared with the set standard effective sintering time range to determine whether the sintering time of the device is qualified; Step S5: If the device sintering time is unqualified, the device is subjected to electrical and thermal performance tests, and a deviation threshold is set. If the electrical and thermal performance test results are both within the normal range, and the sintering time is within the qualified interval or exceeds but is less than the deviation threshold, the power semiconductor device is ultimately determined to be qualified for sintering. If the electrical or thermal performance test results are abnormal, and the sintering time is not within the qualified interval, the device is determined to be unqualified for sintering.

2. A power semiconductor device package sintering evaluation method as claimed in claim 1, characterized in that: The specific steps of step S3 include: S3.1: Based on the temperature-time curve data collected during the sintering process, the temperature-time curve data corresponding to the defect-free device is screened out; S3.2: Perform first-order difference calculation on the temperature-time curve data to obtain the temperature change between adjacent time points , where n represents the number of temperature-time data, and Represent the temperature values ​​of the i-th and i+1-th temperature data points respectively; S3.3: Based on the first-order difference results and time interval Calculating the slope , generate a slope sequence of temperature change in each time interval; S3.4: Set the slope change threshold and temperature stability threshold , starting from the heating stage of the temperature-time curve, find the slope The slope change threshold is exceeded for the first time The corresponding temperature value is taken as the starting temperature of the solid phase reaction ; S3.5: After the temperature reaches the peak value, analyze the temperature drop or fluctuation stage. When the temperature change amplitude at N consecutive time points is less than the temperature stability threshold When the temperature reaches a stable state, the corresponding temperature value is taken as the sintering completion temperature. .

3. A power semiconductor device package sintering evaluation method as claimed in claim 2, characterized in that: The specific steps of step S3 also include: S3.6: Set the solid phase reaction starting temperature range to , starting from the heating stage of the temperature-time curve, traverse and check the temperature data points, the traversal method is: like , then record the corresponding time point ; like , then continue to check the next data point; like , then trace back one data point, where and Respectively represent the minimum and maximum values ​​of the solid phase reaction starting temperature; S3.7: Calculate the time point corresponding to the starting temperature of the solid phase reaction by traversal ,in, and Represent the temperature value and time of the i-1th temperature data point respectively.

4. A power semiconductor device package sintering evaluation method as claimed in claim 3, characterized in that: The specific steps of step S3 also include: S3.8: If , then record the corresponding time point ; like , then calculate the time point corresponding to the sintering completion temperature, the formula is: ; S3.9: Based on the time point determined and , calculate the effective sintering time .

5. A power semiconductor device package sintering evaluation method as claimed in claim 4, characterized in that: The specific steps of step S5 include: S5.1: Connect the device under test to the semiconductor parameter tester and set the test current to ; S5.2: Apply a forward bias voltage, measure the voltage drop across the device, calculate the on-resistance according to Ohm's law, and compare the measured on-resistance with the standard on-resistance range of the device model to determine whether it is within the normal range; S5.3: Set the temperature change rate threshold , apply a power load P to the device. If the device temperature reaches a stable state, by monitoring the temperature change rate, if , it is considered stable and the chip surface temperature is recorded and the package case heat sink temperature , where r represents the temperature change rate monitored in real time.

6. A power semiconductor device package sintering evaluation method as claimed in claim 5, characterized in that: The specific steps of step S5 include: S5.4: Based on Calculate the thermal resistance and compare the calculated thermal resistance with the standard thermal resistance range of the device model to determine whether it is normal; S55: Set the deviation threshold of sintering time according to the device's accuracy requirements and process tolerance ; If the on-resistance is within the standard on-resistance range, the thermal resistance is also within the standard thermal resistance range, and , then the power semiconductor device package sintering qualification is determined; If the on-resistance is not within the standard on-resistance range, or the thermal resistance is not within the standard thermal resistance range, or the sintering time is not within the standard range, or , it is determined that the power semiconductor device package sintering is unqualified.

7. A power semiconductor device package sintering evaluation system, which is used to implement a power semiconductor device package sintering evaluation method according to any one of claims 1 to 6, characterized in that: include: Data acquisition module, data analysis module, comparison module, and test module; The data acquisition module is used to collect temperature and time data in real time during the sintering process, as well as preliminary scanning test results after the sintering is completed; The data analysis module is used to analyze the collected temperature-time curve data, determine the solid phase reaction starting temperature point and the sintering completion temperature point, and calculate the effective sintering time; The comparison module is used to set a standard effective sintering time range according to the model of the power semiconductor device and the packaging process requirements, and compare the calculated effective sintering time with the standard; The test module is used to test the electrical and thermal properties of the device when the sintering time is unqualified, and to make a comprehensive judgment based on the test results and the deviation threshold.

8. A power semiconductor device package sintering evaluation system as claimed in claim 7, characterized in that: The data analysis module includes: a temperature curve analysis unit and a time calculation unit; The temperature curve analysis unit is used to analyze the temperature-time curve data to determine the solid phase reaction starting temperature and the sintering completion temperature; The time calculation unit is used to calculate the time when the temperature reaches the key temperature points determined by the temperature curve analysis unit to obtain the effective sintering time.

9. A power semiconductor device package sintering evaluation system as claimed in claim 8, characterized in that: The comparison module includes: a standard setting unit and a comparison and determination unit; The standard setting unit is used to set a standard effective sintering time range according to the device model and packaging process requirements; The comparison and judgment unit is used to compare the calculated effective sintering time with the standard effective sintering time range to determine whether the sintering time is qualified.

10. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the power semiconductor device package sintering evaluation method according to any one of claims 1 to 6 are implemented.

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