Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and relates to the technical field of semiconductors. The forming method comprises the following steps: providing a substrate, wherein the substrate comprises an array region and a mark region; forming a laminated structure on the surface of the substrate, wherein the laminated structure comprises a first barrier layer and a first semiconductor layer in the direction away from the substrate; forming a second barrier layer on the surface of the laminated structure, wherein the second barrier layer comprises a nitrogen element and a silicon element; and etching the laminated structure to form a contact hole in the array region and an alignment mark in the mark region at the same time, the contact hole penetrating through the second barrier layer and the laminated structure and extending into the substrate to expose the active region in the substrate. According to the invention, the second barrier layer is formed in the alignment mark, and the second barrier layer comprises the nitrogen element and the silicon element, so that a film layer in the alignment mark is prevented from being damaged and the alignment precision of the alignment mark is prevented from being influenced when wet etching is carried out on the structure through the anti-corrosion effect of the second barrier layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, overlay error (OVL) refers to the alignment deviation or misalignment error between different layers during the multi-layer semiconductor manufacturing process. The measurement and control of OVL is very important to ensure the accuracy and reliability of multi-layer semiconductor manufacturing.

[0003] At present, in the semiconductor manufacturing process, in order to reduce the alignment deviation between different layers, alignment marks can be formed in the mark area while forming devices in the active area, and the alignment between different layers can be performed by comparing the alignment marks. However, due to process limitations, during the formation of different film layers, the film layer inside the alignment mark formed in the mark area will be lost, which reduces the alignment accuracy of the alignment mark and further reduces the yield of the device.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In view of this, a semiconductor structure and a method for forming the same are provided. The method for forming the semiconductor structure forms an alignment mark having a second barrier layer in a mark area. The second barrier layer has high corrosion resistance and can ensure the integrity of the film layer of the alignment mark, thereby ensuring the alignment of the alignment mark.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising:

[0008] Providing a substrate, the substrate comprising an array region and a marking region;

[0009] forming a stacked structure on the surface of the substrate, wherein the stacked structure includes a first barrier layer and a first semiconductor layer in a direction away from the substrate;

[0010] forming a second barrier layer on the surface of the stacked structure, wherein the second barrier layer includes nitrogen and silicon;

[0011] The stacked structure is etched to simultaneously form a contact hole in the array region and an alignment mark in the mark region, wherein the contact hole penetrates the second barrier layer and the stacked structure and extends into the interior of the substrate to expose the active region in the substrate.

[0012] In some embodiments of the present disclosure, based on the above solution, the bottom of the contact hole and the alignment mark has a damaged layer, and the damaged layer is removed. The method includes:

[0013] Conformally forming a protective layer on the surface of the second barrier layer, in the contact hole, and in the alignment mark;

[0014] removing a portion of the protective layer to expose the damaged layer and the surface of the second barrier layer;

[0015] The damaged layer is removed by wet etching.

[0016] In some embodiments of the present disclosure, based on the above solution, the method further includes:

[0017] A second semiconductor layer is filled in the contact hole and the alignment mark.

[0018] In some embodiments of the present disclosure, based on the above solution, the method further includes:

[0019] removing the remaining portion of the protective layer;

[0020] A second semiconductor layer is filled in the contact hole and the alignment mark.

[0021] In some embodiments of the present disclosure, based on the above solution, the active region is formed in the substrate, and the method includes:

[0022] A plurality of isolation structures distributed at intervals are formed on the substrate, and the orthographic projections of the plurality of isolation structures on the substrate are located in the array region to form the active region.

[0023] According to another aspect of the present disclosure, there is provided a semiconductor structure, the semiconductor structure comprising:

[0024] A substrate, the substrate comprising an array region and a marking region;

[0025] A stacked structure formed on the substrate, the stacked structure comprising a first barrier layer and a first semiconductor layer in a direction away from the substrate;

[0026] A second barrier layer formed on the surface of the stacked structure, wherein the second barrier layer includes nitrogen and silicon;

[0027] A contact hole and an alignment mark, wherein the contact hole penetrates the second barrier layer and the stacked structure and extends into the interior of the substrate to expose the active area in the substrate, wherein the orthographic projection of the contact hole on the substrate is located in the array area, and the orthographic projection of the alignment mark on the substrate is located in the mark area.

[0028] In some embodiments of the present disclosure, based on the above solution, the weight content of the nitrogen element in the second barrier layer is greater than or equal to 30%.

[0029] In some embodiments of the present disclosure, based on the aforementioned solution, the second barrier layer includes silicon oxynitride or silicon nitride.

[0030] In some embodiments of the present disclosure, based on the aforementioned solution, the semiconductor structure further includes a second semiconductor layer, and the second semiconductor layer is filled in the contact hole and the alignment mark.

[0031] In some embodiments of the present disclosure, based on the aforementioned solution, the semiconductor structure further includes a plurality of isolation structures, and the plurality of isolation structures are spaced apart and distributed on the substrate to form an active region in the substrate.

[0032] The present disclosure provides a method for forming a semiconductor structure, which forms a stacked structure on a substrate, forms a second barrier layer on the stacked structure, and etches the stacked structure to simultaneously form contact holes in an array area of ​​the substrate and alignment marks in a mark area, wherein the second barrier layer includes nitrogen and silicon elements. By improving the corrosion resistance of the second barrier layer, the integrity of the alignment mark can be ensured during a wet etching process, thereby avoiding the problem of decreased alignment accuracy caused by damage to a film layer within the alignment mark, thereby improving the yield of the device and reducing the manufacturing cost. In addition, this formation method reduces the contact resistance between the contact holes and the active area within the structure, thereby improving the functionality of the device.

[0033] The present disclosure provides a semiconductor structure, which includes a substrate, a stacked structure and a second barrier layer. The second barrier layer is formed on the surface of the stacked structure, and the second barrier layer includes nitrogen and silicon elements. By arranging the second barrier layer in the semiconductor structure, the second barrier layer has high corrosion resistance. In the semiconductor etching process, the alignment mark in the mark area can be prevented from being damaged. The structure is simple and has high alignment accuracy, which ensures the alignment of the alignment mark and the manufacturing cost of the device is low. In addition, the contact resistance between the contact hole and the active area in the structure is small, and the functionality of the device is good.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0036] Figure 1 The present invention is a flowchart of a method for forming a semiconductor structure in an exemplary embodiment of the present invention.

[0037] Figure 2 It is a schematic structural diagram of a substrate and a stacked structure in an exemplary embodiment of the present disclosure.

[0038] Figure 3 It is a schematic structural diagram of a second barrier layer in an exemplary embodiment of the present disclosure.

[0039] Figure 4 It is a schematic structural diagram of a contact hole and an alignment mark in an exemplary embodiment of the present disclosure.

[0040] Figure 5 It is a schematic structural diagram of a protective layer in an exemplary embodiment of the present disclosure.

[0041] Figure 6 It is a schematic diagram of the structure of a damaged layer in an exemplary embodiment of the present disclosure.

[0042] Figure 7 It is a schematic structural diagram of a semiconductor structure after removing a damaged layer in an exemplary embodiment of the present disclosure.

[0043] Figure 8 The present invention is a flowchart of removing a damaged layer in an exemplary embodiment of the present invention.

[0044] The reference numerals are described as follows:

[0045] 100, substrate; 200, stacked structure; 210, first barrier layer; 220, first semiconductor layer; 300, second barrier layer; 400, contact hole; 500, alignment mark; 610, protection layer; 620, barrier layer; 700, damage layer; A, array area; M, mark area; AA, active area. DETAILED DESCRIPTION

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0047] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0048] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0049] In semiconductor devices, the bit line (BL) is the main circuit line used to store and read data. In memories (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.) and logic circuits (such as flash memory, etc.), the bit line contact (BLC) is a hole structure used to connect the bit line with the electronic devices or circuit elements at the lower level. Through the bit line contact hole, the current can pass through the layer from the bit line to the lower electronic device or circuit element that needs to be connected.

[0050] In the related art, the process of forming a bit line contact hole includes: forming a stacked film layer on a substrate; forming a barrier layer on the stacked film layer; etching the stacked film layer so that the bit line contact hole is formed in the active area AA of the substrate. However, in the process of forming the bit line contact hole, the substrate will be exposed at the bottom of the bit line contact hole. Due to oxidation in the process, etc., an oxide layer or a damage layer will be formed on the exposed substrate. When the bit line is subsequently formed, this oxide layer or damage layer will increase the contact resistance between the bit line and the active area AA, thereby affecting the function of the entire device. In order to remove this oxide layer or damage layer, wet etching and other methods are usually used to remove the oxide layer or damage layer, but the chemical reagents used in wet etching will damage the alignment mark on the mark area M, affecting the interlayer alignment accuracy in the subsequent device process.

[0051] Based on this, the present disclosure provides a method for forming a semiconductor structure, such as Figure 1 As shown, the forming method includes: step S100 to step S400.

[0052] Wherein, step S100: providing a substrate 100, the substrate 100 comprising an array region A and a marking region M;

[0053] Step S200: forming a stacked structure 200 on the surface of the substrate 100, wherein the stacked structure 200 includes a first barrier layer 210 and a first semiconductor layer 220 in a direction away from the substrate 100;

[0054] Step S300: forming a second barrier layer 300 on the surface of the stacked structure 200, wherein the second barrier layer 300 includes nitrogen and silicon elements;

[0055] Step S400 : etching the stacked structure 200 to simultaneously form a contact hole 400 in the array area A and an alignment mark 500 in the mark area M, wherein the contact hole 400 penetrates the second barrier layer 300 and the stacked structure 200 and extends into the interior of the substrate 100 to expose the active area AA in the substrate 100 .

[0056] The present disclosure provides a method for forming a semiconductor structure, which forms a stacked structure 200 on a substrate 100, forms a second barrier layer 300 on the stacked structure 200, and etches the stacked structure 200 to simultaneously form a contact hole 400 in the array area A of the substrate 100 and an alignment mark 500 in the mark area M, wherein the second barrier layer 300 includes nitrogen and silicon elements. By providing the second barrier layer 300 in the structure and improving the corrosion resistance of the second barrier layer 300, the integrity of the alignment mark 500 can be ensured during the wet etching process, and the problem of decreased alignment accuracy caused by damage to the film layer in the alignment mark 500 is avoided, thereby improving the yield of the device and reducing the manufacturing cost. In addition, the contact resistance between the contact hole 400 and the active area AA in the structure is reduced by this formation method, thereby improving the functionality of the device.

[0057] The following will describe in detail the steps of the method for forming a semiconductor structure provided by the embodiment of the present disclosure in conjunction with the accompanying drawings:

[0058] In the embodiments provided in the present disclosure, Figure 2 As shown, in step S100, a substrate 100 is provided, and the substrate 100 includes an array region A and a marking region M.

[0059] Wherein, the substrate 100 may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (GeSi) substrate, SOI (Silicon On Insulator) or GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, for example, silicon carbide (SiC), indium phosphide (InP) or gallium arsenide (GaAs), cadmium telluride (CdTe), indium selenide (InSe), gallium nitride (GaN), indium gallium phosphide (InGaAs), etc. The cross section of the substrate 100 provided in the present disclosure may be a rectangle, a square, or other shapes such as a circle. The shape of the substrate 100 may be selected according to the actual design requirements of the device, and the present disclosure does not specifically limit it.

[0060] The substrate 100 may include an array region A and a marking region M. The array region A on the substrate 100 is the main part of the semiconductor device for realizing specific functions. It may be composed of transistors, capacitors, resistors and other electronic components for performing tasks such as calculation, data storage or signal processing. The structure and function of the array region A depend on the design objectives of the chip, and may be a processor core, a storage unit, a sensor interface, etc.

[0061] The marking area M on the substrate 100 may include a mark for identifying a semiconductor device or an area for providing an alignment mark 500 for a process. In a specific embodiment provided by the present disclosure, the marking area M may refer to a dicing path, wherein the dicing path is usually located at the edge of a wafer and forms an elongated channel along the surface of the wafer. When the semiconductor wafer completes various process steps, it will be cut into multiple independent chips. The function of the dicing path is to cut the wafer and divide it into individual chips.

[0062] The substrate 100 also includes an active area AA, wherein the formation of the active area AA in the substrate 100 includes: forming a plurality of isolation structures distributed at intervals on the substrate 100, wherein the orthographic projections of the plurality of isolation structures on the substrate 100 are located in the array area A, so as to form the active area AA. The isolation structure may be a shallow trench isolation structure (STI), and the method for forming the shallow trench isolation structure includes: etching a trench on the substrate 100, for example, etching a trench on the surface of the substrate 100 by chemical etching or physical etching; after etching the trench, the substrate 100 needs to be cleaned and planarized to remove residual impurities and surface unevenness; filling the trench with insulating material, for example, filling the trench with silicon oxide (SiO2) or silicon nitride (SiN) and other materials, so as to insulate and isolate the trenches; after filling the insulating material, planarization and polishing need to be performed to make the surface of the trench flush with the surface of the substrate 100. Of course, the above steps are only exemplary of the method for forming the isolation structure, and the deformation, combination and corresponding replacement of the above steps are all within the protection scope of the present disclosure.

[0063] In the embodiments provided in the present disclosure, Figure 2 As shown, in step S200 , a stacked structure 200 is formed on the surface of the substrate 100 , and the stacked structure 200 includes a first barrier layer 210 and a first semiconductor layer 220 in a direction away from the substrate 100 .

[0064] A stacked structure 200 is formed on the surface of the substrate 100, and the stacked structure 200 may include a first barrier layer 210 and a first semiconductor layer 220 arranged in a direction away from the substrate 100. The first barrier layer 210 may be a film layer made of materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbide (SiC) or silicon oxycarbide (SiOC). Of course, the first barrier layer 210 may also be made of other materials, which may have functions such as an insulating layer and a protective layer, which is not specifically limited in the present disclosure. The first barrier layer 210 may be formed by a process method such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0065] Among them, the first semiconductor layer 220 can be a polysilicon (Poly) layer, or other semiconductor film layers. The first semiconductor layer 220 can be selected according to the actual design requirements of the device, and the present disclosure does not make specific limitations. The first semiconductor layer 220 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) and other process methods.

[0066] In some embodiments, an oxide layer may be further included between the stacked structure 200 and the substrate 100, for example, a silicon oxide (SiO2) layer, and the substrate 100 and the stacked structure 200 may be isolated by the oxide layer. The oxide layer may be formed by direct deposition on the surface of the substrate 100, or the oxide layer and the isolation structure may be formed simultaneously when the isolation structure is formed on the substrate 100. In addition, in the present disclosure, in addition to the oxide layer, other film layers for forming a semiconductor structure may be further included between the stacked structure 200 and the substrate 100, which will not be described in detail herein.

[0067] In some embodiments, the stacked structure 200 may include a stacked first barrier layer 210 and a stacked first semiconductor layer 220, or may include a stacked plurality of first barrier layers 210 and a stacked plurality of first semiconductor layers 220, wherein the number of the first barrier layer 210 and the first semiconductor layer 220 may be selected according to the actual structure of the device, and the present disclosure does not specifically limit this. In the semiconductor structure provided in the present disclosure, the first barrier layer 210 and the first semiconductor layer 220 are both described as one layer.

[0068] In the embodiments provided in the present disclosure, Figure 3 As shown, in step S300 , a second barrier layer 300 is formed on the surface of the stacked structure 200 , and the second barrier layer 300 includes nitrogen and silicon.

[0069] After the first semiconductor layer 220 in the stacked structure 200 is formed, a second barrier layer 300 may be formed on the stacked structure 200, and the stacked structure 200 and the structure in the substrate 100 are protected by the second barrier layer 300. The second barrier layer 300 covers the surface of the first semiconductor layer 220, and the orthographic projection of the second barrier layer 300 on the substrate 100 is located in the array region A and the marking region M at the same time.

[0070] In order to improve the corrosion resistance of the second barrier layer 300 and reduce the damage of the second barrier layer 300 in the subsequent process, the second barrier layer 300 may include nitrogen and silicon, wherein the weight content of nitrogen in the second barrier layer 300 is greater than or equal to 30%, for example, the weight content of nitrogen in the second barrier layer 300 may be 30%, 40%, 50%, 60%, 70%, 80%, 90% or more, and the greater the proportion of nitrogen in the second barrier layer 300, the better the corrosion resistance of the second barrier layer 300. However, it should be noted that the second barrier layer 300 also needs to have other functions, therefore, the content of nitrogen in the second barrier layer 300 needs to comprehensively consider multiple factors, for example, insulation, hardness, anti-metal diffusion ability and other factors, that is, the specific content of nitrogen in the second barrier layer 300 can be adaptively adjusted according to the specific function and structure of the second barrier layer 300, and the present disclosure does not make specific limitations.

[0071] The second barrier layer 300 also includes silicon and other elements, such as oxygen, etc. In some embodiments, the second barrier layer 300 may include silicon oxynitride (SiON) or silicon nitride (SiN). For example, when the second barrier layer 300 is a film layer formed of silicon oxynitride (SiON), the weight content of nitrogen in the silicon oxynitride (SiON) film layer must be greater than or equal to 30%; or, when the second barrier layer 300 is a film layer formed of silicon nitride (SiN), the weight content of nitrogen in the silicon nitride (SiN) film layer must be greater than or equal to 30%.

[0072] It should be noted that, the weight content of nitrogen in the second barrier layer 300 given in the above embodiment is greater than or equal to 30%, but in some embodiments, when the weight content cannot be used to calibrate the content of nitrogen in the second barrier layer 300, other content indicators such as mass percentage, volume percentage or molar percentage can be used to calibrate the content of nitrogen in the second barrier layer 300. In other words, the above weight content can be converted into other calibration methods through adaptive changes to calibrate the content of nitrogen, all of which are within the scope of protection of the present disclosure.

[0073] The second barrier layer 300 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD). In the present disclosure, preferably, since the stress of the nitrogen-containing film layer is relatively large, atomic layer deposition (ALD) can be used, for example, plasma atomic layer deposition (Plasma-Assisted Atomic Layer Deposition, Plasma ALD) can be selected to form the second barrier layer 300 to reduce the stress of the second barrier layer 300.

[0074] In some embodiments, the second barrier layer 300 may be formed on the stacked structure 200 by a plasma-assisted atomic layer deposition (Plasma ALD) process at a temperature of 600° C. to 700° C. For example, the temperature for forming the second barrier layer 300 may be 600° C., 610° C., 620° C., 630° C., 640° C., 650° C., 660° C., 670° C., 6800° C., 690° C. or 700° C., and the specific temperature may be adaptively adjusted according to the manufacturing process requirements of the second barrier layer 300. The thickness of the second barrier layer 300 may be 20 nm to 40 nm, for example, 20 nm, 25 nm, 30 nm, 35 nm or 40 nm, and the thickness value may be selected according to actual requirements.

[0075] The second barrier layer 300 provided in the above embodiment of the present disclosure has strong corrosion resistance and conformality. In the subsequent process, for example, when using a wet etching process to remove the film layer, the second barrier layer 300 has good corrosion resistance and good resistance to acids (such as hydrofluoric acid) used in the wet etching process. Therefore, the second barrier layer 300 will not be damaged, thereby maintaining the integrity of the film layer.

[0076] In the embodiments provided in the present disclosure, Figure 4 As shown, in step S400, the stacked structure 200 is etched to simultaneously form a contact hole 400 in the array area A and an alignment mark 500 in the mark area M, wherein the contact hole 400 penetrates the second barrier layer 300 and the stacked structure 200 and extends into the interior of the substrate 100 to expose the active area AA in the substrate 100.

[0077] After forming the second barrier layer 300, the second barrier layer 300 and the stacked structure 200 are etched simultaneously to form a contact hole 400 in the array region A and an alignment mark 500 in the mark region M. Figures 4 to 7 As shown, the contact hole 400 penetrates the second barrier layer 300 and the stacked structure 200 and extends to the inside of the substrate 100 to expose the active area AA in the substrate 100. After the contact hole 400 and the alignment mark 500 are formed, due to process limitations, a damaged layer 700 is formed at the bottom of the contact hole 400 and the bottom of the alignment mark 500. For example, the damaged layer 700 can be an oxide layer formed by oxidation of the exposed substrate 100, or can be a damaged layer 700 formed in a plasma process. The damaged layer 700 is located at the bottom of the contact hole 400 and covers the surface of the substrate 100. When the bit line structure is subsequently manufactured, the damaged layer 700 can increase the contact resistance between the bit line and the active area AA, affecting the performance of the device. Therefore, the damaged layer 700 needs to be removed.

[0078] In some embodiments, Figure 8 As shown, the method for removing the damaged layer 700 includes: steps S501 to S503.

[0079] Wherein, step S501: conformally forming a protection layer 610 on the surface of the second barrier layer 300, in the contact hole 400 and in the alignment mark 500;

[0080] Step S502: removing a portion of the protective layer 610 to expose the surfaces of the damaged layer 700 and the second barrier layer 300;

[0081] Step S503: removing the damaged layer 700 by wet etching.

[0082] Among them, Figure 5As shown, a protective layer 610 is conformally formed on the surface of the second barrier layer 300, in the contact hole 400 and in the alignment mark 500, as shown in FIG. Figure 6 As shown, a portion of the protective layer 610 is removed to expose the surface of the damaged layer 700 and the second barrier layer 300. The protective layer 610 may be a polysilicon (Poly) layer, and the protective layer 610 is formed on the surface of the second barrier layer 300, the bottom and sidewalls in the contact hole 400, and the bottom and sidewalls of the alignment mark 500. The protective layer 610 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD).

[0083] The second barrier layer 300 located on the surface of the second barrier layer 300 and the second barrier layer 300 located at the bottom of the contact hole 400 and the bottom of the alignment mark 500 are removed by dry etching or wet etching, and the second barrier layer 300 located on the sidewalls of the contact hole 400 and the sidewalls of the alignment mark 500 is retained, so that the remaining second barrier layer 300 can protect the sidewalls of the contact hole 400 and the sidewalls of the alignment mark 500, and the damaged layer 700 located at the bottom of the contact hole 400 and the bottom of the alignment mark 500 is exposed.

[0084] like Figure 7 As shown, wet etching is used to remove the damaged layer 700. Since wet etching is a common surface processing technology used to selectively remove or change the shape of a specific area on a semiconductor material, wet etching generally uses a chemical solution (such as an acidic or alkaline solution) to etch the semiconductor material. For example, a hydrofluoric acid (HF) solution can be used to etch the damaged layer 700 to remove the damaged layer 700 and expose the active area AA of the substrate 100.

[0085] After removing the damaged layer 700, the method for forming the semiconductor structure also includes a method for forming a second semiconductor layer. In the first embodiment, the method for forming the second semiconductor layer includes: after removing the damaged layer 700, filling the second semiconductor layer in the contact hole 400 and the alignment mark 500 to form a final semiconductor structure. Or, in the second embodiment, the method for forming the second semiconductor layer may include: removing the remaining portion of the protective layer 610; filling the second semiconductor layer in the contact hole 400 and the alignment mark 500 to form a final semiconductor structure. Both of the above-mentioned two forming methods are applicable to the present disclosure, but in order to avoid the formation of voids in the second semiconductor layer during the deposition process and improve the formation quality of the second semiconductor layer, the second semiconductor layer is usually formed using the forming method in the first example.

[0086] The second semiconductor layer and the protective layer 610 may be made of the same material, for example, a polysilicon (Poly) layer. The second semiconductor layer protective layer 610 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD).

[0087] It should be noted that the methods and structures provided in the above embodiments of the present disclosure also include other methods and structures for forming bit line structures, which may be commonly used methods and structures in the art and will not be described in detail here, but it should be understood that other conventional formation steps and structures of the bit line structure are within the protection scope of the present disclosure.

[0088] The present disclosure provides a method for forming a semiconductor structure, which forms a stacked structure 200 on a substrate 100, forms a second barrier layer 300 on the stacked structure 200, and etches the stacked structure 200 to simultaneously form a contact hole 400 in the array area A of the substrate 100 and an alignment mark 500 in the mark area M, wherein the second barrier layer 300 includes nitrogen and silicon elements. By providing the second barrier layer 300 in the structure and improving the corrosion resistance of the second barrier layer 300, the integrity of the alignment mark 500 can be ensured during the wet etching process, and the problem of decreased alignment accuracy caused by damage to the film layer in the alignment mark 500 is avoided, thereby improving the yield of the device and reducing the manufacturing cost. In addition, the contact resistance between the contact hole 400 and the active area AA in the structure is reduced by this formation method, thereby improving the functionality of the device.

[0089] It should be noted that, although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0090] The present disclosure provides a semiconductor structure, such as Figure 7 As shown, the semiconductor structure includes: a substrate 100 , a stacked structure 200 , a second barrier layer 300 , a contact hole 400 and an alignment mark 500 .

[0091] The substrate 100 includes an array area A and a marking area M; a stacked structure 200 is formed on the substrate 100, and the stacked structure 200 includes a first barrier layer 210 and a first semiconductor layer 220 in a direction away from the substrate 100; a second barrier layer 300 is formed on the surface of the stacked structure 200, and the second barrier layer 300 includes nitrogen and silicon elements; a contact hole 400 passes through the second barrier layer 300 and the stacked structure 200 and extends to the inside of the substrate 100 to expose the active area AA in the substrate 100, wherein the orthographic projection of the contact hole 400 on the substrate 100 is located in the array area A, and the orthographic projection of the alignment mark 500 on the substrate 100 is located in the marking area M.

[0092] The present disclosure provides a semiconductor structure, which includes a substrate 100, a stacked structure 200 and a second barrier layer 300. The second barrier layer 300 is formed on the surface of the stacked structure 200, and the second barrier layer 300 includes nitrogen and silicon elements. By arranging the second barrier layer 300 in the semiconductor structure, the second barrier layer 300 has high corrosion resistance. In the semiconductor etching process, the alignment mark 500 in the mark area M can be prevented from being damaged. The structure is simple and has high alignment accuracy, which ensures the alignment of the alignment mark 500 and the manufacturing cost of the device is low. In addition, the contact resistance between the contact hole 400 and the active area AA in the structure is small, and the functionality of the device is good.

[0093] The following will describe in detail the various parts of the semiconductor structure provided by the embodiment of the present disclosure in conjunction with the accompanying drawings:

[0094] The substrate 100 includes an array region A and a marking region M. The stacked structure 200 is formed on the substrate 100, and the stacked structure 200 includes a first barrier layer 210 and a first semiconductor layer 220 in a direction away from the substrate 100. In the present disclosure, other film layers for forming a semiconductor structure may be included between the substrate 100 and the stacked structure 200, which are not listed here one by one. The type of the substrate 100 and the specific structure of the stacked structure 200 are as described in the above embodiment, and are not described in detail here.

[0095] The substrate 100 also includes a plurality of isolation structures, which are spaced apart on the substrate 100 to form an active area AA on the substrate 100. In a semiconductor device, the active area AA may be a region that carries current and performs functions, and is generally used to implement functions such as injection, transmission, and amplification of electrons or holes. In the embodiment provided in the present disclosure, the active area AA in the substrate 100 is isolated and formed by a plurality of isolation structures, for example, the isolation structure may be a shallow trench isolation structure.

[0096] The second barrier layer 300 is formed on the surface of the stacked structure 200, and the second barrier layer 300 includes nitrogen and silicon. In order to improve the corrosion resistance of the second barrier layer 300 and reduce the damage of the second barrier layer 300 in the subsequent process, the second barrier layer 300 may include nitrogen and silicon, wherein the weight content of nitrogen in the second barrier layer 300 is greater than or equal to 30%, for example, the weight content of nitrogen in the second barrier layer 300 may be 30%, 40%, 50%, 60%, 70%, 80%, 90% or more, and the greater the proportion of nitrogen in the second barrier layer 300, the better the corrosion resistance of the second barrier layer 300. However, it should be noted that the second barrier layer 300 also needs to have other functions. Therefore, the content of nitrogen in the second barrier layer 300 needs to take into account multiple factors, such as insulation, hardness, and anti-metal diffusion ability. That is, the specific content of nitrogen in the second barrier layer 300 can be adaptively adjusted according to the specific function and structure of the second barrier layer 300, and the present disclosure does not make specific limitations.

[0097] The second barrier layer 300 also includes silicon and other elements, such as oxygen, etc. In some embodiments, the second barrier layer 300 may include silicon oxynitride (SiON) or silicon nitride (SiN). For example, when the second barrier layer 300 is a film layer formed of silicon oxynitride (SiON), the weight content of nitrogen in the silicon oxynitride (SiON) film layer must be greater than or equal to 30%; or, when the second barrier layer 300 is a film layer formed of silicon nitride (SiN), the weight content of nitrogen in the silicon nitride (SiN) film layer must be greater than or equal to 30%.

[0098] It should be noted that, the weight content of nitrogen in the second barrier layer 300 given in the above embodiment is greater than or equal to 30%, but in some embodiments, when the weight content cannot be used to calibrate the content of nitrogen in the second barrier layer 300, other content indicators such as mass percentage, volume percentage or molar percentage can be used to calibrate the content of nitrogen in the second barrier layer 300. In other words, the above weight content can be converted into other calibration methods through adaptive changes to calibrate the content of nitrogen, all of which are within the scope of protection of the present disclosure.

[0099] The method for forming the second barrier layer 300 is the same as the method for forming the second barrier layer 300 shown in the above embodiment, and will not be described again here.

[0100] The contact hole 400 penetrates the second barrier layer 300 and the stacked structure 200 and extends to the inside of the substrate 100 to expose the active area AA in the substrate 100, wherein the orthographic projection of the contact hole 400 on the substrate 100 is located in the array area A, and the orthographic projection of the alignment mark 500 on the substrate 100 is located in the mark area M. The semiconductor structure further includes a second semiconductor layer, for example, a polysilicon (Poly) layer, and the second semiconductor layer fills the contact hole 400 and the alignment mark 500 to form a final semiconductor structure.

[0101] The specific formation methods of the various film layers and structures of the semiconductor structure provided by the present invention are described in the above-mentioned formation method part and will not be repeated here.

[0102] The present disclosure provides a semiconductor structure, which includes a substrate 100, a stacked structure 200 and a second barrier layer 300. The second barrier layer 300 is formed on the surface of the stacked structure 200, and the second barrier layer 300 includes nitrogen and silicon elements. By arranging the second barrier layer 300 in the semiconductor structure, the second barrier layer 300 has high corrosion resistance. In the semiconductor etching process, the alignment mark 500 in the mark area M can be prevented from being damaged. The structure is simple and has high alignment accuracy, which ensures the alignment of the alignment mark 500 and the manufacturing cost of the device is low. In addition, the contact resistance between the contact hole 400 and the active area AA in the structure is small, and the functionality of the device is good.

[0103] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an array region and a marking region; forming a stacked structure on the surface of the substrate, wherein the stacked structure includes a first barrier layer and a first semiconductor layer in a direction away from the substrate; forming a second barrier layer on the surface of the stacked structure, wherein the second barrier layer includes nitrogen and silicon; The stacked structure is etched to simultaneously form a contact hole in the array region and an alignment mark in the mark region, wherein the contact hole penetrates the second barrier layer and the stacked structure and extends into the interior of the substrate to expose the active region in the substrate.

2. The method for forming a semiconductor structure according to claim 1, wherein: The contact hole and the bottom of the alignment mark have a damaged layer, and the damaged layer is removed. The method includes: Conformally forming a protective layer on the surface of the second barrier layer, in the contact hole, and in the alignment mark; removing a portion of the protective layer to expose the damaged layer and the surface of the second barrier layer; The damaged layer is removed by wet etching.

3. The method for forming a semiconductor structure according to claim 2, wherein: The method further comprises: A second semiconductor layer is filled in the contact hole and the alignment mark.

4. The method for forming a semiconductor structure according to claim 2, wherein: The method further comprises: removing the remaining portion of the protective layer; A second semiconductor layer is filled in the contact hole and the alignment mark.

5. The method for forming a semiconductor structure according to claim 1, wherein: The active region is formed in the substrate, the method comprising: A plurality of isolation structures distributed at intervals are formed on the substrate, and the orthographic projections of the plurality of isolation structures on the substrate are located in the array region to form the active region.

6. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising an array region and a marking region; A stacked structure formed on the substrate, the stacked structure comprising a first barrier layer and a first semiconductor layer in a direction away from the substrate; A second barrier layer formed on the surface of the stacked structure, wherein the second barrier layer includes nitrogen and silicon; A contact hole and an alignment mark, wherein the contact hole penetrates the second barrier layer and the stacked structure and extends into the interior of the substrate to expose the active area in the substrate, wherein the orthographic projection of the contact hole on the substrate is located in the array area, and the orthographic projection of the alignment mark on the substrate is located in the mark area.

7. The semiconductor structure according to claim 6, characterized in that: The weight content of the nitrogen element in the second barrier layer is greater than or equal to 30%.

8. The semiconductor structure according to claim 6, characterized in that: The second barrier layer includes silicon oxynitride or silicon nitride.

9. The semiconductor structure according to claim 6, characterized in that: The semiconductor structure further includes a second semiconductor layer, and the second semiconductor layer is filled in the contact hole and the alignment mark.

10. The semiconductor structure according to claim 6, characterized in that: The semiconductor structure further includes a plurality of isolation structures, which are spaced apart and distributed on the substrate to form an active region in the substrate.

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