Power semiconductor device and manufacturing method thereof

Abstract

The invention provides a power semiconductor device and a manufacturing method thereof, and the manufacturing method comprises the steps: forming a first groove in a substrate of a cellular region, and forming a second groove in a substrate of a terminal region; forming a first dielectric layer to cover the inner walls of the first groove and the second groove; filling a first polycrystalline silicon layer in the first groove and the second groove; removing a part of height of the first polycrystalline silicon layer and a part of height of the first dielectric layer in the first groove, and forming an isolation layer on the residual first polycrystalline silicon layer in the first groove; forming a second dielectric layer on the side wall of the first groove; filling a second polysilicon layer in the first trench; forming a third dielectric layer on the top surface of the substrate, wherein the third dielectric layer covers the first groove and the second groove; etching the third dielectric layer to form a first contact hole which exposes the second polycrystalline silicon layer and the first polycrystalline silicon layer in the second groove; and etching the third dielectric layer and the substrate at the periphery of the first groove to form a second contact hole. According to the technical scheme, electrical failure can be avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power semiconductor device and a manufacturing method thereof. Background Art

[0002] As a power semiconductor device, shielded gate trench (SGT) MOS devices may encounter the following electrical failure risks caused by contact hole morphology during the development process, resulting in electrical failure problems such as gate-source leakage current failure (IGSS fail) during electrical testing:

[0003] 1) When a dry etching process is used to simultaneously etch the gate electrode in the trench and the contact hole at the corresponding position of the body region outside the trench, the etching rate of the gate electrode made of polysilicon is faster than the etching rate of the single crystal silicon in the area where the body region is located. As a result, when the contact hole at the corresponding position of the body region is etched to the desired position, the contact hole at the corresponding position of the gate electrode has already etched through the gate electrode, thereby increasing the contact resistance and generating leakage.

[0004] 2) The width of the contact hole at the corresponding position of the voltage-resistant ring in the terminal area is too large, which is prone to offset during etching, resulting in the width of the voltage-resistant ring between the contact hole and the side wall of the trench being too small, which in turn makes it difficult for the field plate to contact.

[0005] Therefore, how to avoid electrical failure is an urgent problem to be solved. Summary of the invention

[0006] An object of the present invention is to provide a power semiconductor device and a method for manufacturing the same, so as to avoid electrical failure.

[0007] To achieve the above object, the present invention provides a method for manufacturing a power semiconductor device, comprising:

[0008] Providing a substrate having a cellular region and a terminal region;

[0009] forming a first trench in the substrate of the cell region, and forming a second trench in the substrate of the terminal region;

[0010] forming a first dielectric layer to cover inner walls of the first trench and the second trench;

[0011] Filling a first polysilicon layer in the first trench and the second trench;

[0012] Removing a portion of the height of the first polysilicon layer and a portion of the height of the first dielectric layer in the first trench, and forming an isolation layer on the remaining first polysilicon layer in the first trench;

[0013] forming a second dielectric layer on the sidewall of the first trench, wherein the thickness of the second dielectric layer is less than the thickness of the first dielectric layer;

[0014] Filling a second polysilicon layer in the first trench;

[0015] forming a third dielectric layer on the top surface of the substrate, wherein the third dielectric layer covers the first trench and the second trench;

[0016] The third dielectric layer is etched to form a first contact hole exposing the second polysilicon layer and the first polysilicon layer in the second groove; and the third dielectric layer and the substrate outside the first groove are etched to form a second contact hole, wherein the depth of the second contact hole is greater than the depth of the first contact hole.

[0017] Optionally, a top surface of the second polysilicon layer does not exceed a top surface of the first polysilicon layer in the second trench.

[0018] Optionally, a height difference between a top surface of the second polysilicon layer and a top surface of the first polysilicon layer in the second trench is 0.02 μm-0.1 μm.

[0019] Optionally, a width of the first contact hole is 80% to 95% of a width of the second contact hole.

[0020] Optionally, after filling the second polysilicon layer in the first trench and before forming the third dielectric layer on the top surface of the substrate, the method for manufacturing the power semiconductor device further includes:

[0021] forming a body region in the substrate around the first trench and the second trench;

[0022] A source region is formed in a body region outside the first trench, and the second contact hole at least exposes the body region at the bottom surface of the source region.

[0023] Optionally, a width of the second groove is greater than a width of the first groove, and a depth of the second groove is greater than a depth of the first groove.

[0024] The present invention also provides a power semiconductor device, comprising:

[0025] A substrate having a cell region and a terminal region, wherein a first groove is formed in the substrate of the cell region, and a second groove is formed in the substrate of the terminal region;

[0026] A first dielectric layer formed on a partial height inner wall of the first trench and the entire inner wall of the second trench;

[0027] A first polysilicon layer is filled in the first trench and the second trench at a partial height, wherein a top surface of the first polysilicon layer in the second trench is higher than a top surface of the first polysilicon layer in the first trench;

[0028] an isolation layer formed on the first polysilicon layer in the first trench;

[0029] A second dielectric layer is formed on the sidewall of the remaining height of the first trench, and the thickness of the second dielectric layer is less than the thickness of the first dielectric layer;

[0030] A second polysilicon layer filled in the first trench;

[0031] A third dielectric layer is formed on the top surface of the substrate, and the third dielectric layer covers the first groove and the second groove;

[0032] A first contact hole and a second contact hole, wherein the first contact hole penetrates the third dielectric layer and exposes the second polysilicon layer and the first polysilicon layer in the second trench, and the second contact hole penetrates the third dielectric layer outside the first trench and enters the substrate, and the depth of the second contact hole is greater than the depth of the first contact hole.

[0033] Optionally, a top surface of the second polysilicon layer does not exceed a top surface of the first polysilicon layer in the second trench.

[0034] Optionally, a height difference between a top surface of the second polysilicon layer and a top surface of the first polysilicon layer in the second trench is 0.02 μm-0.1 μm.

[0035] Optionally, a width of the first contact hole is 80% to 95% of a width of the second contact hole.

[0036] Optionally, the power semiconductor device further includes:

[0037] a body region formed in the substrate around the first trench and the second trench;

[0038] A source region is formed in a body region outside the first trench, and the second contact hole at least exposes the body region at the bottom surface of the source region.

[0039] Optionally, a width of the second groove is greater than a width of the first groove, and a depth of the second groove is greater than a depth of the first groove.

[0040] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0041] 1. A method for manufacturing a power semiconductor device of the present invention comprises: providing a substrate, wherein the substrate has a cell region and a terminal region; forming a first trench in the substrate of the cell region, and forming a second trench in the substrate of the terminal region; forming a first dielectric layer to cover the inner walls of the first trench and the second trench; filling a first polysilicon layer in the first trench and the second trench; removing a portion of the height of the first polysilicon layer and a portion of the height of the first dielectric layer in the first trench, and forming an isolation layer on the remaining first polysilicon layer in the first trench; forming a second dielectric layer on the sidewall of the first trench, wherein the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; filling a second polysilicon layer in the first trench; forming a third dielectric layer on the top surface of the substrate, The third dielectric layer covers the first groove and the second groove; the third dielectric layer is etched to form a first contact hole exposing the second polysilicon layer and the first polysilicon layer in the second groove; and the third dielectric layer and the substrate outside the first groove are etched to form a second contact hole, the depth of the second contact hole is greater than the depth of the first contact hole, that is, the first contact hole and the second contact hole are formed in different etching processes, so that the second contact hole can reach the required depth while avoiding the first contact hole from penetrating the second polysilicon layer, that is, avoiding the second polysilicon layer from being etched through, thereby avoiding increasing the contact resistance and generating leakage, and further avoiding electrical failure problems such as gate-source leakage current failure during electrical testing.

[0042] 2. The power semiconductor device of the present invention comprises: a substrate having a cell region and a terminal region, wherein a first groove is formed in the substrate of the cell region, and a second groove is formed in the substrate of the terminal region; a first dielectric layer is formed on the inner wall of a part of the height of the first groove and the entire inner wall of the second groove; a first polysilicon layer is filled in the first groove and the second groove of a part of the height, and the top surface of the first polysilicon layer in the second groove is higher than the top surface of the first polysilicon layer in the first groove; an isolation layer is formed on the first polysilicon layer in the first groove; a second dielectric layer is formed on the sidewall of the remaining height of the first groove, and the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; a second polysilicon layer is filled in the first groove; a third dielectric layer is formed on the substrate The top surface of the substrate is provided with a third dielectric layer covering the first groove and the second groove; a first contact hole and a second contact hole, wherein the first contact hole penetrates the third dielectric layer and exposes the second polysilicon layer and the first polysilicon layer in the second groove, and the second contact hole penetrates the third dielectric layer outside the first groove and enters the substrate, and the depth of the second contact hole is greater than the depth of the first contact hole, that is, the first contact hole and the second contact hole are formed in different etching processes respectively, so that the second contact hole reaches the required depth while avoiding the first contact hole from penetrating the second polysilicon layer, that is, avoiding the second polysilicon layer from being etched through, thereby avoiding increasing the contact resistance and generating leakage, and further avoiding electrical failure problems such as gate-source leakage current failure during electrical testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a flow chart of a method for manufacturing a power semiconductor device according to an embodiment of the present invention;

[0044] Figure 2a to Figure 2m yes Figure 1 A schematic diagram of a device in a method for manufacturing a power semiconductor device is shown.

[0045] Among them, Figure 1 to Figure 2m The reference numerals are described as follows:

[0046] 10-substrate; 101-first groove; 102-second groove; 103-silicon oxide layer; 104-silicon nitride layer; 11-first dielectric layer; 12-first polysilicon layer; 121-first patterned photoresist layer; 122-first polysilicon material layer; 13-isolation layer; 131-second patterned photoresist layer; 132-isolation material layer; 14-second dielectric layer; 15-second polysilicon layer; 16-third dielectric layer; 171-first contact hole; 172-second contact hole; 181-body region; 182-source region; 19-contact plug. DETAILED DESCRIPTION

[0047] In order to make the purpose, advantages and features of the present invention more clear, the power semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0048] An embodiment of the present invention provides a method for manufacturing a power semiconductor device. Figure 1 , Figure 1 1 is a flow chart of a method for manufacturing a power semiconductor device according to an embodiment of the present invention, wherein the method for manufacturing a power semiconductor device comprises:

[0049] Step S1, providing a substrate, wherein the substrate has a cell region and a terminal region;

[0050] Step S2, forming a first trench in the substrate of the cell region, and forming a second trench in the substrate of the terminal region;

[0051] Step S3, forming a first dielectric layer to cover the inner walls of the first trench and the second trench;

[0052] Step S4, filling a first polysilicon layer in the first trench and the second trench;

[0053] Step S5, removing a portion of the height of the first polysilicon layer and a portion of the height of the first dielectric layer in the first trench, and forming an isolation layer on the remaining portion of the first polysilicon layer in the first trench;

[0054] Step S6, forming a second dielectric layer on the sidewall of the first trench, wherein the thickness of the second dielectric layer is less than the thickness of the first dielectric layer;

[0055] Step S7, filling the first trench with a second polysilicon layer;

[0056] Step S8, forming a third dielectric layer on the top surface of the substrate, and the third dielectric layer covers the first trench and the second trench;

[0057] Step S9, etching the third dielectric layer to form a first contact hole exposing the second polysilicon layer and the first polysilicon layer in the second groove; and etching the third dielectric layer and the substrate around the first groove to form a second contact hole, wherein the depth of the second contact hole is greater than the depth of the first contact hole.

[0058] See below Figure 2a to Figure 2m The manufacturing method of the power semiconductor device provided in this embodiment is described in more detail. Figure 2a to Figure 2m It is also a schematic diagram of a longitudinal cross-section of a power semiconductor device.

[0059] According to step S1 , a substrate 10 is provided, wherein the substrate 10 has a cell region A1 and a terminal region A2 .

[0060] The terminal area A2 surrounds a cell array composed of a plurality of cell areas A1.

[0061] The base 10 includes a substrate and an epitaxial layer formed on the substrate.

[0062] The substrate 10 may be made of any suitable material known to those skilled in the art, such as single crystal silicon, silicon germanium, silicon carbide, etc.

[0063] According to step S2, Figure 2a As shown, a first trench 101 is formed in the substrate 10 of the cell area A1, and a second trench 102 is formed in the substrate 10 of the terminal area A2.

[0064] The steps of forming the first trench 101 and the second trench 102 include: forming a patterned mask layer on the substrate 10 , and etching the substrate 10 using the patterned mask layer as a mask to form the first trench 101 and the second trench 102 .

[0065] The mask layer may be a single-layer structure or a structure of at least two layers, for example, Figure 2a The mask layer shown in the figure includes a silicon oxide layer 103 and a silicon nitride layer 104 sequentially covering the substrate 10. The silicon oxide layer 103 can be formed by a thermal oxidation process, and the silicon nitride layer 104 can be formed by a deposition process. The silicon oxide layer 103 and the silicon nitride layer 104 of the desired thickness can be obtained by adjusting the process parameters.

[0066] After forming the first trench 101 and the second trench 102, the mask layer on the substrate 10 around the first trench 101 and the second trench 102 may be retained, or the mask layer may be removed before subsequently forming the first dielectric layer 11. Figure 2b to Figure 2m Shown is an embodiment in which the mask layer is retained.

[0067] Preferably, the width of the second groove 102 is greater than the width of the first groove 101, and the depth of the second groove 102 is greater than the depth of the first groove 101, so that the pressure-resistant ring subsequently formed in the second groove 102 is wider and deeper, thereby improving the pressure-resistant performance of the power semiconductor device.

[0068] According to step S3, Figure 2b As shown, a first dielectric layer 11 is formed to cover the inner walls of the first trench 101 and the second trench 102 .

[0069] The first dielectric layer 11 may further extend to the substrate 10 outside the first trench 101 and the second trench 102 .

[0070] After forming the first trench 101 and the second trench 102, if the mask layer on the substrate 10 outside the first trench 101 and the second trench 102 is retained, the mask layer is still sandwiched between the first dielectric layer 11 on the top surface of the substrate 10 and the substrate 10; after forming the first trench 101 and the second trench 102, if the mask layer is removed, the bottom surface of the first dielectric layer 11 on the top surface of the substrate 10 directly contacts the top surface of the substrate 10.

[0071] The first dielectric layer 11 may be made of insulating materials such as silicon oxide or silicon oxynitride.

[0072] According to step S4, Figure 2c and Figure 2d As shown, the first polysilicon layer 12 is filled in the first trench 101 and the second trench 102 .

[0073] The step of forming the first polysilicon layer 12 may include: Figure 2c As shown, a first polysilicon material layer 122 is filled in the first trench 101 and the second trench 102, the first polysilicon material layer 122 fills the first trench 101 and the second trench 102 and buries the first dielectric layer 11 therein, and the first polysilicon material layer 122 is planarized by a chemical mechanical polishing process until the top surface of the first dielectric layer 11 on the top surface of the substrate 10 is exposed; then, as shown Figure 2d As shown, a portion of the first polysilicon material layer 122 is continuously removed until the top surface of the remaining first polysilicon material layer 122 is flush with the top surface of the substrate 10 , and the remaining first polysilicon material layer 122 serves as the first polysilicon layer 12 .

[0074] In other embodiments, the top surface of the first polysilicon layer 12 may be slightly higher or slightly lower than the top surface of the substrate 10 .

[0075] According to step S5, Figure 2e to Figure 2g As shown, a portion of the height of the first polysilicon layer 12 and a portion of the height of the first dielectric layer 11 in the first trench 101 are removed, and an isolation layer 13 is formed on the remaining first polysilicon layer 12 in the first trench 101 .

[0076] The steps may include: Figure 2eAs shown, a first patterned photoresist layer 121 is formed on the first dielectric layer 11 and the first polysilicon layer 12, the first patterned photoresist layer 121 exposes the cell area A1, and the first polysilicon layer 12 at a part of the height in the first trench 101 and the first dielectric layer 11 on the top surface of the substrate 10 of the cell area A1 are etched away using the first patterned photoresist layer 121 as a mask, at this time, the silicon nitride layer 104 can be used as an etching stop layer; then, the first patterned photoresist layer 121 is removed; then, as shown in FIG. Figure 2f As shown, an isolation material layer 132 is formed to fill the first trench 101, and the isolation material layer 132 also extends to cover the silicon nitride layer 104 of the cell area A1 and the first dielectric layer 11 and the first polysilicon layer 12 of the terminal area A2, and the isolation material layer 132 and the first dielectric layer 11 of the terminal area A2 are ground until the silicon nitride layer 104 is exposed, that is, the silicon nitride layer 104 is used as a grinding stop layer; then, as shown Figure 2g As shown, a second patterned photoresist layer 131 is formed, and the second patterned photoresist layer 131 exposes the cell area A1. The mask layer (i.e., the silicon nitride layer 104 and the silicon oxide layer 103) on the substrate 10 of the cell area A1 and a partial height of the first dielectric layer 11 and a partial height of the isolation material layer 132 in the first groove 101 are etched and removed using the second patterned photoresist layer 131 as a mask. The remaining isolation material layer 132 on the first polysilicon layer 12 in the first groove 101 serves as the isolation layer 13, and the isolation material layer 132 on the first polysilicon layer 12 in the second groove 102 can also serve as the isolation layer 13; then, the second patterned photoresist layer 131 is removed.

[0077] It should be noted that step S5 is not limited to Figure 2e to Figure 2g In the embodiment shown, for example, in the above steps, when the first polysilicon layer 12 of a portion of the height in the first groove 101 is etched away using the first patterned photoresist layer 121 as a mask, the first dielectric layer 11 of a portion of the height in the first groove 101 can also be etched away simultaneously. Then, when the structure in the first groove 101 is etched away using the second patterned photoresist layer 131 as a mask, only a portion of the height of the isolation material layer 132 needs to be etched away, so that the isolation layer 13 formed in the first groove 101 can extend from the first polysilicon layer 12 to the first dielectric layer 11.

[0078] The isolation layer 13 may be made of insulating materials such as silicon oxide or silicon oxynitride.

[0079] According to step S6, Figure 2hAs shown, a second dielectric layer 14 is formed on the sidewall of the first trench 101 , and the thickness of the second dielectric layer 14 is less than the thickness of the first dielectric layer 11 .

[0080] The second dielectric layer 14 may be formed by a thermal oxidation process.

[0081] The second dielectric layer 14 may further extend to the top surface of the substrate 10 outside the first trench 101 .

[0082] The second dielectric layer 14 may be made of insulating materials such as silicon oxide or silicon oxynitride.

[0083] According to step S7, Figure 2i As shown, the second polysilicon layer 15 is filled in the first trench 101 .

[0084] The step of forming the second polysilicon layer 15 may include: filling a second polysilicon material layer (not shown) in the first trench 101, the second polysilicon material layer filling the first trench 101 and extending to the second dielectric layer 14 and the silicon nitride layer 104 on the top surface of the substrate 10, the first dielectric layer 11 and the isolation layer 13 in the second trench 102, and etching the second polysilicon material layer until the remaining second polysilicon material layer in the first trench 101 reaches a desired thickness, and the remaining second polysilicon material layer serves as the second polysilicon layer 15. At this time, the silicon nitride layer 104 can be etched away, and the silicon oxide layer 103, the first dielectric layer 11 in the second trench 102, and the top of the isolation layer 13 are also partially removed, so that the top surface of the second dielectric layer 14 is flush with the top surface of the silicon oxide layer 103, the first dielectric layer 11 in the second trench 102, and the top surface of the isolation layer 13.

[0085] At this time, the remaining first polysilicon layer 12 in the first trench 101 is used to form a shielding electrode of the transistor unit, and the second polysilicon layer 15 in the first trench 101 is used to form a gate electrode of the transistor unit, and the gate electrode and the shielding electrode are isolated by the isolation layer 13; the first polysilicon layer 12 in the second trench 102 is used to form a voltage-resistant ring of the terminal structure.

[0086] Preferably, the top surface of the second polysilicon layer 15 does not exceed the top surface of the first polysilicon layer 12 in the second groove 102, so as to ensure that when the first contact hole 171 is subsequently etched to form the first contact hole 171, etching can be stopped when the first contact hole 171 just exposes the top surface of the second polysilicon layer 15, thereby preventing the top surface of the first polysilicon layer 12 in the second groove 102 from being too much lower than the top surface of the second polysilicon layer 15, resulting in the first contact hole 171 having penetrated the second polysilicon layer 15 when the first contact hole 171 just exposes the top surface of the first polysilicon layer 12 in the second groove 102 and etching is stopped, i.e., preventing the second polysilicon layer 15 from being etched through.

[0087] Further preferably, Figure 2i As shown, a height difference h1 between a top surface of the second polysilicon layer 15 and a top surface of the first polysilicon layer 12 in the second trench 102 is 0.02 μm-0.1 μm, i.e., a top surface of the second polysilicon layer 15 is 0.02 μm-0.1 μm lower than a top surface of the first polysilicon layer 12 in the second trench 102 .

[0088] In other embodiments, the top surface of the second polysilicon layer 15 may be higher than the top surface of the first polysilicon layer 12 in the second groove 102. In this case, the top surface of the second polysilicon layer 15 is preferably 0.02 μm-0.1 μm higher than the top surface of the first polysilicon layer 12 in the second groove 102, so that when the first contact hole 171 is subsequently etched to form the first contact hole 171, when the first contact hole 171 just exposes the first polysilicon layer 12 in the second groove 102 and etching stops, the first contact hole 171 will enter the second polysilicon layer 15 but will not penetrate the second polysilicon layer 15.

[0089] like Figure 2j As shown, after filling the second polysilicon layer 15 in the first trench 101 and before forming the third dielectric layer 16 on the top surface of the substrate 10, the method for manufacturing the power semiconductor device further includes:

[0090] forming a body region 181 in the substrate 10 around the first trench 101 of the cell region A1 and in the substrate 10 around the second trench 102 of the terminal region A2;

[0091] A source region 182 is formed in the body region 181 outside the first trench 101 of the cell region A1.

[0092] The substrate 10 and the source region 182 have the same doping type, and the source region 182 and the body region 181 have opposite doping types.

[0093] According to step S8, Figure 2k As shown, a third dielectric layer 16 is formed on the top surface of the substrate 10 , and the third dielectric layer 16 covers the first trench 101 and the second trench 102 .

[0094] exist Figure 2k In the illustrated embodiment, the third dielectric layer 16 covers the second polysilicon layer 15 , the second dielectric layer 14 , the silicon oxide layer 103 , and the first dielectric layer 11 and the isolation layer 13 in the second trench 102 .

[0095] The third dielectric layer 16 may be made of insulating materials such as silicon oxide or silicon oxynitride.

[0096] According to step S9, Figure 2k and Figure 2l As shown, the third dielectric layer 16 is etched to form a first contact hole 171 exposing the second polysilicon layer 15 and the first polysilicon layer 12 in the second groove 102; and the third dielectric layer 16 and the substrate 10 outside the first groove 101 are etched to form a second contact hole 172, and the depth of the second contact hole 172 is greater than the depth of the first contact hole 171.

[0097] like Figure 2l As shown, there is a height difference h2 between the bottom surface of the second contact hole 172 and the bottom surface of the first contact hole 171 , and the bottom surface of the second contact hole 172 is lower than the bottom surface of the first contact hole 171 .

[0098] The second contact hole 172 at least exposes the body region 181 at the bottom surface of the source region 182, that is, the second contact hole 172 can just penetrate the source region 182 and expose the body region 181, or, the second contact hole 172 can penetrate the source region 182 and enter the body region 181, so that the contact plug 19 subsequently formed in the second contact hole 172 is electrically connected to the body region 181.

[0099] The first contact hole 171 may be formed first, and then the second contact hole 172 may be formed; or the second contact hole 172 may be formed first, and then the first contact hole 171 may be formed.

[0100] Taking the first contact hole 171 as an example, and then forming the second contact hole 172, the steps of forming the first contact hole 171 and the second contact hole 172 include: Figure 2k, forming a third patterned photoresist layer (not shown) on the cell area A1 and the terminal area A2, the third patterned photoresist layer exposing the second polysilicon layer 15 and the third dielectric layer 16 above the first polysilicon layer 12 in the second groove 102, etching the third dielectric layer 16 using the third patterned photoresist layer as a mask to form a first contact hole 171, the first contact hole 171 on the second polysilicon layer 15 penetrates the third dielectric layer 16 and exposes the second polysilicon layer 15, and the first contact hole 171 on the first polysilicon layer 12 in the second groove 102 penetrates the third dielectric layer 16 and the isolation layer 13 and enters the first polysilicon layer 12; then, removing the third patterned photoresist layer; then, as Figure 2l As shown, a fourth patterned photoresist layer (not shown) is formed on the cell area A1 and the terminal area A2, the fourth patterned photoresist layer fills the first contact hole 171, the fourth patterned photoresist layer exposes the third dielectric layer 16 above the source area 182, and the third dielectric layer 16 is etched using the fourth patterned photoresist layer as a mask to form a second contact hole 172, the second contact hole 172 penetrates the third dielectric layer 16, the second dielectric layer 14 and the source area 182 and enters the body area 181; then, the fourth patterned photoresist layer is removed.

[0101] Since the first contact hole 171 and the second contact hole 172 are formed respectively in different etching processes, the depth of the second contact hole 172 can be greater than the depth of the first contact hole 171, so that the second contact hole 172 can reach the required depth while avoiding the first contact hole 171 from penetrating the second polysilicon layer 15, that is, avoiding the second polysilicon layer 15 from being etched through, thereby avoiding increasing the contact resistance and generating leakage, and further avoiding electrical failure problems such as gate-source leakage current failure during electrical testing.

[0102] Preferably, the width of the first contact hole 171 is 80% to 95% of the width of the second contact hole 172, that is, by modifying the layout, the width of the first contact hole 171 is 5% to 20% smaller than the width of the second contact hole 172, thereby preventing the first contact hole 171 from being too large and causing easy deviation during etching, thereby preventing the width of the pressure-resistant ring between the first contact hole 171 and the side wall of the second groove 102 from being too small, thereby avoiding difficulty in field plate contact.

[0103] like Figure 2m As shown, the method for manufacturing the power semiconductor device further includes: forming contact plugs 19 in the first contact hole 171 and the second contact hole 172 .

[0104] In summary, the present invention provides a method for manufacturing a power semiconductor device, comprising: providing a substrate, the substrate having a cell region and a terminal region; forming a first trench in the substrate of the cell region, and forming a second trench in the substrate of the terminal region; forming a first dielectric layer to cover the inner walls of the first trench and the second trench; filling a first polysilicon layer in the first trench and the second trench; removing a portion of the height of the first polysilicon layer and a portion of the height of the first dielectric layer in the first trench, and forming an isolation layer on the remaining first polysilicon layer in the first trench; forming a second A dielectric layer is formed on the sidewall of the first trench, and the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; a second polysilicon layer is filled in the first trench; a third dielectric layer is formed on the top surface of the substrate, and the third dielectric layer covers the first trench and the second trench; the third dielectric layer is etched to form a first contact hole exposing the second polysilicon layer and the first polysilicon layer in the second trench; and the third dielectric layer and the substrate are etched around the first trench to form a second contact hole, and the depth of the second contact hole is greater than the depth of the first contact hole. The manufacturing method of the power semiconductor device of the present invention can avoid electrical failure.

[0105] An embodiment of the present invention provides a power semiconductor device, comprising: a substrate having a cell region and a terminal region, wherein a first trench is formed in the substrate of the cell region, and a second trench is formed in the substrate of the terminal region; a first dielectric layer is formed on an inner wall of a portion of the height of the first trench and the entire inner wall of the second trench; a first polysilicon layer is filled in the first trench and the second trench at a portion of the height, wherein the top surface of the first polysilicon layer in the second trench is higher than the top surface of the first polysilicon layer in the first trench; an isolation layer is formed on the first polysilicon layer in the first trench; and a second dielectric layer is formed on the first polysilicon layer. The sidewall of the remaining height of the first trench, the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; the second polysilicon layer is filled in the first trench; the third dielectric layer is formed on the top surface of the substrate, and the third dielectric layer covers the first trench and the second trench; a first contact hole and a second contact hole, the first contact hole penetrates the third dielectric layer and exposes the second polysilicon layer and the first polysilicon layer in the second trench, the second contact hole penetrates the third dielectric layer outside the first trench and enters the substrate, and the depth of the second contact hole is greater than the depth of the first contact hole.

[0106] See below Figure 2m The power semiconductor device of this embodiment is described in more detail.

[0107] The substrate 10 has a cell region A1 and a terminal region A2. A first groove (i.e., Figure 2a The first groove 101 shown in FIG. 1 is formed in the substrate 10 of the terminal area A2, and a second groove 102 (i.e. Figure 2a 102 shown in FIG. 1 ).

[0108] The terminal area A2 surrounds a cell array composed of a plurality of cell areas A1.

[0109] The base 10 includes a substrate and an epitaxial layer formed on the substrate.

[0110] The substrate 10 may be made of any suitable material known to those skilled in the art, such as single crystal silicon, silicon germanium, silicon carbide, etc.

[0111] Preferably, the width of the second groove 102 is greater than the width of the first groove 101, and the depth of the second groove 102 is greater than the depth of the first groove 101, so that the pressure-resistant ring formed in the second groove 102 is wider and deeper, thereby improving the pressure-resistant performance of the power semiconductor device.

[0112] The first dielectric layer 11 is formed on a partial height inner wall of the first trench 101 and the entire inner wall of the second trench 102 .

[0113] The first dielectric layer 11 may be made of insulating materials such as silicon oxide or silicon oxynitride.

[0114] The first polysilicon layer 12 is filled in a partial height of the first trench 101 and the second trench 102 , and a top surface of the first polysilicon layer 12 in the second trench 102 is higher than a top surface of the first polysilicon layer 12 in the first trench 101 .

[0115] Preferably, the top surface of the first polysilicon layer 12 in the second trench 102 is flush with the top surface of the substrate 10 outside the second trench 102. In other embodiments, the top surface of the first polysilicon layer 12 in the second trench 102 may be slightly higher or lower than the top surface of the substrate 10.

[0116] The isolation layer 13 is formed on the first polysilicon layer 12 in the first trench 101 .

[0117] In one embodiment, the isolation layer 13 in the first trench 101 can also extend from the first polysilicon layer 12 to the first dielectric layer 11 .

[0118] In one embodiment, the isolation layer 13 may also be formed on the first polysilicon layer 12 in the second trench 102 .

[0119] The isolation layer 13 may be made of insulating materials such as silicon oxide or silicon oxynitride.

[0120] The second dielectric layer 14 is formed on the sidewall of the remaining height of the first trench 101 , and the thickness of the second dielectric layer 14 is less than the thickness of the first dielectric layer 12 .

[0121] In one embodiment, the second dielectric layer 14 may further extend to the top surface of the substrate 10 of the cell area A1 outside the first trench 101 .

[0122] In one embodiment, a mask layer may be formed on the top surface of the substrate 10 in the terminal area A2 outside the second trench 102. The mask layer may be, for example, Figure 2m As shown in the silicon oxide layer 103 , the top surfaces of the silicon oxide layer 103 , the second dielectric layer 14 , the first dielectric layer 11 in the second trench 102 , and the isolation layer 13 are flush.

[0123] The second dielectric layer 14 may be made of insulating materials such as silicon oxide or silicon oxynitride.

[0124] The second polysilicon layer 15 is filled in the first trench 101 .

[0125] The first polysilicon layer 12 in the first trench 101 is used to form a shielding electrode of the transistor unit, and the second polysilicon layer 15 in the first trench 101 is used to form a gate electrode of the transistor unit, and the gate electrode and the shielding electrode are isolated by the isolation layer 13; the first polysilicon layer 12 in the second trench 102 is used to form a voltage-resistant ring of the terminal structure.

[0126] Preferably, the top surface of the second polysilicon layer 15 does not exceed the top surface of the first polysilicon layer 12 in the second trench 102, so as to ensure that the first contact hole (i.e. Figure 2l When the first contact hole 171 is formed in the second trench 102, etching can be stopped when the first contact hole 171 just exposes the top surface of the second polysilicon layer 15, so as to prevent the top surface of the first polysilicon layer 12 in the second trench 102 from being too much lower than the top surface of the second polysilicon layer 15, resulting in the first contact hole 171 having penetrated the second polysilicon layer 15 when the first contact hole 171 just exposes the top surface of the first polysilicon layer 12 in the second trench 102 and etching is stopped, that is, the second polysilicon layer 15 is prevented from being etched through.

[0127] Further preferably, Figure 2iAs shown, a height difference h1 between a top surface of the second polysilicon layer 15 and a top surface of the first polysilicon layer 12 in the second trench 102 is 0.02 μm-0.1 μm, i.e., a top surface of the second polysilicon layer 15 is 0.02 μm-0.1 μm lower than a top surface of the first polysilicon layer 12 in the second trench 102 .

[0128] In other embodiments, the top surface of the second polysilicon layer 15 may be higher than the top surface of the first polysilicon layer 12 in the second groove 102. In this case, the top surface of the second polysilicon layer 15 is preferably 0.02 μm-0.1 μm higher than the top surface of the first polysilicon layer 12 in the second groove 102, so that when the first contact hole 171 is subsequently etched to form the first contact hole 171, when the first contact hole 171 just exposes the first polysilicon layer 12 in the second groove 102 and etching stops, the first contact hole 171 will enter the second polysilicon layer 15 but will not penetrate the second polysilicon layer 15.

[0129] The power semiconductor device further comprises:

[0130] A body region 181 is formed in the substrate 10 around the first trench 101 of the cell region A1 and in the substrate 10 around the second trench 102 of the terminal region A2;

[0131] The source region 182 is formed in the body region 181 outside the first trench 101 of the cell region A1.

[0132] The substrate 10 and the source region 182 have the same doping type, and the source region 182 and the body region 181 have opposite doping types.

[0133] The third dielectric layer 16 is formed on the top surface of the substrate 10 , and the third dielectric layer 16 covers the first trench 101 and the second trench 102 .

[0134] exist Figure 2m In the illustrated embodiment, the third dielectric layer 16 covers the second polysilicon layer 15 , the second dielectric layer 14 , the silicon oxide layer 103 , and the first dielectric layer 11 and the isolation layer 13 in the second trench 102 .

[0135] The third dielectric layer 16 may be made of insulating materials such as silicon oxide or silicon oxynitride.

[0136] The first contact hole 171 penetrates the third dielectric layer 16 and exposes the second polysilicon layer 15 and the first polysilicon layer 12 in the second trench 102. Figure 2lThe second contact hole 172 in the substrate 10 penetrates the third dielectric layer 16 outside the first trench 101 and enters the substrate 10 , and the depth of the second contact hole 172 is greater than the depth of the first contact hole 171 .

[0137] like Figure 2l As shown, there is a height difference h2 between the bottom surface of the second contact hole 172 and the bottom surface of the first contact hole 171 , and the bottom surface of the second contact hole 172 is lower than the bottom surface of the first contact hole 171 .

[0138] It should be noted that the first contact hole 171 on the second polysilicon layer 15 and the first contact hole 171 on the first polysilicon layer 12 in the second trench 102 have the same depth.

[0139] The second contact hole 172 at least exposes the body region 181 at the bottom surface of the source region 182, that is, the second contact hole 172 can just penetrate the source region 182 and expose the body region 181, or, the second contact hole 172 can penetrate the source region 182 and enter the body region 181, so that the contact plug 19 subsequently formed in the second contact hole 172 is electrically connected to the body region 181.

[0140] exist Figure 2m In the illustrated embodiment, the top surface of the second polysilicon layer 15 is lower than the top surface of the first polysilicon layer 12 in the second trench 102, the first contact hole 171 on the second polysilicon layer 15 just penetrates the third dielectric layer 16 and exposes the second polysilicon layer 15, the first contact hole 171 on the first polysilicon layer 12 in the second trench 102 penetrates the third dielectric layer 16 and the isolation layer 13 and enters the first polysilicon layer 12; the second contact hole 172 penetrates the third dielectric layer 16, the second dielectric layer 14 and the source region 182 and enters the body region 181.

[0141] Since the depth of the second contact hole 172 is greater than the depth of the first contact hole 171, that is, the first contact hole 171 and the second contact hole 172 are respectively formed in different etching processes, the second contact hole 172 can reach the required depth while avoiding the first contact hole 171 from penetrating the second polysilicon layer 15, that is, avoiding the second polysilicon layer 15 from being etched through, thereby avoiding increasing the contact resistance and generating leakage, and further avoiding electrical failure problems such as gate-source leakage current failure during electrical testing.

[0142] Preferably, the width of the first contact hole 171 is 80% to 95% of the width of the second contact hole 172, that is, by modifying the layout, the width of the first contact hole 171 is 5% to 20% smaller than the width of the second contact hole 172, thereby preventing the first contact hole 171 from being too large and causing easy deviation during etching, thereby preventing the width of the pressure-resistant ring between the first contact hole 171 and the side wall of the second groove 102 from being too small, thereby avoiding difficulty in field plate contact.

[0143] The power semiconductor device further includes: a contact plug 19 formed in the first contact hole 171 and the second contact hole 172 .

[0144] In summary, the power semiconductor device provided by the present invention comprises: a substrate having a cell region and a terminal region, wherein a first trench is formed in the substrate of the cell region, and a second trench is formed in the substrate of the terminal region; a first dielectric layer is formed on the inner wall of a portion of the height of the first trench and the entire inner wall of the second trench; a first polysilicon layer is filled in the first trench and the second trench at a portion of the height, wherein the top surface of the first polysilicon layer in the second trench is higher than the top surface of the first polysilicon layer in the first trench; an isolation layer is formed on the first polysilicon layer in the first trench; a second dielectric layer is formed The second dielectric layer has a thickness less than that of the first dielectric layer on the sidewall of the remaining height of the first trench; a second polysilicon layer is filled in the first trench; a third dielectric layer is formed on the top surface of the substrate, and the third dielectric layer covers the first trench and the second trench; a first contact hole and a second contact hole, the first contact hole penetrates the third dielectric layer and exposes the second polysilicon layer and the first polysilicon layer in the second trench, the second contact hole penetrates the third dielectric layer outside the first trench and enters the substrate, and the depth of the second contact hole is greater than the depth of the first contact hole. The power semiconductor device provided by the present invention can avoid electrical failure.

[0145] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a power semiconductor device, characterized in that: include: Providing a substrate having a cellular region and a terminal region; forming a first trench in the substrate of the cell region, and forming a second trench in the substrate of the terminal region; forming a first dielectric layer to cover inner walls of the first trench and the second trench; Filling a first polysilicon layer in the first trench and the second trench; Removing a portion of the height of the first polysilicon layer and a portion of the height of the first dielectric layer in the first trench, and forming an isolation layer on the remaining first polysilicon layer in the first trench; forming a second dielectric layer on the sidewall of the first trench, wherein the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; Filling a second polysilicon layer in the first trench; forming a third dielectric layer on the top surface of the substrate, wherein the third dielectric layer covers the first trench and the second trench; Etching the third dielectric layer to form a first contact hole exposing the second polysilicon layer and the first polysilicon layer in the second trench; Furthermore, the third dielectric layer and the substrate at the periphery of the first trench are etched to form a second contact hole, wherein the depth of the second contact hole is greater than the depth of the first contact hole.

2. The method for manufacturing a power semiconductor device according to claim 1, wherein: A top surface of the second polysilicon layer does not exceed a top surface of the first polysilicon layer in the second trench.

3. The method for manufacturing a power semiconductor device according to claim 2, wherein: A height difference between a top surface of the second polysilicon layer and a top surface of the first polysilicon layer in the second trench is 0.02 μm-0.1 μm.

4. The method for manufacturing a power semiconductor device according to claim 1, wherein: The width of the first contact hole is 80% to 95% of the width of the second contact hole.

5. The method for manufacturing a power semiconductor device according to claim 1, wherein: After filling the second polysilicon layer in the first trench and before forming the third dielectric layer on the top surface of the substrate, the method for manufacturing the power semiconductor device further includes: forming a body region in the substrate around the first trench and the second trench; A source region is formed in a body region outside the first trench, and the second contact hole at least exposes the body region at the bottom surface of the source region.

6. The method for manufacturing a power semiconductor device according to claim 1, wherein: The width of the second groove is greater than that of the first groove, and the depth of the second groove is greater than that of the first groove.

7. A power semiconductor device, characterized in that: include: A substrate having a cell region and a terminal region, wherein a first groove is formed in the substrate of the cell region, and a second groove is formed in the substrate of the terminal region; A first dielectric layer formed on a partial height inner wall of the first trench and the entire inner wall of the second trench; A first polysilicon layer is filled in the first trench and the second trench at a partial height, wherein a top surface of the first polysilicon layer in the second trench is higher than a top surface of the first polysilicon layer in the first trench; an isolation layer formed on the first polysilicon layer in the first trench; A second dielectric layer is formed on the sidewall of the remaining height of the first trench, and the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; A second polysilicon layer filled in the first trench; A third dielectric layer is formed on the top surface of the substrate, and the third dielectric layer covers the first groove and the second groove; A first contact hole and a second contact hole, wherein the first contact hole penetrates the third dielectric layer and exposes the second polysilicon layer and the first polysilicon layer in the second trench, and the second contact hole penetrates the third dielectric layer outside the first trench and enters the substrate, and the depth of the second contact hole is greater than the depth of the first contact hole.

8. The power semiconductor device according to claim 7, characterized in that: A top surface of the second polysilicon layer does not exceed a top surface of the first polysilicon layer in the second trench.

9. The power semiconductor device according to claim 8, characterized in that: A height difference between a top surface of the second polysilicon layer and a top surface of the first polysilicon layer in the second trench is 0.02 μm-0.1 μm.

10. The power semiconductor device according to claim 7, characterized in that: The width of the first contact hole is 80% to 95% of the width of the second contact hole.

11. The power semiconductor device according to claim 7, characterized in that: The power semiconductor device further comprises: a body region formed in the substrate around the first trench and the second trench; A source region is formed in a body region outside the first trench, and the second contact hole at least exposes the body region at the bottom surface of the source region.

12. The power semiconductor device according to claim 7, characterized in that: The width of the second groove is greater than that of the first groove, and the depth of the second groove is greater than that of the first groove.

Images