Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a chip, an electrical connector, a plurality of bonding wires, an insulating part and a plastic sealing layer. The chip is provided with a plurality of pads on its front surface. The electrical connector comprises a bearing part and a plurality of pins on the side of the bearing part; the chip is attached to one side of the bearing part with its back surface facing the bearing part. The bonding wires electrically connect the pads with the pins or electrically connect two pads; the plurality of bonding wires comprises a first bonding wire and a second bonding wire, and the first bonding wire is adjacent to the second bonding wire. The insulating part covers at least part of at least one of the first bonding wire and the second bonding wire. The plastic sealing layer encapsulates the chip, the electrical connector, the insulating part and the bonding wires; and at least part of the pins is exposed from the plastic sealing layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a semiconductor structure and a manufacturing method of the semiconductor structure. BACKGROUND

[0002] In a common semiconductor packaging technology, such as a chip packaging technology, the following processes are usually included: firstly, a chip is attached to a lead frame, and the pins of the lead frame are located on one side of the chip; then, bonding wires are used to electrically connect the pads of the chip with the pins, or to connect two pads; and then, a plastic encapsulation layer is formed to encapsulate the chip, the lead frame and the bonding wires.

[0003] In the above packaging technology, during the process of forming the plastic encapsulation layer, the plastic encapsulation material impacts the bonding wires, which easily causes the adjacent bonding wires to contact and short circuit. That is, the yield of the semiconductor product manufactured by the above packaging technology is low. SUMMARY

[0004] The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure.

[0005] According to a first aspect of the present application, a semiconductor structure is provided. The semiconductor structure comprises:

[0006] a chip, the chip comprising a chip front surface and a chip back surface opposite to the chip front surface; the chip front surface is provided with a plurality of pads;

[0007] an electrical connecting member, the electrical connecting member comprising a bearing portion and a plurality of pins located on the side of the bearing portion; the chip is attached to one side of the bearing portion, and the chip back surface faces the bearing portion;

[0008] a plurality of bonding wires, the bonding wires electrically connecting the pads with the pins, or electrically connecting two pads; the plurality of bonding wires comprises a first bonding wire and a second bonding wire, the first bonding wire is adjacent to the second bonding wire;

[0009] an insulating portion, the insulating portion covering at least part of at least one of the first bonding wire and the second bonding wire;

[0010] a plastic encapsulation layer, the plastic encapsulation layer encapsulating the chip, the electrical connecting member, the insulating portion and the bonding wires; and at least part of the pins is exposed from the plastic encapsulation layer.

[0011] In one embodiment, in a direction perpendicular to a plane in which the chip front surface is located, the first bonding wire is adjacent to the second bonding wire, and a projection of a portion of the first bonding wire away from the chip front surface on the plane overlaps a projection of a portion of the second bonding wire away from the chip front surface on the plane; the portion of the second bonding wire away from the chip front surface is located on a side of the first bonding wire away from the carrier; and the insulating portion is located on the chip front surface and covers at least the portion of the first bonding wire away from the chip front surface.

[0012] In one embodiment, the insulating portion covers the first bonding wire and the second bonding wire entirely; and / or,

[0013] In a direction perpendicular to a plane in which the chip front surface is located, a distance between the portion of the first bonding wire away from the chip front surface and the portion of the second bonding wire away from the chip front surface is greater than an outer diameter of the bonding wire.

[0014] In one embodiment, in a direction of the plane in which the chip front surface is located, the first bonding wire is adjacent to the second bonding wire.

[0015] The plurality of pads includes a first pad connected to the first bonding wire and a second pad connected to the second bonding wire, and the first pad is adjacent to the second pad; the plurality of pins includes a first pin connected to the first bonding wire and a second pin connected to the second bonding wire, and the first pin is adjacent to the second pin; a distance between the first pad and the second pad is less than a distance between the first pin and the second pin; and the insulating portion covers at least an end portion of the first bonding wire connected to the first pad and an end portion of the second bonding wire connected to the second pad.

[0016] In one embodiment, a temperature at which the insulating portion is converted from a solid state to a molten state is higher than a solidification temperature of a material of the plastic package layer.

[0017] In one embodiment, the insulating portion covers the chip front surface and a region of the carrier that is not covered by the chip.

[0018] In one embodiment, the electrical connector is a lead frame, and the carrier is spaced apart from the pins; or,

[0019] The electrical connector is a circuit board, and the circuit board includes a main body portion, the pins are located on the main body portion, and the carrier is a portion of the main body portion.

[0020] According to a second aspect of embodiments of the present application, a method for manufacturing a semiconductor structure is provided, including:

[0021] A chip and an electrical connector are provided; the chip comprises a chip front surface and a chip back surface opposite to the chip front surface; the chip front surface is provided with a plurality of pads; the electrical connector comprises a carrier and a plurality of pins located at the side of the carrier;

[0022] The chip is mounted on one side of the carrier; the chip back surface faces the carrier, and the plurality of pins of the electrical connector are located at the side of the chip;

[0023] A plurality of bonding wires are provided; the bonding wires electrically connect the pads and the pins, or electrically connect two pads; the plurality of bonding wires comprise a first bonding wire and a second bonding wire, and the first bonding wire is adjacent to the second bonding wire;

[0024] An insulating part is formed; the insulating part covers at least part of at least one of the first bonding wire and the second bonding wire;

[0025] A plastic encapsulation layer is formed; the plastic encapsulation layer encapsulates the chip, the electrical connector, the insulating part and the bonding wires; and at least part of the pins is exposed from the plastic encapsulation layer.

[0026] In one embodiment, the forming of the insulating part comprises:

[0027] An insulating material is dropped onto the surface of the chip front surface and / or the surface of the carrier exposed, and the insulating material is solidified to form the insulating part.

[0028] In one embodiment, the projection of the dropping trajectory of the insulating material on the plane in which the chip front surface is located does not overlap with the projection of the first bonding wire on the plane, and does not overlap with the projection of the second bonding wire on the plane; and / or,

[0029] The angle between the projection of the dropping trajectory of the insulating material on the plane in which the chip front surface is located and the plane is an acute angle.

[0030] In one embodiment, in the direction perpendicular to the plane in which the chip front surface is located, the first bonding wire is adjacent to the second bonding wire, and the projection of the part of the first bonding wire away from the chip front surface on the plane overlaps with the projection of the part of the second bonding wire away from the chip front surface on the plane; the part of the second bonding wire away from the chip front surface is located on the side of the first bonding wire away from the carrier; the insulating part is located on the chip front surface, and the insulating part covers at least the part of the first bonding wire away from the chip front surface; or,

[0031] The first bonding wire is adjacent to the second bonding wire in the direction of the plane where the front surface of the chip is located; the plurality of pads includes a first pad connected to the first bonding wire and a second pad connected to the second bonding wire, the first pad is adjacent to the second pad; the plurality of pins includes a first pin connected to the first bonding wire and a second pin connected to the second bonding wire, the first pin is adjacent to the second pin; the distance between the first pad and the second pad is less than the distance between the first pin and the second pin; the insulating part at least covers the end of the first bonding wire connected to the first pad and the end of the second bonding wire connected to the second pad.

[0032] The main technical effects achieved by the embodiments of the present application are as follows:

[0033] The semiconductor structure and the manufacturing method of the semiconductor structure provided by the embodiments of the present application can avoid the situation that the adjacent first bonding wire and second bonding wire are in contact and cause short circuit, improve the yield of the semiconductor structure, and the insulating part is a non-conductive structure, which does not affect the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a partial structure diagram of a semiconductor structure provided by an example embodiment of the present application;

[0035] Figure 2 is a sectional view of a semiconductor structure provided by an example embodiment of the present application;

[0036] Figure 3 is a partial structure diagram of a semiconductor structure provided by another example embodiment of the present application;

[0037] Figure 4 is a flowchart of a manufacturing method of a semiconductor structure provided by an example embodiment of the present application. DETAILED DESCRIPTION

[0038] The illustrative examples set forth in the following description are provided merely as examples of specific embodiments consistent with the disclosure. Accordingly, the examples are not intended to limit the disclosure in any way, as the disclosure can be practiced in various ways. The description sets forth various illustrative examples, but these examples are not intended to represent all embodiments consistent with the disclosure. On the contrary, the illustrative examples set forth in the description are intended only to provide examples of apparatus and methods consistent with the disclosure, as set forth in the appended claims.

[0039] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0040] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various information, these terms are not intended to denote a temporal or chronological order. Rather, these terms are used merely as labels to distinguish different specific embodiments from each other. For example, a first information can be termed a second information, and, similarly, a second information can be termed a first information, without departing from the scope of the present disclosure. As used herein, the word "if' can be construed to mean "when" or "upon" or "in response to determining" depending on the context.

[0041] Some embodiments of the present disclosure will now be described in detail in connection with the accompanying drawings. The following embodiments and features are merely exemplary and can be combined with each other in any way.

[0042] The present embodiments provide a semiconductor structure. As shown in Figure 1 and Figure 2 The semiconductor structure includes a chip 10, an electrical connector 20, a plurality of bonding wires 30, an insulating portion 40, and a plastic encapsulation layer 50.

[0043] The chip 10 includes a chip front surface, a chip back surface opposite to the chip front surface, and a plurality of chip side surfaces connecting the chip front surface and the chip back surface; the chip front surface is provided with a plurality of pads 11. The electrical connector 20 includes a carrier 21 and a plurality of pins 22 located at the side of the carrier 21. The pins 22 are located at the side of the carrier 21, which means that the pins 22 are not part of the carrier 21, and there can be a gap between the pins 22 and the side of the carrier 21. The chip 10 is attached to one side of the carrier 21, and the chip back surface faces the carrier 21. The bonding wires 30 electrically connect the pads 11 and the pins 22, or electrically connect two pads 11. The plurality of bonding wires 30 includes a first bonding wire 31 and a second bonding wire 32, and the first bonding wire 31 is adjacent to the second bonding wire 32. The first bonding wire 31 is adjacent to the second bonding wire 32, which means that there is no other bonding wire between them. The insulating part 40 covers at least part of at least one of the first bonding wire 31 and the second bonding wire 32. The plastic package layer 50 encapsulates the chip 10, the electrical connector 20, the insulating part 40, and the bonding wires 30, and at least part of the pins 22 is exposed from the plastic package layer 50.

[0044] The semiconductor structure provided by the embodiments of the present application can avoid the situation that the adjacent first bonding wire and second bonding wire are in contact and cause short circuit, and improve the yield of the semiconductor structure, by setting the insulating part and at least part of at least one of the adjacent first bonding wire and second bonding wire being covered by the insulating part, so that even if the plastic package material impacts the first bonding wire and the second bonding wire during the process of forming the plastic package layer, the first bonding wire and the second bonding wire will not be in contact. The carrier of the electrical connector can fix the chip and the electrical connector together, prevent the relative movement of the chip and the electrical connector during the process of forming the plastic package layer, and affect the reliability of the electrical connection between the pad and the pin, which helps to improve the yield of the semiconductor structure. The insulating part is a non-conductive structure, which does not affect the electrical performance of the semiconductor structure.

[0045] In one embodiment, the plurality of bonding wires 30 can include two or more first bonding wires 31 and a second bonding wire 32 adjacent to each first bonding wire 31. For each first bonding wire 31 and the second bonding wire 32 adjacent thereto, the insulating part 40 covers at least part of at least one of them.

[0046] In one embodiment, the semiconductor structure includes two or more chips 10, and the bonding wires 30 can connect the pads 11 of different chips 10. Figure 1In the illustrated embodiment, the semiconductor structure includes two chips 10. A first bonding wire 31 connects two pads 11, each of which belongs to a different chip 10. A second bonding wire 32 connects two pads 11, each of which belongs to a different chip 10.

[0047] In another embodiment, the semiconductor structure includes one chip 10. The bonding wire 30 connects two pads 11 of the chip 10.

[0048] In one embodiment, as shown in FIG. 1, the semiconductor structure includes a chip 10. The chip 10 includes a plurality of pads 11. The pads 11 are arranged in a matrix. Figure 1 Figure 1 In the illustrated embodiment, only some of the pins 22 are connected to the pads 11. In practice, each pin 22 is electrically connected to a pad 11 of the chip 10 by a bonding wire 30.

[0049] In one embodiment, as shown in FIG. 1, the semiconductor structure includes a chip 10. The chip 10 includes a plurality of pads 11. The pads 11 are arranged in a matrix. Figure 2 In the illustrated embodiment, the chip 10 is attached to one side of the carrier 21 by an adhesive 60. In some embodiments, the adhesive 60 is electrically conductive. For example, the adhesive 60 can be solidified from silver paste. In other embodiments, the adhesive 60 is electrically non-conductive.

[0050] Figure 1 Figure 2 In one embodiment, as shown in FIG. 1, the electrical connector 20 is a lead frame. The carrier 21 is an island of the lead frame. The carrier 21 is spaced apart from the pins 22. In other embodiments, the electrical connector can be a circuit board. The circuit board includes a main body on which the pins are disposed. The carrier is a portion of the main body that is not occupied by the pins or other components.

[0051] In one embodiment, as shown in FIG. 1, the electrical connector 20 is a lead frame. The carrier 21 is an island of the lead frame. The carrier 21 is spaced apart from the pins 22. In other embodiments, the electrical connector can be a circuit board. The circuit board includes a main body on which the pins are disposed. The carrier is a portion of the main body that is not occupied by the pins or other components. Figure 1 2 ​​​​As shown, in the direction perpendicular to the plane where the chip front surface is located, the first bonding wire 31 is adjacent to the second bonding wire 32, and the orthogonal projection of the part 311 of the first bonding wire 31 away from the chip front surface on the plane where the chip front surface is located overlaps with the orthogonal projection of the part 321 of the second bonding wire 32 away from the chip front surface on the plane. The part 321 of the second bonding wire 32 away from the chip front surface is located on the side of the first bonding wire 31 away from the carrier 21. The insulating part 40 covers the chip 10, and the insulating part 40 at least covers the part 311 of the first bonding wire 31 away from the chip front surface. When the insulating part 40 is formed, the distance from the surface of the insulating part 40 away from the carrier 21 to the carrier 21 can be controlled to make the insulating part 40 at least cover the part 311 of the first bonding wire 31 away from the chip front surface which is closer to the carrier 21. In this way, a part of the insulating part 40 is located between the part 311 of the first bonding wire 31 away from the chip front surface and the part 321 of the second bonding wire 32 away from the chip front surface, and the insulating part 40 is at least connected to the part 311 of the first bonding wire 31 away from the chip front surface, which can effectively avoid the contact between the first bonding wire 31 and the second bonding wire 32 caused by the impact of the plastic sealing material during the process of forming the plastic sealing layer.

[0052] Further, as shown, Figure 2 the insulating part 40 covers the first bonding wire 31 and the second bonding wire 32. In this way, during the process of forming the plastic sealing layer, the first bonding wire 31 and the second bonding wire 32 will not move even under the impact of the plastic sealing material, which can more effectively avoid the contact between the first bonding wire 31 and the second bonding wire 32.

[0053] Further, in the direction perpendicular to the plane where the chip front surface is located, the distance between the part 311 of the first bonding wire 31 away from the chip front surface and the part 321 of the second bonding wire 32 away from the chip front surface is greater than the outer diameter of the bonding wire 30. In this way, there is a certain distance between the part 311 of the first bonding wire 31 away from the chip front surface and the part 321 of the second bonding wire 32 away from the chip front surface, which helps to avoid the contact between the first bonding wire 31 and the second bonding wire 32 caused by the impact of the insulating material during the process of forming the insulating part 40. In some embodiments, in the direction perpendicular to the plane where the chip front surface is located, the distance between the part 311 of the first bonding wire 31 away from the chip front surface and the part 321 of the second bonding wire 32 away from the chip front surface is greater than twice the outer diameter of the bonding wire 30. In this way, the contact between the first bonding wire 31 and the second bonding wire 32 caused by the impact of the insulating material can be more effectively avoided.

[0054] In one embodiment, as Figure 3In the shown embodiment, the first bonding wire 31 and the second bonding wire 32 are adjacent to each other in the direction of the plane in which the front surface of the chip 10 is located. The plurality of pads 11 includes a first pad 111 connected to the first bonding wire 31 and a second pad 112 connected to the second bonding wire 32, and the first pad 111 is adjacent to the second pad 112. The plurality of pins 22 includes a first pin 221 connected to the first bonding wire 31 and a second pin 222 connected to the second bonding wire 32, and the first pin 221 is adjacent to the second pin 222. The distance between the first pad 111 and the second pad 112 is smaller than the distance between the first pin 221 and the second pin 222. The insulating portion 40 covers at least the end of the first bonding wire 31 connected to the first pad 111 and the end of the second bonding wire 32 connected to the second pad 112. The distance between the end of the first bonding wire 31 connected to the first pad 111 and the end of the second bonding wire 32 connected to the second pad 112 is small, and they are more likely to contact after being impacted by the plastic package material. Therefore, the insulating portion 40 covers the end of the first bonding wire 31 connected to the first pad 111 and the end of the second bonding wire 32 connected to the second pad 112, which can effectively prevent the first bonding wire 31 from contacting the second bonding wire 32 and causing short circuit. Figure 3 In the shown embodiment, the insulating portion 40 only covers the end of the first bonding wire 31 connected to the first pad 111 and the end of the second bonding wire 32 connected to the second pad 112. In other embodiments, the insulating portion 40 can cover all of the first bonding wire 31 and the second bonding wire 32.

[0055] In one embodiment, the insulating portion 40 covers each bonding wire 30. In this way, the arrangement of the insulating portion 40 can effectively prevent any adjacent two bonding wires 30 from contacting and causing short circuit during the process of forming the plastic package layer. At the same time, it can prevent the bonding wires from being impacted by the plastic package material and collapsing, and the collapsed part of the bonding wire contacting the conductive structure on the surface of the chip and causing short circuit.

[0056] In one embodiment, the insulating portion 40 covers the entire area of the front surface of the chip 10. In this way, the insulating portion 40 can protect the pads 11 arranged on the front surface of the chip 10.

[0057] Further, the insulating portion 40 covers the front surface of the chip 10 and the area of the carrier portion 21 not covered by the chip 10. In this way, the insulating portion 40 can make the chip 10 fixed more firmly on the carrier portion 21, and further prevent the chip 10 from moving relative to the carrier portion 21.

[0058] In one embodiment, as shown in FIG. 1, the insulating portion 40 covers the entire area of the front surface of the chip 10. Figure 2 and Figure 3As shown, the insulating portion 40 does not cover the pin 22. In other embodiments, the insulating portion 40 may cover at least a portion of the pin 22. If the insulating material has good flowability during the formation of the insulating portion 40, the insulating material may flow to the surface of the pin 22 facing the bonding wire 30, so that the finally formed insulating portion 40 covers at least a portion of the surface of the pin 22.

[0059] In one embodiment, the insulating portion 40 is made of acrylic hot melt adhesive (AD glue). This results in a lower material cost for the insulating portion 40, without significantly increasing the fabrication cost of the semiconductor structure. In other embodiments, the insulating portion 40 can be made of other materials that can be dynamically converted from a fluid state to a solid state.

[0060] In one embodiment, the temperature at which the insulating portion 40 transforms from a solid to a molten state is higher than the curing temperature of the material of the molding compound 30. The molding compound 30 is formed after the insulating portion 40. By setting the temperature at which the insulating portion 40 transforms from a solid to a molten state to a higher temperature than the curing temperature of the material of the molding compound 30, it is possible to avoid the insulating portion 40 transforming into a molten state during the curing process of the molding compound, which would cause the insulating portion 40 to no longer cover the bonding wires it covered before melting, potentially leading to contact between adjacent bonding wires.

[0061] In one embodiment, the insulating portion 40 covers the front side of the chip 10, and the material of the insulating portion 40 is a material with very low transmittance, for example, the material of the insulating portion 40 may be black. This arrangement makes it impossible to directly observe the structure of the chip 10, increasing the difficulty of technically deciphering the semiconductor structure.

[0062] In one embodiment, such as Figure 2 As shown, the surface of pin 22 facing away from the front of the chip exposes the molding compound 50. In other embodiments, the end of pin 22 away from the chip may expose the molding compound 50. The portion of pin 22 exposed in the molding compound can be electrically connected to external components.

[0063] In one embodiment, the material of the encapsulation layer 50 can be a polymer resin, resin composite material, polymer composite material, etc. For example, the encapsulation layer 50 can be a resin with fillers, wherein the fillers can be inorganic particles. The encapsulation layer 50 can be formed by injection molding, compression molding, or transfer molding.

[0064] This application also provides a method for manufacturing a semiconductor structure. For example... Figure 4 As shown, the method for manufacturing the semiconductor structure includes the following steps 110 to 150.

[0065] In step 110, a chip and an electrical connector are provided; the chip includes a chip front surface, a chip back surface opposite to the chip front surface, and a plurality of chip side surfaces connecting the chip front surface and the chip back surface; the chip front surface is provided with a plurality of pads; the electrical connector includes a carrier and a plurality of pins located on the side of the carrier.

[0066] In step 120, the chip is attached to one side of the carrier; the chip back surface faces the carrier, and the plurality of pins of the electrical connector are located on the side of the chip.

[0067] In one embodiment, the step of attaching the chip to one side of the carrier can include the following process:

[0068] First, silver paste is applied to one side of the carrier;

[0069] Then, the chip is placed on the silver paste;

[0070] Then, the silver paste is cured, and after the silver paste is cured, the chip is fixed to the carrier by the cured silver paste.

[0071] In step 130, a plurality of bonding wires are provided, the bonding wires electrically connecting the pads and the pins, or electrically connecting two pads; the plurality of bonding wires include a first bonding wire and a second bonding wire, and the first bonding wire is adjacent to the second bonding wire.

[0072] In one embodiment, the two ends of the bonding wire can be bonded to the conductive part and the pad respectively by wire bonding, or the two ends of the bonding wire can be bonded to two pads respectively by wire bonding. Wire bonding refers to a method of tightly welding two structures by using heat, pressure, and ultrasonic energy.

[0073] In step 140, an insulating part is formed, the insulating part covering at least part of at least one of the first bonding wire and the second bonding wire.

[0074] In one embodiment, the step of forming the insulating part can include the following process: a flowable insulating material is dropped onto the exposed surface of the chip front surface and / or the carrier, and the insulating material is cured to form the insulating part. After the amount of the insulating material dropped onto the chip front surface and the surface of the carrier not covered by the chip gradually increases, the height of the insulating material increases, so that the insulating material can cover at least one of the first bonding wire and the second bonding wire. The finally formed insulating part can cover the chip front surface, or can cover the area of the carrier not covered by the chip.

[0075] In one embodiment, the drop trajectory of the insulating material has no intersection with the projection of the first bonding wire on the plane where the front surface of the chip is located, and has no intersection with the projection of the second bonding wire on the plane. The insulating material drops under the action of gravity, and the drop trajectory is a straight line. In this way, the insulating material can be prevented from directly dropping on the first bonding wire or the second bonding wire, so that the first bonding wire or the second bonding wire is deformed to contact each other.

[0076] In one embodiment, the drop trajectory of the insulating material has no intersection with the projection of each of the bonding wires on the plane where the front surface of the chip is located. In this way, the insulating material can be prevented from directly dropping on the bonding wires to cause the bonding wires to collapse, and the collapsed part of the bonding wires contacts the conductive structure on the surface of the chip to cause short circuit.

[0077] In one embodiment, the angle between the drop trajectory of the insulating material and the plane where the front surface of the chip is located is an acute angle. In this way, the impact force of the insulating material on the bonding wires can be reduced, and the short circuit of the adjacent bonding wires caused by the impact of the bonding wires, and the short circuit caused by the collapse of the bonding wires after the impact to contact the conductive structure on the surface of the chip can be improved. When the insulating material is dropped on the front surface of the chip or the surface of the carrier which is not covered by the front surface of the chip, the structure including the chip, the electrical connecting member and the bonding wires can be tilted to a certain angle with the horizontal direction before the insulating material is dropped, so that the angle between the drop trajectory of the insulating material and the plane where the front surface of the chip is located is an acute angle.

[0078] In some embodiments, the impact force of the insulating material on the bonding wires can be reduced by controlling the drop speed of the insulating material.

[0079] In step 150, a plastic encapsulation layer is formed, the plastic encapsulation layer encapsulates the chip, the electrical connecting member, the insulating part and the bonding wires, and at least part of the pins is exposed from the plastic encapsulation layer.

[0080] In one embodiment, before the plastic encapsulation layer is formed, some pretreatment steps such as chemical cleaning, plasma cleaning and the like can be performed to remove impurities on the surface of the chip, the electrical connecting member and the insulating part, so that the plastic encapsulation layer can be more closely connected with the chip, the electrical connecting member and the insulating part, and delamination or cracking phenomenon does not occur.

[0081] In one embodiment, the material of the plastic encapsulation layer can be polymer resin, resin composite material, polymer composite material and the like. For example, the plastic encapsulation layer can be resin with filler, and the filler can be inorganic particles. The plastic encapsulation layer can be formed by injection molding, compression molding or transfer molding and the like.

[0082] In one embodiment, the first bonding wire is adjacent to the second bonding wire in a direction perpendicular to a plane in which the chip front surface lies, and a projection of a portion of the first bonding wire away from the chip front surface on the plane overlaps a projection of a portion of the second bonding wire away from the chip front surface on the plane; the portion of the second bonding wire away from the chip front surface is located on a side of the first bonding wire facing away from the carrier; the insulating portion covers the chip, and the insulating portion at least covers the portion of the first bonding wire away from the chip front surface.

[0083] In one embodiment, the first bonding wire is adjacent to the second bonding wire in a direction perpendicular to a plane in which the chip front surface lies, and a projection of a portion of the first bonding wire away from the chip front surface on the plane overlaps a projection of a portion of the second bonding wire away from the chip front surface on the plane; the portion of the second bonding wire away from the chip front surface is located on a side of the first bonding wire facing away from the carrier; the insulating portion covers the chip, and the insulating portion at least covers the portion of the first bonding wire away from the chip front surface.

[0084] Embodiments of the semiconductor structure provided by the present application and embodiments of the method for manufacturing a semiconductor structure belong to the same inventive concept, and the descriptions of related details and advantages can be referred to each other, which will not be described here in detail.

[0085] It is noted that in the drawings, the dimensions of layers and regions can be exaggerated for clarity. Also, it can be understood that when a layer or element is referred to as being "on" another layer or element, it can be directly on the other layer or element or intervening layers can also be present. In addition, it can be understood that when a layer or element is referred to as being "beneath" another layer or element, it can be directly beneath the other layer or element or one or more intervening layers or elements can also be present. Also, it can be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer or element between the two layers or elements or one or more intervening layers or elements can also be present. Like reference numerals refer to like elements throughout.

[0086] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0087] It is to be understood that the application is not limited to the precise construction already described above and shown in the drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application should only be limited by the claims appended hereto.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a chip comprising a chip front surface and a chip back surface opposite to the chip front surface; the chip front surface is provided with a plurality of pads; an electrical connector comprising a carrier and a plurality of pins located on the side of the carrier; the chip is attached to one side of the carrier, and the chip back surface faces the carrier; a plurality of bonding wires electrically connecting the pads and the pins, or electrically connecting two pads; the plurality of bonding wires comprises a first bonding wire and a second bonding wire, the first bonding wire is adjacent to the second bonding wire; an insulating portion covering at least part of at least one of the first bonding wire and the second bonding wire; a plastic encapsulation layer encapsulating the chip, the electrical connector, the insulating portion and the bonding wires; and at least part of the pins is exposed from the plastic encapsulation layer; in a direction perpendicular to the plane in which the chip front surface is located, the first bonding wire and the second bonding wire are adjacent to each other, and the projection of the part of the first bonding wire away from the chip front surface on the plane in which the chip front surface is located overlaps with the projection of the part of the second bonding wire away from the chip front surface on the plane; the part of the second bonding wire away from the chip front surface is located on the side of the first bonding wire away from the carrier; the insulating portion is located on the chip front surface, and the insulating portion covers at least the part of the first bonding wire away from the chip front surface; the distance between the part of the first bonding wire away from the chip front surface and the part of the second bonding wire away from the chip front surface in a direction perpendicular to the plane in which the chip front surface is located is greater than the outer diameter of the bonding wire.

2. The semiconductor structure of claim 1, wherein, The insulating portion covers the first bonding wire and the second bonding wire.

3. The semiconductor structure of claim 1, wherein, In the direction of the plane in which the chip front surface is located, the first bonding wire and the second bonding wire are adjacent to each other; The plurality of pads comprises a first pad connected to the first bonding wire and a second pad connected to the second bonding wire, the first pad and the second pad are adjacent to each other; the plurality of pins comprises a first pin connected to the first bonding wire and a second pin connected to the second bonding wire, the first pin and the second pin are adjacent to each other; the distance between the first pad and the second pad is less than the distance between the first pin and the second pin; the insulating portion covers at least the end of the first bonding wire connected to the first pad and the end of the second bonding wire connected to the second pad.

4. The semiconductor structure of claim 1, wherein, The temperature at which the insulating portion changes from a solid state to a molten state is higher than the solidification temperature of the material of the plastic encapsulation layer.

5. The semiconductor structure of claim 1, wherein, The insulating portion covers the chip front surface and the area of the carrier not covered by the chip.

6. The semiconductor structure of claim 1, wherein, The electrical connector is a lead frame, and the carrier and the pins are spaced apart; or The electrical connector is a circuit board, and the circuit board comprises a main body portion, the pins are located on the main body portion, and the carrier is a part of the main body portion.

7. A method of manufacturing a semiconductor structure, characterized by, comprises: providing a chip and an electrical connector; the chip comprises a chip front surface and a chip back surface opposite to the chip front surface; The chip front surface is provided with a plurality of pads; the electrical connector comprises a bearing part and a plurality of pins located on the side of the bearing part; The chip is attached to one side of the bearing part; the chip back surface faces the bearing part, and the plurality of pins of the electrical connector are located on the side of the chip; A plurality of bonding wires are provided, which electrically connect the pads and the pins or electrically connect two pads; the plurality of bonding wires comprise a first bonding wire and a second bonding wire, and the first bonding wire is adjacent to the second bonding wire; An insulating part is formed, which covers at least part of at least one of the first bonding wire and the second bonding wire; A plastic encapsulation layer is formed, which encapsulates the chip, the electrical connector, the insulating part and the bonding wires; At least part of the pins is exposed from the plastic encapsulation layer; The formation of the insulating part comprises: dropping a flowable insulating material on the exposed surface of the chip front surface and / or the bearing part, and solidifying the insulating material to form the insulating part; The orthogonal projection of the dropping track of the insulating material on the plane in which the chip front surface is located does not overlap with the orthogonal projection of the first bonding wire on the plane, and does not overlap with the orthogonal projection of the second bonding wire on the plane; and / or, the included angle between the orthogonal projection of the dropping track of the insulating material on the plane in which the chip front surface is located and the plane is an acute angle.

8. The method of manufacturing a semiconductor structure according to claim 7, wherein In the direction perpendicular to the plane in which the chip front surface is located, the first bonding wire is adjacent to the second bonding wire, and the orthogonal projection of the part of the first bonding wire away from the chip front surface on the plane in which the chip front surface is located overlaps with the orthogonal projection of the part of the second bonding wire away from the chip front surface on the plane; The part of the second bonding wire away from the chip front surface is located on the side of the first bonding wire away from the bearing part; The insulating part is located on the chip front surface, and the insulating part covers at least the part of the first bonding wire away from the chip front surface; or In the direction of the plane in which the chip front surface is located, the first bonding wire is adjacent to the second bonding wire; the plurality of pads comprise a first pad connected to the first bonding wire and a second pad connected to the second bonding wire, and the first pad is adjacent to the second pad; the plurality of pins comprise a first pin connected to the first bonding wire and a second pin connected to the second bonding wire, and the first pin is adjacent to the second pin; the distance between the first pad and the second pad is smaller than the distance between the first pin and the second pin; the insulating part covers at least the end of the first bonding wire connected to the first pad and the end of the second bonding wire connected to the second pad.

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