Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; the interlayer dielectric layer is formed on the substrate; the metal interconnection structure is formed in the interlayer dielectric layer, the metal interconnection structure comprises two metal layers and a through hole plug, each metal layer comprises at least one metal wire, each metal wire comprises a plurality of sections of sub-metal wires, the sub-metal wires in the adjacent layers of metal wires are arranged in a staggered manner, and the through hole plug is arranged between the sub-metal wires. And the sub-metal wires in the metal wires of the adjacent layers are electrically connected through the through hole plugs. According to the technical scheme, the parasitic capacitance of the semiconductor device can be obviously reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Semiconductor devices (such as MOS transistors) will have certain parasitic capacitance in practical applications. These parasitic capacitances will have a certain impact on the performance of the circuit, causing the semiconductor device to generate additional charge and voltage fluctuations when switching, thereby affecting the response speed of the circuit. In addition, since additional power is consumed during switching, parasitic capacitance will also increase the power consumption of the semiconductor device, while introducing additional interference signals and increasing the noise of the circuit.

[0003] In order to reduce parasitic capacitance, conventional processes generally use materials with low dielectric constant (k) or air gaps as interlayer dielectric layers. However, this method requires the use of additional materials or processes.

[0004] Therefore, how to significantly reduce the parasitic capacitance of semiconductor devices is a problem that needs to be solved urgently. Summary of the invention

[0005] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can significantly reduce the parasitic capacitance of the semiconductor device.

[0006] To achieve the above object, the present invention provides a semiconductor device, comprising:

[0007] substrate;

[0008] An interlayer dielectric layer formed on the substrate;

[0009] A metal interconnect structure is formed in the interlayer dielectric layer, the metal interconnect structure includes two metal layers and through-hole plugs, each metal layer includes at least one metal wire, each metal wire includes multiple segments of sub-metal wires, the sub-metal wires in the metal wires of adjacent layers are staggered, and the sub-metal wires in the metal wires of adjacent layers are electrically connected through the through-hole plugs.

[0010] Optionally, each metal layer includes at least two metal wires; and in each metal layer, the sub-metal wires in two adjacent metal wires are staggered.

[0011] Optionally, the semiconductor device further includes:

[0012] A shallow trench isolation structure is formed in the substrate, wherein the shallow trench isolation structure defines an active area;

[0013] A gate structure formed on the active area;

[0014] A source region and a drain region formed in the active region;

[0015] The metal interconnect structure further includes a contact plug, and the bottom metal layer is electrically connected to the source region or the drain region through the contact plug.

[0016] Optionally, the sub-metal lines in the metal lines of adjacent layers are electrically connected via at least two through-hole plugs.

[0017] Optionally, the semiconductor device further includes: a virtual gate, wherein the virtual gate is located on both sides of the gate structure.

[0018] Optionally, the metal interconnect structure includes a first metal layer and a second metal layer, wherein the second metal layer also includes a metal block, the metal line extends in a first direction, the metal block extends in a second direction, the metal blocks are located at both ends of the metal line, and each of the metal blocks is connected to the source region or the drain region.

[0019] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0020] providing a substrate;

[0021] An interlayer dielectric layer and a metal interconnection structure are formed, wherein the interlayer dielectric layer is formed on the substrate, and the metal interconnection structure is formed in the interlayer dielectric layer; the metal interconnection structure includes two metal layers and a through-hole plug, each metal layer includes at least one metal wire, each metal wire includes multiple segments of sub-metal wires, the sub-metal wires in the metal wires of adjacent layers are staggered, and the sub-metal wires in the metal wires of adjacent layers are electrically connected through the through-hole plugs.

[0022] Optionally, each metal layer includes at least two metal wires; and in each metal layer, the sub-metal wires in two adjacent metal wires are staggered.

[0023] Optionally, before forming the interlayer dielectric layer and the metal interconnect structure, the method for manufacturing the semiconductor device further includes:

[0024] forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure defines an active area;

[0025] forming a gate structure on the active area;

[0026] forming a source region and a drain region in the active region;

[0027] The metal interconnect structure further includes a contact plug, and the bottom metal layer is electrically connected to the source region or the drain region through the contact plug.

[0028] Optionally, the sub-metal lines in the metal lines of adjacent layers are electrically connected via at least two through-hole plugs.

[0029] Optionally, the metal interconnect structure includes a first metal layer and a second metal layer, wherein the second metal layer also includes a metal block, the metal line extends in a first direction, the metal block extends in a second direction, the metal blocks are located at both ends of the metal line, and each of the metal blocks is connected to the source region or the drain region.

[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0031] 1. The semiconductor device of the present invention has a metal interconnect structure including two metal layers and a through-hole plug, each metal layer includes at least one metal wire, each metal wire includes a plurality of sub-metal wires, the sub-metal wires in the metal wires of adjacent layers are staggered, and the sub-metal wires in the metal wires of adjacent layers are electrically connected through the through-hole plug, so that the parasitic capacitance of the semiconductor device can be significantly reduced.

[0032] 2. The manufacturing method of the semiconductor device of the present invention forms an interlayer dielectric layer and a metal interconnection structure, wherein the interlayer dielectric layer is formed on a substrate, and the metal interconnection structure is formed in the interlayer dielectric layer; the metal interconnection structure includes two metal layers and a through-hole plug, each metal layer includes at least one metal wire, each metal wire includes multiple segments of sub-metal wires, the sub-metal wires in the metal wires of adjacent layers are staggered, and the sub-metal wires in the metal wires of adjacent layers are electrically connected through the through-hole plugs, so that the parasitic capacitance of the semiconductor device can be significantly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention;

[0034] Figure 2a is a schematic longitudinal cross-sectional view of a metal interconnect structure according to an embodiment of the present invention;

[0035] Figure 2b yes Figure 1 A longitudinal cross-sectional schematic diagram of the semiconductor device along the AA' direction is shown;

[0036] Figure 3 yes Figure 1 A longitudinal cross-sectional schematic diagram of the semiconductor device along the BB' direction shown;

[0037] Figure 4 The flowchart of the method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0038] Among them, Figure 1 to Figure 4 The reference numerals are described as follows:

[0039] 10-substrate; 101-shallow trench isolation structure; 11-interlayer dielectric layer; 121a-first sub-metal line; 121b-first connection layer; 121c-second connection layer; 122-second metal layer; 122a-second sub-metal line; 122b-metal block; 131-via plug; 132-contact plug; 14-gate structure; 15-dummy gate. DETAILED DESCRIPTION

[0040] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0041] An embodiment of the present invention provides a semiconductor device, comprising: a substrate; an interlayer dielectric layer formed on the substrate; a metal interconnect structure formed in the interlayer dielectric layer, the metal interconnect structure comprising two metal layers and a through-hole plug, each of the metal layers comprising at least one metal wire, each of the metal wires comprising a plurality of sub-metal wires, the sub-metal wires in the metal wires of adjacent layers being staggered, and the sub-metal wires in the metal wires of adjacent layers being electrically connected via the through-hole plugs.

[0042] See below Figure 1 to Figure 3 The semiconductor device provided by this embodiment is described in more detail. Figure 1 The shallow trench isolation structure 101 and the interlayer dielectric layer 11 are not shown.

[0043] The substrate 10 may be a single-layer structure, or may include a multi-layer structure composed of the same or different materials. The substrate 10 may be made of semiconductor materials such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors, or may include a layered substrate such as Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator, or may include other materials other than semiconductor materials, which is not limited in the present application.

[0044] The interlayer dielectric layer 11 is formed on the substrate 10 .

[0045] The interlayer dielectric layer 11 may include multiple stacked insulating layers.

[0046] The metal interconnect structure is formed in the interlayer dielectric layer 11, and the metal interconnect structure includes two metal layers (i.e., the first metal layer and the second metal layer 122) and a through-hole plug 131. Each metal layer includes at least one metal wire, and each metal wire includes multiple segments of sub-metal wires. In two adjacent metal layers, the sub-metal wires in the metal wires of the adjacent layers are staggered, and the sub-metal wires in the metal wires of the adjacent layers are electrically connected through the through-hole plug 131. The staggered arrangement of the sub-metal wires in the metal wires of the adjacent layers means that the sub-metal wires in the metal wires of the adjacent layers are staggered between their projections in a direction perpendicular to the surface of the substrate 10, such as Figure 2a As shown, in this direction, the first sub-metal line 121 a in the first metal layer and the second sub-metal line 122 a in the second metal layer are staggered and electrically connected through the via plug 131 .

[0047] Among them, in two adjacent metal layers, the projections of the sub-metal wires in the metal wires in the adjacent layers in a direction perpendicular to the surface of the substrate 10 only overlap at their ends, and the projections of the areas other than the ends of the sub-metal wires in the metal wires in the adjacent layers in a direction perpendicular to the surface of the substrate 10 do not overlap, and the through-hole plugs 131 are located between the ends of the sub-metal wires in the metal wires in the adjacent layers, and the segments of the sub-metal wires in the metal wires in the adjacent layers are alternately connected in sequence through the through-hole plugs 131 to achieve electrical connection between the metal wires in the adjacent layers.

[0048] Since the sub-metal wires in the metal wires of adjacent layers are staggered between their projections in a direction perpendicular to the surface of the substrate 10, the overlapping area between the projections of the metal wires of adjacent layers in a direction perpendicular to the surface of the substrate 10 is significantly reduced, thereby significantly reducing the overlapping area between the projections of the metal layers of adjacent layers in a direction perpendicular to the surface of the substrate 10 (i.e., the facing area of ​​the metal layers of adjacent layers), thereby significantly reducing the parasitic capacitance formed by the metal layers of adjacent layers and the interlayer dielectric layer 11 therebetween, i.e., significantly reducing the parasitic capacitance of the semiconductor device.

[0049] In one embodiment, each metal layer includes at least two metal wires. Preferably, in each metal layer, the sub-metal wires in two adjacent metal wires are staggered. The staggered arrangement of the sub-metal wires in two adjacent metal wires refers to staggered arrangement in a direction perpendicular to the extension direction of the metal wires, such as Figure 1As shown, in the same metal layer, the first sub-metal wire 121a in one metal wire is staggered with the first sub-metal wire 121a in an adjacent metal wire. In each metal layer, the ends of the sub-metal wires in two adjacent metal wires may overlap or not overlap in a direction perpendicular to the extension of the metal wires, and the areas other than the ends of the sub-metal wires in two adjacent metal wires do not overlap in a direction perpendicular to the extension of the metal wires.

[0050] Since in each metal layer, the sub-metal wires in two adjacent metal wires are staggered in a direction perpendicular to the extension direction of the metal wires, the overlapping area of ​​the two adjacent metal wires in each metal layer in the direction perpendicular to the extension direction of the metal wires (i.e., the facing area of ​​the two adjacent metal wires) is significantly reduced, thereby significantly reducing the parasitic capacitance formed by the two adjacent metal wires in each metal layer and the interlayer dielectric layer 11 therebetween, thereby further significantly reducing the parasitic capacitance of the semiconductor device.

[0051] In one embodiment, the second metal layer 122 further includes a metal block 122b, the metal line can extend in a first direction, the metal block 122b can extend in a second direction, the metal blocks 122b can be located at both ends of the metal line, one end of the metal line in the second metal layer 122 is connected to one of the metal blocks 122b, and the other end of the metal line in the second metal layer 122 is not connected to another of the metal blocks 122b. The first direction is different from the second direction; in one embodiment, the first direction is perpendicular to the second direction.

[0052] The two metal blocks 122 b are arranged opposite to each other, and all the metal wires are arranged in sequence and spaced apart along the second direction between the two metal blocks 122 b.

[0053] In one embodiment, the second metal layer 122 includes two relatively staggered comb-shaped structures, each of the comb-shaped structures includes a plurality of comb teeth arranged in sequence and a comb back located at the same end of each comb tooth, the comb backs of the two comb-shaped structures are parallel to each other, and the comb teeth are perpendicular to the comb backs, the comb teeth and the comb backs can be connected, the metal wire serves as the comb teeth, and the metal block 122b serves as the comb back.

[0054] like Figure 1 to Figure 3As shown, the metal interconnect structure includes a first metal layer and a second metal layer 122, the second metal layer 122 is located above the first metal layer; the first metal layer includes a plurality of first metal wires extending in a first direction Y, each of the first metal wires is arranged at intervals in a second direction X, each of the first metal wires includes a plurality of first sub-metal wires 121a, and the first sub-metal wires 121a in two adjacent first metal wires are arranged staggered in the second direction X; the second metal layer 122 includes two relatively staggered comb-shaped structures, each of the comb-shaped structures includes a plurality of second metal wires extending in the first direction Y and a metal block 122b extending in the second direction X, each of the second metal wires includes A plurality of segments of second sub-metal wires 122a, the second sub-metal wire 122a closest to the metal block 122b in each of the comb-shaped structures is connected to the metal block 122b, the second metal wires in the two comb-shaped structures are interlaced and arranged in a staggered manner, the second sub-metal wires 122a in two adjacent second metal wires are staggered in the second direction X; the projections of the first sub-metal wires 121a in the first metal wires and the second sub-metal wires 122a in the second metal wires in a direction perpendicular to the surface of the substrate 10 are staggered, and each segment of the first sub-metal wire 121a and each segment of the second sub-metal wire 122a are alternately electrically connected in sequence through the through-hole plug 131. The first direction Y is perpendicular to the second direction X.

[0055] The semiconductor device further comprises:

[0056] A shallow trench isolation structure 101 is formed in the substrate 10, and the shallow trench isolation structure 101 defines an active area;

[0057] The gate structure 14 is formed on the active area. In one embodiment, the gate structure 14 may also extend from the active area to the shallow trench isolation structure 101;

[0058] A source region (not shown) and a drain region (not shown) are formed in the active region.

[0059] Each of the metal blocks 122 b in the second metal layer 122 is electrically connected to the source region or the drain region, that is, each of the comb-shaped structures is electrically connected to the source region or the drain region.

[0060] like Figure 1 and Figure 2bAs shown, the semiconductor device also includes: a first connection layer 121b and a second connection layer 121c extending in a second direction X, the first connection layer 121b and the second connection layer 121c are both located in the same layer as the first metal layer, and the first connection layer 121b and the second connection layer 121c are respectively located at two ends of the first metal wire, the first sub-metal wire 121a closest to the first connection layer 121b is not connected to the first connection layer 121b, and the first sub-metal wire 121a closest to the second connection layer 121c is not connected to the second connection layer 121c; the first connection layer 121b and one of the metal blocks 122b in the second metal layer 122 are staggered in projection in a direction perpendicular to the surface of the substrate 10, and the second connection layer 121c and another metal block 122b in the second metal layer 122 overlap in projection in a direction perpendicular to the surface of the substrate 10.

[0061] Preferably, the projections of the first connection layer 121b and the second connection layer 121c in the direction perpendicular to the surface of the substrate 10 are staggered with the projections of the metal block 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10, so that the overlapping area between the projections of the first connection layer 121b and the second connection layer 121c in the direction perpendicular to the surface of the substrate 10 and the projections of the metal block 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10 (that is, the facing area between the first connection layer 121b and the second connection layer 121c and the metal block 122b in the second metal layer 122, respectively) is significantly reduced, thereby significantly reducing the parasitic capacitance formed by the first connection layer 121b, the metal block 122b and the interlayer dielectric layer 11 therebetween, and the parasitic capacitance formed by the second connection layer 121c, the metal block 122b and the interlayer dielectric layer 11 therebetween, thereby further significantly reducing the parasitic capacitance of the semiconductor device. In other embodiments, the projections of the first connection layer 121b and the second connection layer 121c in a direction perpendicular to the surface of the substrate 10 may overlap with the projections of the metal block 122b in the second metal layer 122 in a direction perpendicular to the surface of the substrate 10 .

[0062] In one embodiment, the semiconductor device further includes a dummy gate 15, and the dummy gate 15 is located on both sides of the gate structure 14. The dummy gate 15 does not need to be electrically connected to the metal layer, that is, the dummy gate 15 is not electrically led out. The dummy gate 15 is used for optical proximity correction during exposure, so that the pattern of the formed gate structure 14 is not distorted; and in the process of flattening the device surface using a chemical mechanical polishing process, the dummy gate 15 can also be used to reduce the impact of the process itself on the gate structure 14.

[0063] The metal interconnect structure further includes a contact plug 132 , and the first metal layer is electrically connected to the source region or the drain region through the contact plug 132 .

[0064] The active region may also be formed with a body contact region (not shown).

[0065] by Figure 1 Taking the structure shown as an example, the gate structure 14 is an H-type structure, the "—" part of the H-type structure extends in the first direction Y, the projection of the "—" part of the H-type structure in the direction perpendicular to the surface of the substrate 10 is located between the projections of adjacent first metal lines in the direction perpendicular to the surface of the substrate 10 or between the projections of adjacent second metal lines in the direction perpendicular to the surface of the substrate 10, the "|" part of the H-type structure extends in the second direction X, one end of multiple "—" parts of the H-type structure extends from the active area to the shallow trench isolation structure 101, both ends of one of the "|" parts of the H-type structure extend from the active area to the shallow trench isolation structure 101, and another "|" part of the H-type structure is located on the shallow trench isolation structure 101; the source region and the drain region are respectively formed in the "—" of the H-type structure. The body contact region is formed in the active region on both sides of the “|” portion of the H-type structure away from the “—” portion of the H-type structure; the first connection layer 121b and one of the metal blocks 122b are located above the shallow trench isolation structure 101, the second connection layer 121c is located above the body contact region, and another metal block 122b extends from above the body contact region to above the shallow trench isolation structure 101; the first sub-metal line 121a in the first metal line is electrically connected to the source region and the drain region through the contact plug 132, the first connection layer 121b is electrically connected to the gate structure 14 (the “|” portion of the H-type structure) extending to the shallow trench isolation structure 101 through the contact plug 132, and the second connection layer 121c is electrically connected to the body contact region through the contact plug 132. In other embodiments, the gate structure 14 can be a T-type structure.

[0066] Preferably, each section of the sub-metal line in the first metal layer is electrically connected to the source region or the drain region through at least two contact plugs 132 to improve the effectiveness of the connection. For example, if one of the contact plugs 132 is disconnected or fails, the other contact plugs 132 can still keep the circuit connected to avoid disconnection of the entire circuit.

[0067] Preferably, the sub-metal lines in the metal lines of adjacent layers are electrically connected through at least two through-hole plugs 131 to improve the effectiveness of the connection. For example, if a first sub-metal line in the first metal layer is electrically connected to a second sub-metal line in the second metal layer 122 through at least two through-hole plugs 131, if one of the through-hole plugs 131 is disconnected or fails, the other through-hole plugs 131 can still keep the circuit connected, avoiding the entire circuit from being disconnected.

[0068] In addition, the semiconductor device also includes: a conductive interconnect structure (not shown), which is electrically connected to the metal interconnect structure, the first connection layer 121b and the second connection layer 121c, respectively, and the conductive interconnect structure is used to electrically lead out the metal interconnect structure, the first connection layer 121b and the second connection layer 121c, respectively, and then respectively correspond to electrically lead out the source region, the drain region, the gate structure 14 and the body contact region.

[0069] In summary, the semiconductor device provided by the present invention comprises: a substrate; an interlayer dielectric layer formed on the substrate; a metal interconnection structure formed in the interlayer dielectric layer, the metal interconnection structure comprising two metal layers and a through-hole plug, each metal layer comprising at least one metal wire, each metal wire comprising multiple segments of sub-metal wires, the sub-metal wires in the metal wires of adjacent layers are staggered, and the sub-metal wires in the metal wires of adjacent layers are electrically connected through the through-hole plugs. The semiconductor device of the present invention enables the parasitic capacitance of the semiconductor device to be significantly reduced.

[0070] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 4 , Figure 4 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein the method for manufacturing a semiconductor device comprises:

[0071] Step S1, providing a substrate;

[0072] Step S2, forming an interlayer dielectric layer and a metal interconnection structure, wherein the interlayer dielectric layer is formed on the substrate, and the metal interconnection structure is formed in the interlayer dielectric layer; the metal interconnection structure includes two metal layers and a through-hole plug, each metal layer includes at least one metal wire, each metal wire includes a plurality of sub-metal wires, the sub-metal wires in the metal wires of adjacent layers are staggered, and the sub-metal wires in the metal wires of adjacent layers are electrically connected through the through-hole plug.

[0073] See below Figure 1 to Figure 3 The method for manufacturing the semiconductor device provided in this embodiment is described in more detail. Figure 1 The shallow trench isolation structure 101 and the interlayer dielectric layer 11 are not shown.

[0074] According to step S1, a substrate 10 is provided.

[0075] The substrate 10 may be a single-layer structure, or may include a multi-layer structure composed of the same or different materials. The substrate 10 may be made of semiconductor materials such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors, or may include a layered substrate such as Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator, or may include other materials other than semiconductor materials, which is not limited in the present application.

[0076] According to step S2, an interlayer dielectric layer 11 and a metal interconnection structure are formed, wherein the interlayer dielectric layer 11 is formed on the substrate 10, and the metal interconnection structure is formed in the interlayer dielectric layer 11; the metal interconnection structure includes two metal layers (i.e., a first metal layer and a second metal layer 122) and a through-hole plug 131, wherein each metal layer includes at least one metal wire, and each metal wire includes a plurality of sub-metal wires. In two adjacent metal layers, the sub-metal wires in the metal wires of adjacent layers are staggered, and the sub-metal wires in the metal wires of adjacent layers are electrically connected through the through-hole plug 131.

[0077] The staggered arrangement of the sub-metal wires in the metal wires of adjacent layers means that the sub-metal wires in the metal wires of adjacent layers are staggered between their projections in a direction perpendicular to the surface of the substrate 10, such as Figure 2a As shown, in this direction, the first sub-metal line 121a in the first metal layer and the second sub-metal line 122a in the second metal layer are staggered and electrically connected through the via plug 131. The interlayer dielectric layer 11 may include multiple stacked insulating layers.

[0078] In one embodiment, a first insulating layer may be deposited first, and after the first insulating layer is deposited, a metal material may be deposited on the first insulating layer and the first metal layer may be etched to form the first metal layer; then, a second insulating layer may be deposited on the first insulating layer and the first metal layer, and a through hole and a groove may be formed by etching the second insulating layer, wherein the top surface of the first metal layer is exposed at the bottom of the through hole, the groove is located at the top of the through hole, and metal material is filled into the through hole and the groove, the metal material in the through hole serves as the through hole plug 131, and the metal material in the groove serves as the second metal layer, thereby forming the interlayer dielectric layer 11 and the metal interconnect structure.

[0079] In two adjacent metal layers, the projections of the sub-metal wires in the metal wires in the adjacent layers in a direction perpendicular to the surface of the substrate 10 only overlap at their ends, and the projections of the areas other than the ends of the sub-metal wires in the metal wires in the adjacent layers in a direction perpendicular to the surface of the substrate 10 do not overlap, and the through-hole plugs 131 are located between the ends of the sub-metal wires in the metal wires in the adjacent layers, and the segments of the sub-metal wires in the metal wires in the adjacent layers are alternately connected in sequence through the through-hole plugs 131 to achieve electrical connection between the metal wires in the adjacent layers.

[0080] Since the sub-metal wires in the metal wires of adjacent layers are staggered between their projections in a direction perpendicular to the surface of the substrate 10, the overlapping area between the projections of the metal wires of adjacent layers in a direction perpendicular to the surface of the substrate 10 is significantly reduced, thereby significantly reducing the overlapping area between the projections of the metal layers of adjacent layers in a direction perpendicular to the surface of the substrate 10 (i.e., the facing area of ​​the metal layers of adjacent layers), thereby significantly reducing the parasitic capacitance formed by the metal layers of adjacent layers and the interlayer dielectric layer 11 therebetween, i.e., significantly reducing the parasitic capacitance of the semiconductor device.

[0081] In one embodiment, each metal layer includes at least two metal wires. Preferably, in each metal layer, the sub-metal wires in two adjacent metal wires are staggered. The staggered arrangement of the sub-metal wires in two adjacent metal wires refers to staggered arrangement in a direction perpendicular to the extension direction of the metal wires, such as Figure 1 As shown, in the same metal layer, the first sub-metal wire 121a in one metal wire is staggered with the first sub-metal wire 121a in an adjacent metal wire. In each metal layer, the ends of the sub-metal wires in two adjacent metal wires may overlap or not overlap in a direction perpendicular to the extension of the metal wires, and the areas other than the ends of the sub-metal wires in two adjacent metal wires do not overlap in a direction perpendicular to the extension of the metal wires.

[0082] Since in each metal layer, the sub-metal wires in two adjacent metal wires are staggered in a direction perpendicular to the extension direction of the metal wires, the overlapping area of ​​the two adjacent metal wires in each metal layer in the direction perpendicular to the extension direction of the metal wires (i.e., the facing area of ​​the two adjacent metal wires) is significantly reduced, thereby significantly reducing the parasitic capacitance formed by the two adjacent metal wires in each metal layer and the interlayer dielectric layer 11 therebetween, thereby further significantly reducing the parasitic capacitance of the semiconductor device.

[0083] In one embodiment, the second metal layer 122 further includes a metal block 122b, the metal line can extend in a first direction, the metal block 122b can extend in a second direction, the metal blocks 122b can be located at both ends of the metal line, one end of the metal line in the second metal layer 122 is connected to one of the metal blocks 122b, and the other end of the metal line in the second metal layer 122 is not connected to another of the metal blocks 122b. The first direction is different from the second direction; in one embodiment, the first direction is perpendicular to the second direction.

[0084] The two metal blocks 122 b are arranged opposite to each other, and all the metal wires are arranged in sequence and spaced apart along the second direction between the two metal blocks 122 b.

[0085] In one embodiment, the second metal layer 122 includes two relatively staggered comb-shaped structures, each of the comb-shaped structures includes a plurality of comb teeth arranged in sequence and a comb back located at the same end of each comb tooth, the comb backs of the two comb-shaped structures are parallel to each other, and the comb teeth are perpendicular to the comb backs, the comb teeth and the comb backs can be connected, the metal wire serves as the comb teeth, and the metal block 122b serves as the comb back.

[0086] like Figure 1 to Figure 3As shown, the metal interconnect structure includes a first metal layer and a second metal layer 122, the second metal layer 122 is located above the first metal layer; the first metal layer includes a plurality of first metal wires extending in a first direction Y, each of the first metal wires is arranged at intervals in a second direction X, each of the first metal wires includes a plurality of first sub-metal wires 121a, and the first sub-metal wires 121a in two adjacent first metal wires are arranged staggered in the second direction X; the second metal layer 122 includes two relatively staggered comb-shaped structures, each of the comb-shaped structures includes a plurality of second metal wires extending in the first direction Y and a metal block 122b extending in the second direction X, each of the second metal wires includes A plurality of segments of second sub-metal wires 122a, the second sub-metal wire 122a closest to the metal block 122b in each of the comb-shaped structures is connected to the metal block 122b, the second metal wires in the two comb-shaped structures are interlaced and arranged in a staggered manner, the second sub-metal wires 122a in two adjacent second metal wires are staggered in the second direction X; the projections of the first sub-metal wires 121a in the first metal wires and the second sub-metal wires 122a in the second metal wires in a direction perpendicular to the surface of the substrate 10 are staggered, and each segment of the first sub-metal wire 121a and each segment of the second sub-metal wire 122a are alternately electrically connected in sequence through the through-hole plug 131. The first direction Y is perpendicular to the second direction X.

[0087] Before forming the interlayer dielectric layer 11 and the metal interconnect structure, the method for manufacturing the semiconductor device further includes:

[0088] Forming a shallow trench isolation structure 101 in the substrate 10, wherein the shallow trench isolation structure 101 defines an active area;

[0089] A gate structure 14 is formed on the active region; in one embodiment, the gate structure 14 may also extend from the active region to the shallow trench isolation structure 101;

[0090] A source region (not shown), a drain region (not shown) and a body contact region (not shown) are formed in the active region.

[0091] Each of the metal blocks 122 b in the second metal layer 122 is electrically connected to the source region or the drain region, that is, each of the comb-shaped structures is electrically connected to the source region or the drain region.

[0092] like Figure 1 and Figure 2bAs shown, the manufacturing method of the semiconductor device also includes: forming a first connection layer 121b and a second connection layer 121c extending in a second direction X, the first connection layer 121b and the second connection layer 121c are both formed simultaneously with the first metal layer, the first connection layer 121b and the second connection layer 121c are both located at the same layer as the first metal layer, and the first connection layer 121b and the second connection layer 121c are respectively located at two ends of the first metal line, the first sub-metal line 121a closest to the first connection layer 121b is not connected to the first connection layer 121b, and the first sub-metal line 121a closest to the second connection layer 121c is not connected to the second connection layer 121c; the projections of the first connection layer 121b and one of the metal blocks 122b in the second metal layer 122 in a direction perpendicular to the surface of the substrate 10 are staggered, and the projections of the second connection layer 121c and another of the metal blocks 122b in the second metal layer 122 in a direction perpendicular to the surface of the substrate 10 overlap.

[0093] Preferably, the projections of the first connection layer 121b and the second connection layer 121c in the direction perpendicular to the surface of the substrate 10 are staggered with the projections of the metal block 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10, so that the overlapping area between the projections of the first connection layer 121b and the second connection layer 121c in the direction perpendicular to the surface of the substrate 10 and the projections of the metal block 122b in the second metal layer 122 in the direction perpendicular to the surface of the substrate 10 (that is, the facing area between the first connection layer 121b and the second connection layer 121c and the metal block 122b in the second metal layer 122, respectively) is significantly reduced, thereby significantly reducing the parasitic capacitance formed by the first connection layer 121b, the metal block 122b and the interlayer dielectric layer 11 therebetween, and the parasitic capacitance formed by the second connection layer 121c, the metal block 122b and the interlayer dielectric layer 11 therebetween, thereby further significantly reducing the parasitic capacitance of the semiconductor device. In other embodiments, the projections of the first connection layer 121b and the second connection layer 121c in a direction perpendicular to the surface of the substrate 10 may overlap with the projections of the metal block 122b in the second metal layer 122 in a direction perpendicular to the surface of the substrate 10 .

[0094] In one embodiment, the method for manufacturing the semiconductor device further includes: forming a virtual gate 15 on both sides of the gate structure 14. The virtual gate 15 can be formed simultaneously with the gate structure 14. The virtual gate 15 does not need to be electrically connected to the metal layer, that is, the virtual gate 15 is not electrically led out. The virtual gate 15 is used for optical proximity correction during exposure so that the pattern of the formed gate structure 14 is not distorted; and in the process of flattening the device surface using a chemical mechanical polishing process, the virtual gate 15 can also be used to reduce the impact of the process itself on the gate structure 14.

[0095] The metal interconnect structure further includes a contact plug 132 , and the first metal layer is electrically connected to the source region or the drain region through the contact plug 132 .

[0096] After forming the bottommost insulating layer and before forming the first insulating layer, the bottommost insulating layer may be etched to form a contact hole, and a metal material may be filled into the contact hole to form the contact plug 132 .

[0097] by Figure 1Taking the structure shown as an example, the gate structure 14 is an H-type structure, the "—" part of the H-type structure extends in the first direction Y, the projection of the "—" part of the H-type structure in the direction perpendicular to the surface of the substrate 10 is located between the projections of adjacent first metal lines in the direction perpendicular to the surface of the substrate 10 or between the projections of adjacent second metal lines in the direction perpendicular to the surface of the substrate 10, the "|" part of the H-type structure extends in the second direction X, one end of multiple "—" parts of the H-type structure extends from the active area to the shallow trench isolation structure 101, both ends of one of the "|" parts of the H-type structure extend from the active area to the shallow trench isolation structure 101, and another "|" part of the H-type structure is located on the shallow trench isolation structure 101; the source region and the drain region are respectively formed in the "—" of the H-type structure. The body contact region is formed in the active region on both sides of the “|” portion of the H-type structure away from the “—” portion of the H-type structure; the first connection layer 121b and one of the metal blocks 122b are located above the shallow trench isolation structure 101, the second connection layer 121c is located above the body contact region, and another metal block 122b extends from above the body contact region to above the shallow trench isolation structure 101; the first sub-metal line 121a in the first metal line is electrically connected to the source region and the drain region through the contact plug 132, the first connection layer 121b is electrically connected to the gate structure 14 (the “|” portion of the H-type structure) extending to the shallow trench isolation structure 101 through the contact plug 132, and the second connection layer 121c is electrically connected to the body contact region through the contact plug 132. In other embodiments, the gate structure 14 can be a T-type structure.

[0098] Preferably, each section of the sub-metal line in the first metal layer is electrically connected to the source region or the drain region through at least two contact plugs 132 to improve the effectiveness of the connection. For example, if one of the contact plugs 132 is disconnected or fails, the other contact plugs 132 can still keep the circuit connected to avoid disconnection of the entire circuit.

[0099] Preferably, the sub-metal lines in the metal lines of adjacent layers are electrically connected through at least two through-hole plugs 131 to improve the effectiveness of the connection. For example, if a first sub-metal line in the first metal layer is electrically connected to a second sub-metal line in the second metal layer 122 through at least two through-hole plugs 131, if one of the through-hole plugs 131 is disconnected or fails, the other through-hole plugs 131 can still keep the circuit connected, avoiding the entire circuit from being disconnected.

[0100] In addition, the manufacturing method of the semiconductor device also includes: forming a conductive interconnect structure (not shown), wherein the conductive interconnect structure is electrically connected to the metal interconnect structure, the first connection layer 121b and the second connection layer 121c, respectively, and the conductive interconnect structure is used to electrically lead out the metal interconnect structure, the first connection layer 121b and the second connection layer 121c, respectively, and then respectively correspond to electrically lead out the source region, the drain region, the gate structure 14 and the body contact region.

[0101] In summary, the manufacturing method of the semiconductor device provided by the present invention includes: providing a substrate; forming an interlayer dielectric layer and a metal interconnection structure, wherein the interlayer dielectric layer is formed on the substrate, and the metal interconnection structure is formed in the interlayer dielectric layer; the metal interconnection structure includes two metal layers and a through-hole plug, each metal layer includes at least one metal wire, each metal wire includes multiple sub-metal wires, the sub-metal wires in the metal wires of adjacent layers are staggered, and the sub-metal wires in the metal wires of adjacent layers are electrically connected through the through-hole plug. The manufacturing method of the semiconductor device of the present invention enables the parasitic capacitance of the semiconductor device to be significantly reduced.

[0102] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; An interlayer dielectric layer formed on the substrate; A metal interconnect structure is formed in the interlayer dielectric layer, the metal interconnect structure includes two metal layers and through-hole plugs, each metal layer includes at least one metal wire, each metal wire includes multiple segments of sub-metal wires, the sub-metal wires in the metal wires of adjacent layers are staggered, and the sub-metal wires in the metal wires of adjacent layers are electrically connected through the through-hole plugs.

2. The semiconductor device according to claim 1, wherein Each of the metal layers includes at least two of the metal wires; in each of the metal layers, the sub-metal wires in two adjacent metal wires are arranged in a staggered manner.

3. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: A shallow trench isolation structure is formed in the substrate, wherein the shallow trench isolation structure defines an active area; A gate structure formed on the active area; A source region and a drain region formed in the active region; The metal interconnect structure further includes a contact plug, and the bottom metal layer is electrically connected to the source region or the drain region through the contact plug.

4. The semiconductor device according to claim 1, wherein The sub-metal lines in the metal lines of adjacent layers are electrically connected via at least two through-hole plugs.

5. The semiconductor device according to claim 3, wherein: The semiconductor device further comprises: a virtual gate, wherein the virtual gate is located at two sides of the gate structure.

6. The semiconductor device according to claim 3, wherein: The metal interconnect structure includes a first metal layer and a second metal layer, wherein the second metal layer also includes a metal block, the metal line extends in a first direction, the metal block extends in a second direction, the metal blocks are located at both ends of the metal line, and each of the metal blocks is connected to the source region or the drain region.

7. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming an interlayer dielectric layer and a metal interconnect structure, wherein the interlayer dielectric layer is formed on the substrate, and the metal interconnect structure is formed in the interlayer dielectric layer; The metal interconnect structure includes two metal layers and through-hole plugs, each of the metal layers includes at least one metal wire, each of the metal wires includes multiple segments of sub-metal wires, the sub-metal wires in the metal wires of adjacent layers are staggered, and the sub-metal wires in the metal wires of adjacent layers are electrically connected through the through-hole plugs.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: Each of the metal layers includes at least two of the metal wires; in each of the metal layers, the sub-metal wires in two adjacent metal wires are arranged in a staggered manner.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: Before forming the interlayer dielectric layer and the metal interconnect structure, the method for manufacturing the semiconductor device further includes: forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure defines an active area; forming a gate structure on the active area; forming a source region and a drain region in the active region; The metal interconnect structure further includes a contact plug, and the bottom metal layer is electrically connected to the source region or the drain region through the contact plug.

10. The method for manufacturing a semiconductor device according to claim 7, wherein: The sub-metal lines in the metal lines of adjacent layers are electrically connected via at least two through-hole plugs.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: The metal interconnect structure includes a first metal layer and a second metal layer, wherein the second metal layer also includes a metal block, the metal line extends in a first direction, the metal block extends in a second direction, the metal blocks are located at both ends of the metal line, and each of the metal blocks is connected to the source region or the drain region.

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