A high uniformity two-dimensional VCSEL laser and its preparation method

Abstract

The present invention discloses a high-uniformity two-dimensional VCSEL laser and a preparation method thereof. The laser comprises a two-dimensional array of multiple rows and columns composed of a plurality of light-emitting units; each light-emitting unit is sequentially formed with an insulating substrate layer, an N-type conductive layer, a two-dimensional electron gas layer, an etching cutoff layer, an N-DBR layer, an extended cavity, an active area, a P-DBR layer, and a P-contact layer from bottom to top; a plurality of upper electrodes are formed on the P-contact layer in each light-emitting unit, and a plurality of dielectric film layers are formed in the area where the upper electrode is not formed on the P-contact layer, and the dielectric film layer extends downward to the two-dimensional electron gas layer; a P-plating layer is formed on the upper surface of the upper electrode and the dielectric film layer, and an N-plating layer is formed between the lower parts of each dielectric film layer. A high-uniformity two-dimensional VCSEL laser and a preparation method thereof in the present invention overcome the problem of epitaxial layer stress accumulation caused by the thick conductive layer of the coplanar electrode addressing VCSEL on the one hand, and on the other hand, improves the uniformity of electron lateral transport on the n-plane and the uniformity of luminescence in different light-emitting areas.

Description

Technical Field

[0001] The present invention relates to the field of lasers, and in particular to a high-uniformity two-dimensional VCSEL laser and a preparation method thereof. Background Art

[0002] Vertical Cavity Surface Emitting Laser (VCSEL) has the advantages of good beam quality, low threshold current, high frequency regulation, easy two-dimensional array integration and low manufacturing cost. In recent years, with the large-scale application of VCSEL in LiDAR, 3D sensing and other fields, VCSEL has attracted more and more attention.

[0003] Two-dimensional addressable VCSEL has the advantage of zoned driving and is an ideal light source for solid-state lidar. Commonly used two-dimensional addressable VCSELs mostly use a coplanar electrode process, which usually requires the growth of a thick conductive layer in the substrate or reflective cavity for lateral electrical transport of the bottom electrode. On the one hand, the thick conductive layer will increase the thickness of the epitaxial layer, causing stress accumulation and making it difficult to grow high-quality epitaxial growth; on the other hand, the growth of a thick conductive layer usually has a high doping concentration and there is an upper limit to the doping concentration. A thick conductive layer alone cannot achieve good lateral electrical transport, which affects the uniformity of light emission in different light-emitting intervals of the two-dimensional array.

[0004] In addition, the N-side metal electrode solution can use the high electron mobility of the metal electrode to reduce the lateral resistance of the device and improve the uniformity of electrical injection and luminescence in different light-emitting intervals. However, the production of the N-side contact electrode N-Contact needs to be in a relatively flat area, and the width of the channel between N-Mesa is relatively narrow. If two photolithography processes are used to etch the flat N-contact contact platform and peel off the N-contact electrode, there will be anomalies in the alignment of the two photolithography processes in the deep trench, resulting in a significant increase in the width of the channel between N-Mesa and a reduction in the fill rate and power density of the two-dimensional addressing VCSEL. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a high-uniformity two-dimensional VCSEL laser and a preparation method thereof. On the one hand, a coplanar partitioned electrode is adopted in combination with a two-dimensional electron gas layer with high electron mobility, so as to solve the problem of epitaxial layer stress accumulation faced by the thick conductive layer of the existing addressable device; on the other hand, a primary photolithography mask is adopted to wet-etch the remaining N-DBR layer and the etching cut-off layer to form a positive trapezoidal etching cross section, evaporate the N electrode, peel off to form the N-Contact layer, and electroplate a thick gold layer, so as to overcome the alignment deviation problem of the traditional secondary photolithography and solve the problem of decreased carrier transport efficiency of the thick epitaxial conductive layer over a long transport distance; in addition, the deep etching groove is filled and leveled by multiple leveling, so as to realize the isolation of the NP electrode and reduce the leakage current of different light-emitting intervals of the two-dimensional array.

[0006] According to one aspect of the present invention, a high-uniformity two-dimensional VCSEL laser and a method for preparing the same are provided, comprising:

[0007] A plurality of light-emitting units, each of the light-emitting units forming a two-dimensional array of multiple rows and columns;

[0008] Each of the light-emitting units is sequentially formed with an insulating substrate layer, an N-type conductive layer, a two-dimensional electron gas layer, an etching cutoff layer, an N-DBR layer, an extended cavity, an active area, a P-DBR layer, and a P-contact layer from bottom to top;

[0009] A plurality of upper electrodes are formed on the P-contact layer in each of the light-emitting units, and a plurality of dielectric film layers are formed on the P-contact layer in an area where the upper electrodes are not formed, and the dielectric film layers extend downward to the two-dimensional electron gas layer, and the two-dimensional electron gas layer is a GaAs system material layer and has high electron mobility;

[0010] The lower part of each of the dielectric film layers is cut off by an N-contact layer, and the N-contact layer is formed on the upper surface of the two-dimensional electron gas layer;

[0011] A P-plating layer is formed on the upper surface of the upper electrode and the dielectric film layer, an N-plating layer is formed between the lower parts of the dielectric film layers, and a filling dielectric layer is arranged between the P-plating layer and the N-plating layer.

[0012] In some embodiments, in a two-dimensional array, the P-plating layers of the light-emitting units in each row are connected to form a P-strip electrode, and the N-plating layers of the light-emitting units in each column are connected to form an N-strip electrode. The advantage is that the strip distribution of P-side electrical injection can be achieved under the action of each P-strip electrode, and the strip distribution of N-side electrical injection can be achieved under the action of each N-strip electrode.

[0013] In some implementations, a P-side isolation channel is formed between each row, and an N-side isolation channel is formed between each column. This is beneficial in that NP electrode isolation is achieved.

[0014] In some embodiments, each P-side isolation channel and each N-side isolation channel are filled and leveled by multiple filling and leveling to achieve deep etching grooves. This is beneficial in that the light emission uniformity of different light emission intervals of the two-dimensional array is improved.

[0015] In some embodiments, in a two-dimensional array, a P-pad is disposed at the end of each row and an N-pad is disposed at the end of each column. The benefit is that each P-pad and each N-pad are disposed to mark each row and each column, respectively.

[0016] According to one aspect of the present invention, there is provided a method for preparing the above-mentioned high uniformity two-dimensional VCSEL laser, comprising the following steps:

[0017] S1: growing a highly doped N-type conductive layer, a two-dimensional electron gas layer, an etching cutoff layer, an N-DBR, an extended cavity layer, an active layer, a P-DBR and a P-contact layer in sequence on an insulating substrate layer;

[0018] S2: forming an upper electrode on the P-contact layer;

[0019] S3: forming a silicon nitride mask layer above the P-contact layer and the upper electrode;

[0020] S4: using the silicon nitride mask layer as a mask to perform etching to the extended cavity to form a p-Mesa structure;

[0021] S5: performing oxidation treatment to form oxidation pores;

[0022] S6: forming an N-Mesa structure by photolithography, dry etching and solution etching, and stopping the etching inside the last three pairs of N-DBRs;

[0023] S7: using the photoresist as a mask, wet-etching the remaining N-DBR layer, etching the cut-off layer, forming a positive trapezoidal etching cross section between the photoresist and the two-dimensional electron gas layer, and then evaporating an N electrode and forming an N-contact layer on the two-dimensional electron gas layer;

[0024] S8: using the photoresist as a mask, etching the N-electrode isolation channel and etching to the insulating substrate layer;

[0025] S9: evaporating a dielectric layer, removing the dielectric film layer on the N-contact layer by photolithography and etching, and forming an N-electrode contact hole;

[0026] S10: connecting the N electrode to the negative electrode and performing electroplating to form N electroplated gold in the trench, wherein the highest point of the electroplated gold does not exceed the top of the extended cavity;

[0027] S11: performing fill-leveling photolithography on the chip for multiple times to form a thick fill-leveling layer in each groove;

[0028] S12: forming a P-side contact through hole by photolithography and dry etching of the dielectric film layer;

[0029] S13: forming an electroplating seed gold layer, a P-side isolation channel and a contact metal layer;

[0030] S14: The chip is annealed at high temperature to form an ohmic contact, completing the preparation of a high-uniformity two-dimensional VCSEL laser.

[0031] In some embodiments, in step S5, the Mesa sidewall is placed in a wet oxidation furnace for a short time, and then water vapor is introduced into the chamber, the temperature is raised to the oxidation temperature, and oxidation is performed for a certain time. The benefit is that a specific method for oxidizing the Mesa sidewall is described.

[0032] In some embodiments, in step S7, the wet etching mask and the stripping use the same layer of photoresist, and the isotropic wet etching forms a positive trapezoidal etching cross section, and the distance between the bottom of the trapezoid of the positive trapezoidal etching cross section and the edge of the photoresist is greater than 0.5 um. The benefit is that it describes the relevant position of the positive trapezoidal etching cross section formed between the photoresist and the two-dimensional electron gas layer.

[0033] In some embodiments, in step S10, the thickness of the electroplated gold is controlled by adjusting the electroplating time. It is beneficial in that a specific method for controlling the thickness of the electroplated gold so that its highest point does not exceed the top of the elongated cavity is described.

[0034] In some embodiments, in step S12, a gold electroplating seed layer is formed by depositing a metal film on the surface of the wafer, a P-side isolation channel is formed by photolithography and wet etching, and a strip-shaped partition of the P-side light-emitting area is realized, and a contact metal layer is formed by photolithography and electroplating. The benefit is that specific methods for forming the gold electroplating seed layer, the P-side isolation channel, and the contact metal layer are described respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A top view of a high uniformity two-dimensional VCSEL laser according to an embodiment of the present invention;

[0036] Figure 2 for Figure 1 A cross-sectional view of a high uniformity two-dimensional VCSEL laser in the AA direction is shown;

[0037] Figure 3 for Figure 2 A partially enlarged cross-sectional view of a high uniformity two-dimensional VCSEL laser is shown;

[0038] Figure 4 for Figure 1 A flow chart of a method for preparing a high uniformity two-dimensional VCSEL laser is shown.

[0039] In the figure: light-emitting unit 1, insulating substrate layer 2, N-type conductive layer 3, two-dimensional electron gas layer 4, etching cutoff layer 5, N-DBR layer 6, extended cavity 7, active area 8, P-DBR layer 9, P-contact layer 10, upper electrode 11, dielectric film layer 12, N-contact layer 13, P-plating layer 14, N-plating layer 15, filling dielectric layer 16, P-side isolation channel 17, N-side isolation channel 18, P-pad19, N-pad20. DETAILED DESCRIPTION

[0040] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0041] like Figure 1-3 As shown, the present invention also provides a high uniformity two-dimensional VCSEL laser, including a two-dimensional array of multiple rows and columns composed of multiple light-emitting units 1 (a 4*5 two-dimensional array is taken as an example in the figure).

[0042] Each light-emitting unit 1 is formed from bottom to top with an insulating substrate layer 2, an N-type conductive layer 3, a two-dimensional electron gas layer 4, an etching cutoff layer 5, an N-DBR layer 6, an extended cavity 7, an active region 8, a P-DBR layer 9, and a P-contact layer 10. Among them, the two-dimensional electron gas layer 4 is a GaAs system material layer with high electron mobility.

[0043] In each light-emitting unit 1, a plurality of upper electrodes 11 are formed on the P-contact layer 10, and the plurality of upper electrodes 11 include a positive electrode and a negative electrode, that is, the positive electrode and the negative electrode are both on the same surface, and combined with a two-dimensional electron gas layer 4 with high electron mobility, the problem of epitaxial layer stress accumulation faced by the thick conductive layer of the existing addressable device is solved, and the quality of epitaxial growth is improved.

[0044] In each light-emitting unit 1, a plurality of dielectric film layers 12 are formed in the region where the upper electrode 11 is not formed on the P-contact layer 10, and the dielectric film layers 12 extend downward to the two-dimensional electron gas layer 4 and cut off the etching stop layer 5. The lower portion of each dielectric film layer 12 is cut off by an N-contact layer 13, and the N-contact layer is formed on the upper surface of the two-dimensional electron gas layer 4.

[0045] A P-plating layer 14 is formed on the upper surface of the upper electrode 11 and the dielectric film layer 12, and an N-plating layer 15 is formed between the lower parts of the dielectric film layers 12, and a filling dielectric layer 16 is provided between the P-plating layer 14 and the N-plating layer 15. Among them, by providing an N-contact layer 13 on the surface of the two-dimensional electron gas layer 4, and combining thick plating layers such as the P-plating layer 14 and the N-plating layer 15, the problem of decreased carrier transport efficiency over a long transport distance of a thick epitaxial conductive layer is overcome, and better lateral electrical transport can be achieved.

[0046] like Figure 1 As shown, the P-plating layers of the multiple light-emitting units 1 in each row are connected to form a P-line electrode, and the N-plating layers of the multiple light-emitting units 1 in each column are connected to form an N-line electrode. Thus, under the action of each P-line electrode, a strip distribution of electric injection on the P surface is realized, and at the same time, under the action of each N-line electrode, a strip distribution of electric injection on the N surface is realized. When both the P surface and the N surface are electrically injected, the overlapping area of ​​the P surface and the N surface is lit.

[0047] A P-side isolation channel 17 is formed between each row, and an N-side isolation channel 18 is formed between each column. Each P-side isolation channel 17 and each N-side isolation channel 18 is filled and leveled multiple times during processing to achieve deep etching groove filling, thereby achieving NP electrode isolation and improving the luminous uniformity of different luminous intervals of the two-dimensional array.

[0048] In addition, a P-pad 19 is disposed at the end of each row in the two-dimensional array, and an N-pad 20 is disposed at the end of each column. Each P-pad 10 and each N-pad 20 is used to mark each row and column, respectively.

[0049] like Figure 4 As shown, the present invention also provides a method for preparing the above-mentioned high uniformity two-dimensional VCSEL laser, which includes the following main steps S1 to S14.

[0050] S1: A highly doped N-type conductive layer, a two-dimensional electron gas layer, an etching cutoff layer, an N-DBR, an extended cavity layer, an active layer, a P-DBR and a P-contact layer are sequentially grown on an insulating substrate layer.

[0051] Among them, the insulating substrate layer can choose a non-doped GaAs substrate, and the metal organic chemical vapor deposition process is used to grow the highly doped N-type conductive layer, the two-dimensional electron gas layer, the etching cutoff layer, the N-DBR, the extended cavity layer, the active layer, the P-DBR and the P-contact layer.

[0052] Preferably, the thickness of the highly doped conductive layer is 30 nm to 100 nm.

[0053] S2: forming an upper electrode on the P-contact layer.

[0054] The upper electrode is a metal ring, and the metal material used can be Ti, Pt or the like.

[0055] S3: forming a silicon nitride mask layer above the P-contact layer and the upper electrode.

[0056] Wherein, a silicon nitride mask layer is formed by depositing silicon nitride above the P-contact layer and the upper electrode, and the thickness of the silicon nitride mask layer is 50~1000 nm.

[0057] S4: Etching is performed using the silicon nitride mask layer as a mask until the extended cavity is reached to form a p-Mesa structure.

[0058] Among them, an etching process is adopted to perform etching using the silicon nitride mask layer as a mask until the cavity is extended and a p-Mesa structure is formed.

[0059] S5: performing oxidation treatment to form oxidation pores.

[0060] Specifically, the oxidation treatment method is to place the Mesa side wall into a wet oxidation furnace for a short period of time, then introduce water vapor into the chamber, raise the temperature to the oxidation temperature, and oxidize for a certain period of time.

[0061] S6: Form an N-Mesa structure through photolithography, dry etching and solution etching.

[0062] A photolithography mask layer is formed by photolithography. After photolithography, etching is performed using the photolithography mask layer as a mask to form an N-Mesa structure, and the etching stops within the last three pairs of the lower N-DBR.

[0063] S7: Using the photoresist as a mask, wet-etch the remaining N-DBR layer, etch the cut-off layer, form a positive trapezoidal etching cross section between the photoresist and the two-dimensional electron gas layer, and then evaporate the N electrode and form an N-contact layer on the two-dimensional electron gas layer.

[0064] The same photoresist layer is used for wet etching mask and stripping. When wet etching the cut-off layer, it stops on the two-dimensional electron gas layer. The isotropic wet etching forms a positive trapezoidal etching cross section. The bottom of the trapezoid of the positive trapezoidal etching cross section is more than 0.5 um away from the edge of the photoresist. In addition, after evaporating the N electrode and stripping, an N-contact layer is formed on the two-dimensional electron gas layer.

[0065] S8: Etching the N-electrode isolation channel to the insulating substrate layer.

[0066] Here, the N-electrode isolation track is etched using the photoresist as a mask, and then etched to the insulating substrate layer.

[0067] S9: removing the dielectric film layer on the N-contact layer to form an N-electrode contact hole.

[0068] Wherein, on the basis of the above processing steps, a dielectric layer is evaporated, and then the dielectric film layer on the N-contact layer is removed by photolithography and etching, and an N-electrode contact hole is formed.

[0069] S10: Forming N electroplated gold by electroplating.

[0070] The N electrode is connected to the negative electrode for electroplating, thereby forming N electroplated gold in the channel. The electroplating time is adjusted to control the thickness of the electroplated gold so that the highest point of the electroplated gold does not exceed the top of the extended cavity.

[0071] S11: Perform multiple fill-leveling photolithography on the chip.

[0072] Among them, after the chip undergoes multiple filling and leveling lithography, a thick filling layer will be formed in each groove.

[0073] S12: Etching to form a P-side contact through hole.

[0074] The P-side contact through hole can be formed by photolithography and dry etching of the dielectric film layer.

[0075] S13: forming an electroplating seed gold layer, a P-side isolation channel and a contact metal layer.

[0076] Among them, a plating seed gold layer can be formed by depositing a metal film on the surface of the wafer; a P-side isolation channel can be formed through photolithography and wet etching, and the strip-shaped partitioning of the P-side light-emitting area can be realized; and after photolithography and electroplating, a contact metal layer can be formed.

[0077] S14: The chip is annealed at high temperature to form an ohmic contact, completing the preparation of the two-dimensional addressing VCSEL.

[0078] The chip can be annealed at a high temperature of 200°C-300°C to form an ohmic contact.

[0079] The present invention provides a method for preparing a high uniformity two-dimensional VCSEL laser, which mainly has the following beneficial effects:

[0080] 1. By adopting coplanar partitioned electrodes, that is, the positive and negative electrodes are on the same surface, combined with the introduction of a two-dimensional electron gas layer with high electron mobility on the side of the n-type thick conductive layer close to the n-DBR, the problem of epitaxial layer stress accumulation faced by the thick conductive layer of existing addressable devices is solved, and the quality of epitaxial growth is improved;

[0081] 2. The n-contact layer is made on the surface of the two-dimensional electron gas layer through one-step photolithography. By controlling the cross-sectional morphology of the remaining DBR and the etching cut-off layer and the photoresist in the wet etching, the alignment anomaly problem of the two photolithography of the wet etching flat layer and the N-contact stripping in the traditional solution is solved. On this basis, the thick gold layer is electroplated to overcome the problem of decreased carrier transport efficiency over long transport distances in the thick epitaxial conductive layer, and better lateral electrical transport can be achieved;

[0082] 3. The deep etched grooves are filled and leveled by multiple leveling, the NP electrodes are isolated, the leakage current in different light-emitting intervals is reduced, and the light-emitting uniformity of different light-emitting intervals of the two-dimensional array is improved.

[0083] The above are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A high uniformity two-dimensional VCSEL laser, characterized in that: include A plurality of light-emitting units, each of the light-emitting units forming a two-dimensional array of multiple rows and columns; Each of the light-emitting units is sequentially formed with an insulating substrate layer, an N-type conductive layer, a two-dimensional electron gas layer, an etching cutoff layer, an N-DBR layer, an extended cavity, an active area, a P-DBR layer, and a P-contact layer from bottom to top; A plurality of upper electrodes are formed on the P-contact layer in each of the light-emitting units, and the positive electrode and the negative electrode are both on the same surface, and a plurality of dielectric film layers are formed on the P-contact layer in the region where the upper electrode is not formed, and the dielectric film layers extend downward to the two-dimensional electron gas layer, and the two-dimensional electron gas layer has high electron mobility; The lower part of each of the dielectric film layers is cut off by an N-contact layer, and the N-contact layer is formed on the upper surface of the two-dimensional electron gas layer; A P-plating layer is formed on the upper surface of the upper electrode and the dielectric film layer, an N-plating layer is formed between the lower parts of the dielectric film layers, and a filling dielectric layer is arranged between the P-plating layer and the N-plating layer.

2. A high uniformity two-dimensional VCSEL laser according to claim 1, characterized in that: In a two-dimensional array, the P-plating layers of the light-emitting units in each row are connected to form a P-strip electrode, and the N-plating layers of the light-emitting units in each column are connected to form an N-strip electrode.

3. A high uniformity two-dimensional VCSEL laser according to claim 2, characterized in that: A P-side isolation channel is formed between each row, and an N-side isolation channel is formed between each column.

4. A high uniformity two-dimensional VCSEL laser according to claim 3, characterized in that: Each P-side isolation channel and each N-side isolation channel is filled and leveled by multiple filling and leveling to achieve deep etching grooves.

5. A high uniformity two-dimensional VCSEL laser according to claim 2, characterized in that: In a two-dimensional array, a P-pad is disposed at the end of each row, and an N-pad is disposed at the end of each column.

6. A method for preparing a high uniformity two-dimensional VCSEL laser according to any one of claims 1 to 5, characterized in that: The following steps are included S1: growing a highly doped N-type conductive layer, a two-dimensional electron gas layer, an etching cutoff layer, an N-DBR, an extended cavity layer, an active layer, a P-DBR and a P-contact layer in sequence on an insulating substrate layer; S2: forming an upper electrode on the P-contact layer; S3: forming a silicon nitride mask layer above the P-contact layer and the upper electrode; S4: using the silicon nitride mask layer as a mask to perform etching to the extended cavity to form a p-Mesa structure; S5: performing oxidation treatment to form oxidation pores; S6: forming an N-Mesa structure by photolithography and dry etching, and the etching stops within the last three pairs of N-DBRs; S7: using the photoresist as a mask, wet-etching the remaining N-DBR layer and the etching stop layer to form a positive trapezoidal etching cross section between the photoresist and the two-dimensional electron gas layer, evaporating an N electrode, and forming an N-contact layer on the two-dimensional electron gas layer after stripping; S8: using the photoresist as a mask, etching the N-electrode isolation channel and etching to the insulating substrate layer; S9: evaporating a dielectric layer, removing the dielectric film layer on the N-contact layer by photolithography and etching, and forming an N-electrode contact hole; S10: connecting the N electrode to the negative electrode and performing electroplating to form N electroplated gold in the trench, wherein the highest point of the electroplated gold does not exceed the top of the extended cavity; S11: performing fill-leveling photolithography on the chip for multiple times to form a thick fill-leveling layer in each groove; S12: forming a P-side contact through hole by photolithography and dry etching of the dielectric film layer; S13: forming an electroplating seed gold layer, a P-side isolation channel and a contact metal layer; S14: The chip is annealed at high temperature to form an ohmic contact, completing the preparation of a high-uniformity two-dimensional VCSEL laser.

7. The method for preparing a high uniformity two-dimensional VCSEL laser according to claim 6, characterized in that: In step S5, the Mesa sidewall is placed in a wet oxidation furnace for a short time, and then water vapor is introduced into the chamber, the temperature is raised to the oxidation temperature, and oxidation is performed for a certain period of time.

8. The method for preparing a high uniformity two-dimensional VCSEL laser according to claim 6, characterized in that: In step S7, the same layer of photoresist is used for wet etching mask and stripping, and the isotropic wet etching forms a positive trapezoidal etching cross section, and the distance between the bottom of the trapezoid and the edge of the photoresist is greater than 0.5 um.

9. The method for preparing a high uniformity two-dimensional VCSEL laser according to claim 6, characterized in that: In step S10 , the thickness of the electroplated gold is controlled by adjusting the electroplating time.

10. The method for preparing a high uniformity two-dimensional VCSEL laser according to claim 6, characterized in that: In step S12, a metal film is deposited on the surface of the wafer to form an electroplated seed gold layer, a P-side isolation channel is formed by photolithography and wet etching to realize strip-shaped partitioning of the P-side light-emitting area, and a contact metal layer is formed by photolithography and electroplating.

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