An RC oscillator circuit

Abstract

The present invention discloses an RC oscillator circuit, which relates to the technical field of power management, including: a current generating module, whose input end is connected to a power supply and is used to generate a charging current; a current generating module including PMOS tubes P1 and P2, NMOS tubes N1-N3 and resistors R 1, a ramp voltage generating module, whose input end is connected to the output end of the current generating module, including PMOS tubes P3 and P4, NMOS tube N4 and capacitor #imgabs0#, and the sizes of PMOS tubes P1-P3 are the same; a clock generating module, whose input end is connected to the output end of the ramp voltage generating module, and the output is connected to the input of the D trigger; including NMOS tube N5, the gate of NMOS tube N5 is connected to the drain of N4. The circuit of the present invention does not need a comparator, only needs to input a power supply voltage to generate a clock signal, and the clock cycle is independent of the power supply voltage.

Description

Technical Field

[0001] The invention relates to the technical field of power management, and in particular to an RC oscillator circuit. Background Art

[0002] Oscillators are widely used in power chips and can provide chips with clock signals with stable frequencies. Traditional RC oscillators require additional reference voltages and one or even two comparators to achieve fixed-frequency clock outputs. This approach consumes a large number of tubes, consumes a lot of power itself, and the generated clock frequency is affected by the power supply voltage and reference voltage. Summary of the invention

[0003] The present invention provides an RC oscillator circuit, which solves the problem that a traditional RC oscillator needs an additional reference voltage and one or even two comparators to achieve a fixed-frequency clock output, which consumes a large number of tubes, has high power consumption, and the generated clock frequency is affected by the power supply voltage and the reference voltage.

[0004] The present invention provides an RC oscillator circuit, comprising:

[0005] The current generating module has an input end connected to a power supply and is used to generate a charging current; the current generating module includes PMOS tubes P1 and P2, NMOS tubes N1-N3 and resistors R 1. PMOS tubes P1 and P2 are current mirrors, NMOS tubes N1 and N2 are common gate structures, the sources of PMOS tubes P1 and P2 are connected to the power supply, and the drains are connected to the drains of NMOS tubes N1 and N2 respectively; the resistor R One end of 1 is connected to the source of NMOS tube N1, and the other end is grounded; the drain of NMOS tube N3 is connected to the source of N2 and the gate of N3, the gate is connected to the source of N2, and the source is grounded;

[0006] The ramp voltage generating module, whose input end is connected to the output end of the current generating module, includes PMOS tubes P3 and P4, NMOS tube N4 and capacitor , the sizes of PMOS tubes P1-P3 are the same; the source of PMOS tube P4 is connected to the drain of P3; the gate of NMOS tube N4 is connected to the gate of PMOS tube P4 and the input of D trigger, and the drain is connected to the drain of P4 and the capacitor The positive plate is connected, and the source is grounded; the charging current is Charging is performed to obtain a ramp voltage;

[0007] A clock generation module, whose input end is connected to the output end of the ramp voltage generation module, and whose output end is connected to the input of a D trigger; the clock generation module includes an NMOS tube N5, the gate of which is connected to the drain of N4; the sizes of the NMOS tubes N5 and N3 are the same; when the ramp voltage is greater than the threshold voltage of the NMOS tube N5, the source voltage of the NMOS tube N5 decreases, the gate voltage of the NMOS tube N4 increases, and the ramp voltage decreases. At this time, the capacitor Discharge; Capacitor When the voltage is discharged to 0 immediately, the ramp voltage is less than the threshold voltage of NMOS tube N5, and the charging current has an impact on the capacitor. The gate voltage of NMOS tube N4 decreases and a cycle of T The pulse signal generates a periodic clock signal after passing through the D flip-flop.

[0008] Preferably, the source of the PMOS tube P1 is connected to the power supply, the gate is connected to the drain of the PMOS tube P1 and the gate of the PMOS tube P2, and the drain is connected to the drain of the NMOS tube N1 and the gates of the PMOS tubes P1 and P2; the source of the PMOS tube P2 is connected to the power supply, the gate is connected to the drain of the PMOS tube P1 and the gate of the PMOS tube P1, and the drain is connected to the drain of the NMOS tube N2 and the gates of the NMOS tubes N1 and N2; the drain of the NMOS tube N1 is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1 and P2, the gate is connected to the gate and drain of the NMOS tube N2 and the drain of the PMOS tube P2, and the source is connected to the resistor R 1; the drain of NMOS tube N2 is connected to the drain of PMOS tube P2 and the gates of NMOS tubes N1 and N2, the gate is connected to the gate of NMOS tube N1, the drain of NMOS tube N2 and the drain of PMOS tube P2, the source is connected to the drain and gate of NMOS tube N3; the drain of NMOS tube N3 is connected to the source of NMOS tube N2 and the gate of NMOS tube N3, the gate is connected to the source of NMOS tube N2 and the drain of NMOS tube N3, and the drain is grounded; the resistor R The other end of 1 is grounded.

[0009] Preferably, the source of the PMOS tube P3 is connected to the power supply, the gate is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1, P2 and P3, and the drain is connected to the source of the PMOS tube P4; the source of the PMOS tube P4 is connected to the drain of the PMOS tube P3, the gate is connected to the gate of the NMOS tube N4, and the drain is connected to the drain of the NMOS tube N4 and the positive plate of the capacitor; the drain of the NMOS tube N4 is connected to the drain of the PMOS tube P4 and the positive plate of the capacitor, the gate is connected to the gate of the PMOS tube P4, and the source is grounded; the capacitor The positive plate is connected to the drain of PMOS tube P4 and the drain of NMOS tube N4, and the capacitor The negative plate is grounded.

[0010] Preferably, the clock generation module further comprises PMOS tubes P5, P6, P7, P8 and P9 and NMOS tubes N6, N7 and N8; the source of the PMOS tube P5 is connected to the power supply, the gate is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1, P2, P3 and P6, the drain is connected to the drain of the NMOS tube N5, the gate of the PMOS tube P7 and the gate of the NMOS tube N6; the source of the PMOS tube P6 is connected to the power supply, the gate is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1, P2, P3 and P5, and the drain is connected to the source of the PMOS tube P7; the source of the PMOS tube P7 is connected to the power supply, the gate is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1, P2, P3 and P5, and the drain is connected to the source of the PMOS tube P7 The electrode of the PMOS tube P6 is connected to the drain of the PMOS tube P5, the gate is connected to the drain of the NMOS tube N5 and the gate of the NMOS tube N6, and the drain is connected to the drain of the NMOS tube N6, the gate of the PMOS tube P8 and the gate of the NMOS tube N7; the source of the PMOS tube P8 is connected to the power supply, the gate is connected to the drain of the PMOS tube P7, the drain of the NMOS tube N6 and the gate of the NMOS tube N7, and the drain is connected to the drain of the NMOS tube N7, the gate of the PMOS tube P9 and the gate of the NMOS tube N8; the source of the PMOS tube P9 is connected to the power supply, the gate is connected to the drain of the PMOS tube P8, the NMOS tube N6 and the gate of the NMOS tube N7 The drain of the NMOS tube N7 is connected to the gate of the NMOS tube N8, and the drain is connected to the drain of the NMOS tube N8, the gate of the PMOS tube P4, the gate of the NMOS tube N4, and the CLK port of the D trigger; the drain of the NMOS tube N5 is connected to the drain of the PMOS tube P5, the gate of the PMOS tube P7, and the gate of the NMOS tube N6, the gate is connected to the drain of the PMOS tube P4, the drain of the NMOS tube N4, and the positive plate of the capacitor, and the source is grounded; the drain of the NMOS tube N6 is connected to the drain of the PMOS tube P7, the gate of the PMOS tube P8, and the gate of the NMOS tube N7, and the gate is connected to the drain of the PMOS tube P5, the gate of the NMOS tube P7, and the positive plate of the capacitor. The drain of the OS transistor N5 is connected to the gate of the PMOS transistor P7, and the source is grounded; the drain of the NMOS transistor N7 is connected to the drain of the PMOS transistor P8, the gate of the PMOS transistor P9 and the gate of the NMOS transistor N8, the gate is connected to the drain of the PMOS transistor P7, the drain of the NMOS transistor N6 and the gate of the PMOS transistor P8, and the source is grounded; the drain of the NMOS transistor N8 is connected to the drain of the PMOS transistor P9, the gate of the PMOS transistor P4, the gate of the NMOS transistor N4 and the CLK port of the D trigger, the gate is connected to the drain of the PMOS transistor P8, the drain of the NMOS transistor N7 and the gate of the PMOS transistor P9, and the source is grounded.

[0011] Preferably, the D end of the D flip-flop is connected to the QN end of the flip-flop and the output port CLK, the CLK end is connected to the drain of the PMOS tube P9, the drain of the NMOS tube N8, the gate of the PMOS tube P4 and the gate of the NMOS tube N4, the Q end is suspended, and the QN end is connected to the D end and the output port CLK.

[0012] Preferably, the method for generating a charging current is specifically as follows:

[0013] ;

[0014] In the formula, I is the charging current, is the voltage at point A, which is the source voltage of NMOS tube N1. is the voltage at point B, which is the source voltage of NMOS tube N2. is the voltage difference between the gate and source of NMOS tube N3.

[0015] Preferably, the generation cycle is T The pulse signal is as follows:

[0016] according to CV = IT ,get:

[0017] ;

[0018] In the formula, Capacitor Positive plate voltage, T is the pulse time;

[0019] Assuming that N3 and N5 have the same size, the conduction threshold is the same, and we get:

[0020] ;

[0021] In the formula, is the voltage difference between the gate and source of NMOS tube N5.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The present invention comprises a current generating module, a ramp voltage generating module and a clock generating module. The current generating module comprises PMOS tubes P1 and P2, NMOS tubes N1-N3 and resistors R 1. The ramp voltage generation module includes PMOS tubes P3 and P4, NMOS tube N4 and capacitor , the PMOS tubes P1 and P2 in the current generation module are made the same size as the PMOS tube P3 in the ramp voltage generation module, so that the charging current generated passes through the voltage difference between the gate and source of the NMOS tube N3 and the resistanceR 1 is generated, and then the size of NMOS tube N3 and NMOS tube N5 in the clock generation module are made the same, so that the final generated pulse signal only passes through the capacitor and resistor R 1 is generated, and an RC oscillator circuit that does not require a comparator and can generate a periodic clock signal by only inputting a power supply voltage can be obtained. The clock cycle finally generated is independent of the power supply voltage and the reference voltage, which reduces the number of tubes consumed and reduces power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 It is a structural diagram of an RC oscillator circuit of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Reference Figure 1 The present invention provides an RC oscillator circuit, comprising a current generating module, a ramp voltage generating module and a clock generating module, wherein the current generating module is used to generate a charging current I The ramp voltage generating module is a circuit for generating a ramp voltage (a voltage that rises linearly periodically, i.e., a voltage at point C), and the clock generating module is a circuit for generating a clock.

[0028] The current generation module consists of PMOS (Positive Channel Metal Oxide Semiconductor) tubes P1 and P2, NMOS (N-Metal-Oxide-Semiconductor) tubes N1, N2 and N3, and resistors R 1. The ramp voltage generation module consists of PMOS tubes P3 and P4, NMOS tube N4 and capacitor The clock generation module is composed of PMOS tubes P5, P6, P7, P8 and P9, NMOS tubes N5, N6, N7 and N8 and D flip-flop D1.

[0029] Furthermore, the source of the PMOS tube P1 is connected to the power supply voltage VDD (Voltage The gate of the PMOS tube P1 is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P2, P3, P5 and P6. The drain of the PMOS tube P1 is connected to the drain of the NMOS tube N1 and the gates of the PMOS tubes P1, P2, P3, P5 and P6. The drain of the PMOS tube P2 is connected to VDD. The gate of the PMOS tube P2 is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1, P3, P5 and P6. The drain of the PMOS tube P2 is connected to the drain of the NMOS tube N2 and the gates of the NMOS tubes N1 and N2. The drain of the NMOS tube N1 is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1, P2, P3, P5 and P6. The gate of the NMOS tube N1 is connected to the gate and drain of the NMOS tube N2 and the drain of the PMOS tube P2. The drain of the NMOS tube N1 is connected to the resistor R 1, the drain of NMOS tube N2 is connected to the drain of PMOS tube P2 and the gates of NMOS tubes N1 and N2, the gate of NMOS tube N2 is connected to the gate of NMOS tube N1, the drain of NMOS tube N2 and the drain of PMOS tube P2, the source of NMOS tube N2 is connected to the drain and gate of NMOS tube N3, the drain of NMOS tube N3 is connected to the source of NMOS tube N2 and the gate of NMOS tube N3, the gate of NMOS tube N3 is connected to the source of NMOS tube N2 and the drain of NMOS tube N3, the drain of NMOS tube N3 is connected to the ground wire GND, the resistor R One end of 1 is connected to the source of NMOS tube N1, and the resistor R The other end of 1 is connected to GND.

[0030] The ramp voltage generation module consists of PMOS tubes P3 and P4, NMOS tube N4 and capacitor The source of the PMOS tube P3 is connected to VDD, the gate of the PMOS tube P3 is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1, P2, P3, P5 and P6, the drain of the PMOS tube P3 is connected to the source of the PMOS tube P4, the source of the PMOS tube P4 is connected to the drain of the PMOS tube P3, the gate of the PMOS tube P4 is connected to the gate of the NMOS tube N4, the drain of the PMOS tube P9, the drain of the NMOS tube N8 and the CLK port of the D trigger D1, the drain of the PMOS tube P4 is connected to the drain of the NMOS tube N4, the gate of the NMOS tube N5 and the capacitor The positive plate is connected to the drain of the NMOS tube N4, the drain of the PMOS tube P4, the gate of the NMOS tube N5 and the capacitor The positive plate is connected to the gate of the NMOS tube N4, the gate of the PMOS tube P4, the drain of the PMOS tube P9, the drain of the NMOS tube N8 and the CLK port of the D trigger D1, the source of the NMOS tube N4 is connected to GND, and the capacitor The positive plate is connected to the drain of PMOS tube P4, the drain of NMOS tube N4 and the gate of NMOS tube N5. The negative plate is connected to GND;

[0031] The clock generation module is composed of PMOS tubes P5, P6, P7, P8 and P9, NMOS tubes N5, N6, N7 and N8 and a D flip-flop D1. The source of the PMOS tube P5 is connected to VDD, the gate of the PMOS tube P5 is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1, P2, P3 and P6, the drain of the PMOS tube P5 is connected to the drain of the NMOS tube N5, the gate of the PMOS tube P7 and the gate of the NMOS tube N6, the source of the PMOS tube P6 is connected to VDD, the gate of the PMOS tube P6 is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1, P2, P3 and P5, the drain of the PMOS tube P6 is connected to the source of the PMOS tube P7, the source of the PMOS tube P7 is connected to the drain of the PMOS tube P6, the gate of the PMOS tube P7 is connected to the drain of the PMOS tube P5, the drain of the NMOS tube N5 and the gate of the NMOS tube N6, the drain of the PMOS tube P7 is connected to the drain of the NMOS tube N6, the gate of the PMOS tube P8 and the gate of the NMOS tube N7, The source of OS transistor P8 is connected to VDD, the gate of PMOS transistor P8 is connected to the drain of PMOS transistor P7, the drain of NMOS transistor N6 and the gate of NMOS transistor N7, the drain of PMOS transistor P8 is connected to the drain of NMOS transistor N7, the gate of PMOS transistor P9 and the gate of NMOS transistor N8, the source of PMOS transistor P9 is connected to VDD, the gate of PMOS transistor P9 is connected to the drain of PMOS transistor P8, the drain of NMOS transistor N7 and the gate of NMOS transistor N8, the drain of PMOS transistor P9 is connected to the drain of NMOS transistor N8, the gate of PMOS transistor P4, the gate of NMOS transistor N4 and the CLK port of D trigger D1, the drain of NMOS transistor N5 is connected to the drain of PMOS transistor P5, the gate of PMOS transistor P7 and the gate of NMOS transistor N6, the gate of NMOS transistor N5 is connected to the drain of PMOS transistor P4, the drain of NMOS transistor N4 and the capacitor The positive plate of NMOS tube N5 is connected, the source of NMOS tube N5 is connected to GND, the drain of NMOS tube N6 is connected to the drain of PMOS tube P7, the gate of PMOS tube P8 and the gate of NMOS tube N7, the gate of NMOS tube N6 is connected to the drain of PMOS tube P5, the drain of NMOS tube N5 and the gate of PMOS tube P7, the source of NMOS tube N6 is connected to GND, the drain of NMOS tube N7 is connected to the drain of PMOS tube P8, the gate of PMOS tube P9 and the gate of NMOS tube N8, the gate of NMOS tube N7 is connected to the drain of PMOS tube P7, the drain of NMOS tube N6 and the gate of PMOS tube P8, the source of NMOS tube N7 is connected to GND, and the gate of NMOS tube N The drain of the D flip-flop D8 is connected to the drain of the PMOS tube P9, the gate of the PMOS tube P4, the gate of the NMOS tube N4 and the CLK port of the D flip-flop D1, the gate of the NMOS tube N8 is connected to the drain of the PMOS tube P8, the drain of the NMOS tube N7 and the gate of the PMOS tube P9, the source of the NMOS tube N8 is connected to GND, the D end of the D flip-flop D1 is connected to the QN end of the D flip-flop D1 and the output port CLK, the CLK end of the D flip-flop D1 is connected to the drain of the PMOS tube P9, the drain of the NMOS tube N8, the gate of the PMOS tube P4 and the gate of the NMOS tube N4, the Q end of the D flip-flop D1 is suspended, and the QN end of the D flip-flop D1 is connected to the D end of the D flip-flop D1 and the output port CLK.

[0032] Assume the power supply voltage is VDD. According to the current mirror (P1 and P2) and the common gate structure (N1 and N2), the voltages at points A and B (the source voltage of N1 and the source voltage of N2) are equal, and the currents at P1 and P2 are equal. The generated current is I for:

[0033] .

[0034] If P1, P2, and P3 are the same size and have the same current mirror ratio, the current charging the capacitor is:

[0035] .

[0036] according to CV=IT , within a certain period of time, the voltage relationship generated by the current charging the capacitor is:

[0037] ;

[0038] Right now:

[0039] .

[0040] When the voltage at point C (the drain voltage of N4) is greater than the threshold voltage of N5, the voltage at point D (the drain voltage of N5) is pulled down, and the voltage at point E (the gate voltage of N4) is pulled up. After the voltage at point E is pulled up, the voltage at point C is pulled down, and the capacitor Discharge, current I Re-energize the capacitor Charging, at the same time the voltage at point E is pulled down again, and the cycle at point E is T The pulse is used as the clock signal of the D flip-flop, and the final output high level time is T , with a period of 2 T The clock signal.

[0041] If N3 and N5 are the same size, then the turn-on threshold is the same. V THN3 =V THN5 , V GSN3 =V GSN5 , V THN3 is the threshold voltage of NMOS tube N3, V THN5 is the threshold voltage of NMOS tube N5, V GSN3 is the gate-source voltage difference of NMOS tube N3, V GSN5 is the gate-source voltage difference of NMOS tube N5, then:

[0042] .

[0043] The resulting CLK signal cycle is only related to the resistance R 1 and capacitor The value of is related to , and has nothing to do with the power supply voltage.

[0044] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0045] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An RC oscillator circuit, characterized in that: include: A current generating module, whose input end is connected to a power supply, is used to generate a charging current; the current generating module comprises PMOS tubes P1 and P2, NMOS tubes N1, N2 and N3 and a resistor R1, the PMOS tubes P1 and P2 are current mirrors, the NMOS tubes N1 and N2 are common-gate structures, the sources of the PMOS tubes P1 and P2 are connected to the power supply, and the drains are connected to the drains of the NMOS tubes N1 and N2 respectively; one end of the resistor R1 is connected to the source of the NMOS tube N1, and the other end is grounded; the drain of the NMOS tube N3 is connected to the source of N2 and the gate of N3, the gate is connected to the source of N2, and the source is grounded; A ramp voltage generating module, whose input end is connected to the output end of the current generating module, comprises PMOS tubes P3 and P4, NMOS tube N4 and capacitor C1, and the sizes of PMOS tubes P1, P2 and P3 are the same; The source of the PMOS tube P4 is connected to the drain of P3; the gate of the NMOS tube N4 is connected to the gate of the PMOS tube P4 and the input of the D trigger, the drain is connected to the drain of P4 and the positive plate of the capacitor C1, and the source is grounded; the charging current charges the capacitor C1 to obtain a ramp voltage; A clock generation module, whose input end is connected to the output end of the ramp voltage generation module, and whose output end is connected to the input of a D-type flip-flop; the clock generation module comprises an NMOS tube N5, whose gate is connected to the drain of N4; the sizes of the NMOS tubes N5 and N3 are the same; when the ramp voltage is greater than the threshold voltage of the NMOS tube N5, the source voltage of the NMOS tube N5 decreases, the gate voltage of the NMOS tube N4 increases, the ramp voltage decreases, and the capacitor C1 discharges at this time; when the capacitor C1 is immediately discharged to 0, the ramp voltage is less than the threshold voltage of the NMOS tube N5, the charging current charges the capacitor C1, the gate voltage of the NMOS tube N4 decreases, and a pulse signal with a period of T is generated, and a periodic clock signal is generated after passing through the D-type flip-flop; The clock generation module also includes PMOS tubes P5, P6, P7, P8 and P9 and NMOS tubes N6, N7 and N8; the source of the PMOS tube P5 is connected to the power supply, the gate is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1, P2, P3 and P6, and the drain is connected to the drain of the NMOS tube N5, the gate of the PMOS tube P7 and the gate of the NMOS tube N6; the source of the PMOS tube P6 is connected to the power supply, the gate is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1, P2, P3 and P5, and the drain is connected to the source of the PMOS tube P7; the source of the PMOS tube P7 is connected to the PMOS tube P1, and the gates of the PMOS tubes P1, P2, P3 and P5 are connected. The drain of the MOS tube P6 is connected, the gate is connected to the drain of the PMOS tube P5, the drain of the NMOS tube N5 and the gate of the NMOS tube N6, the drain is connected to the drain of the NMOS tube N6, the gate of the PMOS tube P8 and the gate of the NMOS tube N7; the source of the PMOS tube P8 is connected to the power supply, the gate is connected to the drain of the PMOS tube P7, the drain of the NMOS tube N6 and the gate of the NMOS tube N7, the drain is connected to the drain of the NMOS tube N7, the gate of the PMOS tube P9 and the gate of the NMOS tube N8; the source of the PMOS tube P9 is connected to the power supply, the gate is connected to the drain of the PMOS tube P8, the drain of the NMOS tube N6 and the gate of the NMOS tube N7 The drain of NMOS tube N7 is connected to the drain of NMOS tube N8 and the gate of NMOS tube N8, and the drain is connected to the drain of NMOS tube N8, the gate of PMOS tube P4, the gate of NMOS tube N4 and the CLK port of the D trigger; the drain of NMOS tube N5 is connected to the drain of PMOS tube P5, the gate of PMOS tube P7 and the gate of NMOS tube N6, the gate is connected to the drain of PMOS tube P4, the drain of NMOS tube N4 and the positive plate of the capacitor, and the source is grounded; the drain of NMOS tube N6 is connected to the drain of PMOS tube P7, the gate of PMOS tube P8 and the gate of NMOS tube N7, and the gate is connected to the drain of PMOS tube P5, the gate of NMOS tube P7 and the positive plate of the capacitor. The drain of the S tube N5 is connected to the gate of the PMOS tube P7, and the source is grounded; the drain of the NMOS tube N7 is connected to the drain of the PMOS tube P8, the gate of the PMOS tube P9 and the gate of the NMOS tube N8, the gate is connected to the drain of the PMOS tube P7, the drain of the NMOS tube N6 and the gate of the PMOS tube P8, and the source is grounded; the drain of the NMOS tube N8 is connected to the drain of the PMOS tube P9, the gate of the PMOS tube P4, the gate of the NMOS tube N4 and the CLK port of the D trigger, the gate is connected to the drain of the PMOS tube P8, the drain of the NMOS tube N7 and the gate of the PMOS tube P9, and the source is grounded.

2. An RC oscillator circuit as claimed in claim 1, characterized in that: The source of the PMOS tube P1 is connected to the power supply, the gate is connected to the drain of the PMOS tube P1 and the gate of the PMOS tube P2, and the drain is connected to the drain of the NMOS tube N1 and the gates of the PMOS tubes P1 and P2; the source of the PMOS tube P2 is connected to the power supply, the gate is connected to the drain of the PMOS tube P1 and the gate of the PMOS tube P1, and the drain is connected to the drain of the NMOS tube N2 and the gates of the NMOS tubes N1 and N2; the drain of the NMOS tube N1 is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1 and P2, and the gate is connected to the gate and drain of the NMOS tube N2. The drain of the NMOS tube N2 is connected to the drain of the PMOS tube P2 and the gates of the NMOS tubes N1 and N2, the gate is connected to the gate of the NMOS tube N1, the drain of the NMOS tube N2 and the drain of the PMOS tube P2, the source is connected to the drain and gate of the NMOS tube N3; the drain of the NMOS tube N3 is connected to the source of the NMOS tube N2 and the gate of the NMOS tube N3, the gate is connected to the source of the NMOS tube N2 and the drain of the NMOS tube N3, and the drain is grounded; the other end of the resistor R1 is grounded.

3. An RC oscillator circuit as claimed in claim 2, characterized in that: The source of the PMOS tube P3 is connected to the power supply, the gate is connected to the drain of the PMOS tube P1 and the gates of the PMOS tubes P1, P2 and P3, and the drain is connected to the source of the PMOS tube P4; the source of the PMOS tube P4 is connected to the drain of the PMOS tube P3, the gate is connected to the gate of the NMOS tube N4, and the drain is connected to the drain of the NMOS tube N4 and the positive plate of the capacitor; the drain of the NMOS tube N4 is connected to the drain of the PMOS tube P4 and the positive plate of the capacitor, the gate is connected to the gate of the PMOS tube P4, and the source is grounded; the positive plate of the capacitor C1 is connected to the drain of the PMOS tube P4 and the drain of the NMOS tube N4, and the negative plate of the capacitor C1 is grounded.

4. An RC oscillator circuit as claimed in claim 3, characterized in that: The D end of the D trigger is connected to the QN end of the trigger and the output port CLK, the CLK end is connected to the drain of the PMOS tube P9, the drain of the NMOS tube N8, the gate of the PMOS tube P4 and the gate of the NMOS tube N4, the Q end is suspended, and the QN end is connected to the D end and the output port CLK.

5. An RC oscillator circuit as claimed in claim 4, characterized in that: The method is used to generate a charging current, which is specifically as follows: Where I is the charging current, V A is the voltage at point A, which is the source voltage of NMOS tube N1, V B is the voltage at point B, which is the source voltage of NMOS tube N2, V GSN3 is the voltage difference between the gate and source of NMOS tube N3.

6. An RC oscillator circuit as claimed in claim 5, characterized in that: The pulse signal with a period of T is specifically generated as follows: According to CV=IT, we get: Where V C is the positive plate voltage of capacitor C1, T is the pulse time; Assuming that N3 and N5 have the same size, the conduction threshold is the same, and we get: Where V GSN5 is the voltage difference between the gate and source of NMOS tube N5.

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