Capacitance transimpedance amplifier circuit and method based on composite dielectric gate photosensitive detector

Abstract

The invention discloses a capacitive trans-impedance amplifier circuit and method based on a composite dielectric gate photosensitive detector. In the circuit, a gate end of a composite dielectric gate photosensitive detector pixel is connected with an external bias voltage, a source end is grounded, and a drain end is connected with a first input end of a trans-impedance amplifier through a first switch; the second input end of the transimpedance amplifier is connected with external voltage, and two ends of the capacitor C1 and the second switch are connected with the output end and the first input end of the transimpedance amplifier to form a feedback loop; the output end of the transimpedance amplifier is connected with one end of the third switch, the other end of the third switch is connected with one end of the capacitor C2 and the gate end of the transistor M1, and the other end of the capacitor C2 is grounded; the source end of the transistor M1 is connected with an external voltage VDD, the drain end of the transistor M1 is connected with one input end of the comparator and the current source, the other input end of the comparator is connected with the ramp generator, and the output end of the comparator is connected with the counter. According to the invention, high-speed and high-precision reading of the composite dielectric gate double-transistor photosensitive detector can be realized.

Description

Technical Field

[0001] The invention relates to a capacitive transimpedance amplifier circuit and method based on a composite dielectric grating photosensitive detector, and belongs to the field of integrated circuits. Background Art

[0002] Currently, CCD and CMOS-APS are the two most common imaging devices, but they each have certain limitations. CCD requires complex timing control and voltage requirements, which results in a slow operation speed and difficulty in achieving high integration; while CMOS-APS uses photodiodes and has a more complex structure, resulting in a lower fill factor and a smaller full-well charge capacity.

[0003] In Chinese patent ZL201210442007.X, a composite dielectric gate dual transistor photodetector is proposed, which is characterized in that a single device has reset, photosensitivity and readout functions, thereby forming a complete pixel, which can greatly improve the pixel fill factor and increase the full well charge. As a new generation of imaging devices, the composite dielectric gate dual transistor photodetector has faster operating speed, larger fill factor, more full well charge and can be integrated with CMOS technology. The device uses a MOSFET signal readout area with a variable threshold for readout, which gives it an inherent advantage over CCD and CMOS-APS.

[0004] Based on the above characteristics, a circuit that can quantify the device readout current and detect the change in the device readout current caused by the change in the threshold voltage can realize stable and high-speed readout of the composite dielectric gate dual-transistor photosensitive detector. Patent ZL202310321390.1 proposes a composite dielectric gate dual-transistor pixel readout circuit based on an inverter chain transimpedance amplifier, which uses a ramp generator, an inverter chain transimpedance amplifier, a driver stage and a counter to realize analog conversion and digital readout of the device current. Its inverter chain transimpedance amplifier includes an open-loop feedforward amplifier composed of N stages of inverter cascades (N is an odd number) and a feedback network composed of resistors. Therefore, it inevitably has a response delay problem, and the larger the number of stages N, the more serious the delay problem. In addition, the inverter chain transimpedance amplifier has a high input impedance and has a large noise in a high-gain or low-frequency working environment. Summary of the invention

[0005] In order to solve the existing problems, the present invention provides a capacitive transimpedance amplifier circuit and method based on a composite dielectric grating photosensitive detector to achieve high-speed, high-precision, and low-noise readout of the composite dielectric grating photosensitive detector.

[0006] The technical solution adopted by the circuit of the present invention is as follows:

[0007] The capacitor transimpedance amplifier circuit based on the composite dielectric grating photosensitive detector includes a composite dielectric grating photosensitive detector pixel, a switch CTIA_READ, a switch CTIA_RST, a switch CTIA_TRAN, a transimpedance amplifier, a capacitor C1, an integral capacitor C2, a transistor M1, a ramp generator, a comparator and a counter; wherein the gate end of the composite dielectric grating photosensitive detector pixel is connected to an external bias voltage V dc , its source end is grounded, and its drain end is connected to the first input end of the transimpedance amplifier through the switch CTIA_READ; the second input end of the transimpedance amplifier is connected to the external voltage V REF,TIA , the two ends of capacitor C1 and switch CTIA_RST are connected to the output end and the first input end of the transimpedance amplifier to form a feedback loop; the output end of the transimpedance amplifier is connected to one end of the switch CTIA_TRAN, the other end of the switch CTIA_TRAN is connected to one end of the integral capacitor C2 and the gate end of the transistor M1, and the other end of the integral capacitor C2 is grounded; the source end of the transistor M1 is connected to the external voltage V DD connected to one input of the comparator and the current source I D The other input of the comparator is connected to the ramp generator, and the output of the comparator is connected to the input of the counter.

[0008] The present invention also provides a working method of the above-mentioned capacitive transimpedance amplifier circuit based on the composite dielectric grating photosensitive detector, wherein the composite dielectric grating photosensitive detector pixel includes a MOS-C signal collection area and a MOSFET signal readout area; the capacitive transimpedance amplifier circuit has two working modes, including an exposure mode and a readout mode: in the exposure mode, the MOS-C signal collection area generates a depletion region in the substrate under the action of the gate-substrate forward bias to realize the collection of photogenerated carriers, at this time all switches are disconnected to separate the various parts of the circuit to prevent mutual influence; in the readout mode, the transistor threshold voltage of the MOSFET signal readout area produces a corresponding change according to the amount of charge of the collected photogenerated carriers, thereby realizing the readout of the photogenerated carrier signal.

[0009] Furthermore, the specific working process of the capacitive transimpedance amplifier circuit is as follows:

[0010] In the readout mode, the switches CTIA_READ, CTIA_RST, and CTIA_TRAN are closed, the circuit enters the preparation phase, and the voltage of the integral capacitor C2 is reset to the pixel drain voltage V D ; Turn off the switch CTIA_RST, and the circuit enters the integration stage. The readout current of the composite dielectric grating photosensitive detector pixel discharges to the capacitor C1 and the integration capacitor C2 through the switch CTIA_READ and the switch CTIA_TRAN, so that the voltage difference across the integration capacitor C2 is approximately the clamping voltage V REF,TIA; Turn off the switch CTIA_TRAN, the circuit enters the conversion phase and stabilizes the voltage difference across the integral capacitor C2 at the clamping voltage V REF,TIA ; Disconnect the switches CTIA_READ, CTIA_RST, and CTIA_TRAN. The ramp generator provides voltage to the comparator. At this time, the counter starts counting and the ramp generator starts from the ramp starting voltage V RampStart Start to increase the voltage continuously until the ramp end voltage V RampEnd When the voltage at the connection terminal between the comparator and the ramp generator is greater than the voltage at the connection terminal between the comparator and the drain terminal of the transistor M1, the comparator flips and the counter stops counting. At this time, the number of clock cycles counted by the counter is recorded as N, which is used to represent the readout current of the pixel at this time.

[0011] The present invention also provides a composite dielectric grating photosensitive detector, comprising the above-mentioned capacitive transimpedance amplifier circuit based on the composite dielectric grating photosensitive detector.

[0012] The present invention also provides an imaging device, comprising the above-mentioned capacitive transimpedance amplifier circuit based on the composite dielectric grating photosensitive detector or the above-mentioned composite dielectric grating photosensitive detector.

[0013] The present invention also provides an application of a composite dielectric grating photosensitive detector, and the composite dielectric grating photosensitive detector is applied in the field of environmental radiation detection.

[0014] The present invention proposes a composite dielectric grating photosensitive detector pixel readout circuit based on a capacitive transimpedance amplifier, which uses a capacitive transimpedance amplifier to integrate the photosensitive detector pixel readout current, and then uses a comparator to compare the transimpedance amplifier output voltage with the voltage generated by the ramp amplifier, and uses the output of the comparator, that is, the comparison result of the two voltages, as an enable signal of the counter to quantify the pixel readout current, thereby realizing high-speed and high-precision readout of the composite dielectric grating photosensitive detector. In addition, the circuit of the present invention can control the composite dielectric gate transistor pixel to switch between the working state and the non-working state through a switch, so it is conducive to realizing the double sampling function, further improving the readout accuracy, and suppressing the readout noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of a capacitive transimpedance amplifier circuit based on a composite dielectric grating photosensitive detector of the present invention;

[0016] Figure 2 It is a timing diagram of the port pressurization operation of the capacitive transimpedance amplifier circuit based on the composite dielectric grating photosensitive detector of the present invention. DETAILED DESCRIPTION

[0017] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0018] This embodiment provides a capacitive transimpedance amplifier circuit based on a composite dielectric grating photosensitive detector, such as Figure 1 As shown, it includes a composite dielectric grating photosensitive detector pixel, switches CTIA_READ, CTIA_RST, CTIA_TRAN, a transimpedance amplifier, a capacitor C1, an integrating capacitor C2, a transistor M1, a ramp generator, a comparator and a counter. The gate end of the composite dielectric grating photosensitive detector pixel is connected to an external fixed bias voltage V dc The source is grounded, and the drain is connected to the first input of the transimpedance amplifier through the switch CTIA_READ. The second input of the transimpedance amplifier is provided by an external V REF,TIA The capacitor C1 and the switch CTIA_RST are connected to the output terminal of the transimpedance amplifier and the first input terminal to form a feedback loop. The output terminal of the transimpedance amplifier is connected to one end of the switch CTIA_TRAN, the other end of the switch CTIA_TRAN is connected to one end of the integral capacitor C2 and the gate terminal of the transistor M1, the other end of the integral capacitor C2 is grounded, and the source terminal of the transistor M1 is connected to the external voltage V DD connected to one input of the comparator and the current source I D The other input of the comparator is controlled by the switch CTIA_RAMP and the ramp generator provides V RAMP The ramp voltage, the comparator output voltage V COMPOUT As input to the counter.

[0019] Among them, the transimpedance amplifier and comparator perform linear or nonlinear integration on the input signal charge. When the drain voltage V D Exceeds its threshold voltage V TH After that, the control signal is generated by controlling the switches CTIA_READ, CTIA_RST, CTIA_TRAN, and CTIA_RAMP, and the drain voltage of the pixel transistor of the composite dielectric gate photosensitive detector is discharged to the clamping voltage V by using the integrating capacitors C1 and C2. REF,TIA When the enable signal of the counter is logic 1, the counter is enabled. During the timer timing process, the value of the counter output port increases by 1 at the end of each clock cycle.

[0020] The composite dielectric grating photosensitive detector pixel of this embodiment includes a MOS-C (Metal-Oxide-Semiconductor Capacitor) signal collection area and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) signal readout area, and the input end of the transimpedance amplifier is connected to the N-type source area of ​​the MOSFET part. The capacitor transimpedance amplifier circuit has two working modes, including exposure mode and readout mode: in the exposure mode, the MOS-C signal collection area generates a depletion area in the substrate under the action of the gate-substrate forward bias to realize the collection of photogenerated carriers. At this time, all switches CTIA_READ, CTIA_RST, CTIA_TRAN and CTIA_RAMP are disconnected to separate the circuit parts to prevent mutual influence; in the readout mode, the transistor threshold voltage of the MOSFET signal readout area changes accordingly according to the collected photogenerated carrier charge, so as to realize the readout of the photogenerated carrier signal.

[0021] The specific working process of the capacitor transimpedance amplifier circuit in this embodiment is as follows:

[0022] The composite dielectric grating photosensitive detector pixel is sensitive to light through the PN junction. The PN junction absorbs photons to generate photocurrent and increase the drain voltage of the composite dielectric grating photosensitive detector pixel transistor. At this time, the exposure mode is entered, and the switches CTIA_READ, CTIA_RST, CTIA_TRAN and CTIA_RAMP are closed until the drain voltage of the pixel transistor is stable at V D .

[0023] After the exposure mode ends, the switches CTIA_READ, CTIA_RST and CTIA_TRAN are closed, the working mode is switched to the readout mode and enters the preparation stage. The composite dielectric grating photosensitive detector pixel transistor resets the capacitor C2 voltage to the pixel transistor drain voltage V through CTIA_READ, CTIA_RST and CTIA_TRAN. D .

[0024] After the preparation phase, the integration phase begins. The switch CTIA_RST is disconnected, and the readout current of the composite dielectric grating photosensitive detector pixel transistor is discharged to capacitors C1 and C2 through CTIA_READ and CTIA_TRAN. The discharge charge Q is:

[0025] Q=(V D -V REF,TIA )×(C1+C1)

[0026] Where V Dis the pixel transistor drain voltage, V REF,TIA is the clamping voltage.

[0027] The discharge current can be expressed as:

[0028]

[0029] where μ n is the electron mobility, C OX is the oxide layer capacitance density, w and l are the length and width of the pixel transistor of the composite dielectric gate photosensitive detector, respectively. GS is the gate bias voltage of the pixel transistor of the composite dielectric gate photosensitive detector, V TH is its threshold voltage.

[0030] According to the law of charge conservation, we can get:

[0031] I D ×t Integ =Q = (C1 + C2) × (V D -V REF,TIA )

[0032] Among them I D is the drain current of the pixel transistor of the composite dielectric gate photosensitive detector, t Integ is the integration time,

[0033] The conversion voltage can be obtained:

[0034]

[0035] The theoretical value of this conversion voltage can be used as a reference value for the counter output in the circuit.

[0036] After the integration phase is completed, the switch CTIA_TRAN is disconnected and the conversion phase begins. During this phase, the voltage on capacitor C2 tends to stabilize within 20us. After that, the switches CTIA_READ, CTIA_RST and CTIA_TRAN are all disconnected to enter the readout phase. At this time, the counter starts counting and the ramp generator starts from the ramp start voltage V RampStart Start to increase the voltage continuously until the ramp end voltage V RampEnd The ramp voltage V RAMP , preferably, the ramp starting voltage V RampStart The default value is 0V, the voltage is adjustable in the range of 0-1V, and the ramp termination voltage V RampEnd The default value is 5V, and the voltage can be adjusted within the range of 5-6V. When the voltage at the connection end between the comparator and the ramp generator is greater than the voltage at the connection end between the comparator and the drain terminal of the transistor M1, the comparator flips and the counter stops counting. The number of clock cycles counted by the counter is recorded as N, which can be used to characterize the readout current of the transistor pixel at this time.

[0037] The present invention realizes the function of integral discharge by utilizing only a few capacitors and a number of CMOS devices, and realizes high-speed and high-precision reading of the composite dielectric gate dual-transistor photosensitive detector. Figure 2 Introduced Figure 1 The port pressure working timing diagram of the capacitive transimpedance amplifier circuit based on the composite dielectric grating photosensitive detector is shown in the figure. The circuit structure represents the readout circuit of a single column of composite dielectric grating photosensitive detector pixel transistors. In this embodiment, four columns of composite dielectric grating photosensitive detector pixel transistors share one readout circuit. GBL=0, 1, 2, 3 represent the readout timing of the four columns of composite dielectric grating photosensitive detector pixels. After the exposure mode, the GBL=0 column is selected. After a 50ns preparation phase, a 100ns integration phase, a 20ns conversion phase, and a 2.048us readout phase, the column is switched to GBL=1, 2, 3 and the above readout mode timing is repeated. At this point, the readout of the four columns of composite dielectric grating photosensitive detector pixel transistors is completed.

Claims

1. A capacitive transimpedance amplifier circuit based on a composite dielectric grating photosensitive detector, characterized in that: The circuit includes a composite dielectric grating photosensitive detector pixel, a switch CTIA_READ, a switch CTIA_RST, a switch CTIA_TRAN, a transimpedance amplifier, a capacitor C1, an integrating capacitor C2, a transistor M1, a ramp generator, a comparator and a counter; wherein the gate end of the composite dielectric grating photosensitive detector pixel is connected to an external bias voltage V dc , its source end is grounded, and its drain end is connected to the first input end of the transimpedance amplifier through the switch CTIA_READ; the second input end of the transimpedance amplifier is connected to the external voltage V REF,TIA , the two ends of capacitor C1 and switch CTIA_RST are connected to the output end and the first input end of the transimpedance amplifier to form a feedback loop; the output end of the transimpedance amplifier is connected to one end of the switch CTIA_TRAN, the other end of the switch CTIA_TRAN is connected to one end of the integral capacitor C2 and the gate end of the transistor M1, and the other end of the integral capacitor C2 is grounded; the source end of the transistor M1 is connected to the external voltage V DD connected to one input of the comparator and the current source I D The other input of the comparator is connected to the ramp generator, and the output of the comparator is connected to the input of the counter.

2. The capacitive transimpedance amplifier circuit based on the composite dielectric grating photosensitive detector according to claim 1, characterized in that: The other input terminal of the comparator is connected to the ramp generator through the switch CTIA_RAMP, and the ramp generator provides a ramp starting voltage V RampStart To the ramp end voltage V RampEnd The ramp voltage V RAMP .

3. The capacitive transimpedance amplifier circuit based on the composite dielectric grating photosensitive detector according to claim 2, characterized in that: The ramp starting voltage V RampStart Adjustable in the range of 0-1V, the ramp termination voltage V RampEnd Adjustable in the range of 5-6V.

4. A method for operating a capacitive transimpedance amplifier circuit based on a composite dielectric grating photosensitive detector according to any one of claims 1 to 3, characterized in that: The composite dielectric grating photosensitive detector pixel includes a MOS-C signal collection area and a MOSFET signal readout area; the capacitive transimpedance amplifier circuit has two working modes, including an exposure mode and a readout mode: in the exposure mode, the MOS-C signal collection area generates a depletion area in the substrate under the action of the gate-substrate forward bias to realize the collection of photogenerated carriers, and at this time all switches are disconnected to separate the various parts of the circuit to prevent mutual influence; in the readout mode, the transistor threshold voltage of the MOSFET signal readout area produces corresponding changes according to the amount of charge of the collected photogenerated carriers, thereby realizing the readout of the photogenerated carrier signal.

5. The working method according to claim 4, characterized in that: The specific working process of the capacitor transimpedance amplifier circuit is as follows: In the readout mode, the switches CTIA_READ, CTIA_RST, and CTIA_TRAN are closed, the circuit enters the preparation phase, and the voltage of the integral capacitor C2 is reset to the pixel drain voltage V D ; When the switch CTIA_RST is disconnected, the circuit enters the integration stage. The readout current of the composite dielectric grating photosensitive detector pixel discharges to the capacitor C1 and the integration capacitor C2 through the switch CTIA_READ and the switch CTIA_TRAN, so that the voltage difference across the integration capacitor C2 is approximately the clamping voltage V REF,TIA ; Disconnect the switch CTIA_TRAN, the circuit enters the conversion phase and stabilizes the voltage difference across the integral capacitor C2 at the clamping voltage V REF,TIA ; Disconnect the switches CTIA_READ, CTIA_RST, and CTIA_TRAN. The ramp generator provides voltage to the comparator. The counter starts counting and the ramp generator starts from the ramp start voltage V RampStart Start to increase the voltage continuously until the ramp end voltage V RampEnd When the voltage at the connection terminal between the comparator and the ramp generator is greater than the voltage at the connection terminal between the comparator and the drain terminal of the transistor M1, the comparator flips and the counter stops counting. At this time, the number of clock cycles counted by the counter is recorded as N, which is used to represent the readout current of the pixel at this time.

6. The working method according to claim 5, characterized in that: When the enable signal of the counter is logic 1, the counter is enabled, and during the timing of the timer, at the end of each clock cycle, the value of the counter output port increases by 1.

7. A composite dielectric grating photosensitive detector, characterized in that: The composite dielectric grating photosensitive detector comprises a capacitive transimpedance amplifier circuit based on the composite dielectric grating photosensitive detector as described in any one of claims 1-3.

8. An imaging device comprising the capacitive transimpedance amplifier circuit based on the composite dielectric grating photosensitive detector according to any one of claims 1 to 3 or the composite dielectric grating photosensitive detector according to claim 7.

9. The use of a composite dielectric grating photosensitive detector as claimed in claim 7, characterized in that: The composite dielectric grating photosensitive detector is used in the field of environmental radiation detection.

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