High-precision low-latency analog-to-digital converter capacitor mismatch self-calibration circuit and method

Abstract

The application discloses a high-precision low-latency analog-to-digital converter (ADC) capacitor mismatch self-calibration circuit and method, and the calibration process mainly comprises four stages of a sampling and setting stage, a quantization stage, an amplification stage and an integration stage; the error voltage generated by a to-be-calibrated DAC unit is exponentially incremented and quantitatively estimated by taking the DAC unit of the ADC itself as a calibration DAC, and then compensation is carried out in a digital domain or an analog domain, thereby realizing calibration of the capacitor mismatch error. On the premise of adding a small hardware overhead, the original error detection range is broken through by combining the quantization principle of the exponentially incremented ADC, so that errors less than 1 LSB can also be estimated, and the limitation of self-mismatch of the calibration DAC on the calibration effect is optimized, and accurate calibration of the capacitor mismatch error of a 24-bit high-precision low-latency ADC can be realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit design, and particularly relates to a high-precision low-latency analog-to-digital converter capacitor mismatch self-calibration circuit and method. BACKGROUND

[0002] Precise instruments and meters, medical imaging and other applications urgently need 24-bit high-precision low-latency analog-to-digital converter (ADC) chips, which are core components of real-time measurement and real-time image processing systems. Successive approximation ADC (SAR ADC for short) has become a mainstream architecture of high-precision low-latency analog-to-digital converters due to its low power consumption and simple circuit structure. However, the non-linear error introduced by capacitor mismatch limits the possibility of SAR ADC developing towards high precision and high speed. Therefore, in order to realize high-precision SAR ADC, additional calibration technology needs to be introduced to calibrate the capacitor mismatch.

[0003] A relatively common capacitor mismatch foreground self-calibration method is to use a low-bit DAC itself from top to bottom as a calibration DAC to estimate the error of a high-bit DAC, and then perform error compensation in the analog or digital domain. However, this calibration method can only estimate errors greater than 1 LSB, and when calibrating high-precision ADCs higher than 16 bits, the mismatch of the low-bit DAC itself will limit the calibration effect. SUMMARY

[0004] In order to solve the above problems existing in the prior art, the application provides a high-precision low-latency analog-to-digital converter capacitor mismatch self-calibration circuit and method.

[0005] The technical problem to be solved by the application is solved by the following technical scheme:

[0006] The application provides a high-precision low-latency analog-to-digital converter capacitor mismatch self-calibration circuit, comprising:

[0007] A noise shaping unit is configured to store the amplified G times upper plate residual voltage of the CDAC array in the self-calibration circuit according to the control of a signal clk_ns1, and input the stored residual voltage into the CDAC array according to the control of a signal clk_ns2; each CDAC array contains M-bit main capacitors;

[0008] A residual voltage clearing unit is configured to clear the upper plate residual voltage stored in the noise shaping unit according to the control of a signal clk_reset before calibrating the mth capacitor; M is a positive integer greater than 1, m is a positive integer, the value of m is a preset integer x to M-1, and x is a first preset positive integer;

[0009] a sampling switch unit, configured to, when calibrating the m-th capacitor, access the common mode voltage VCM according to the control of a signal clk_sample so as to be sampled by each CDAC array;

[0010] a set and quantization unit, configured to, when calibrating the m-th capacitor, alternately perform two different set operations on the m-th capacitor according to the control of signals clk_set and clk_comp, and perform a round of quantization on the (m-1)th to (1)th capacitors after each set operation, input an upper plate margin voltage generated by the current round of quantization into the noise shaping unit, and then perform a next round of quantization based on the upper plate margin voltage stored in the noise shaping unit, until p rounds of quantization are performed on the (m-1)th to (1)th capacitors under each set operation; p is a second preset positive integer;

[0011] A calibration and storage unit is configured to determine the weight of the m-th capacitor based on the calibration codes of the m-1th to 1st capacitors generated by the p-round quantization, as well as the weights and amplification factors G of the m-1th to 1st capacitors, complete the calibration of the m-th capacitor, and store the weight of the m-th capacitor for use in calibrating the m+1th capacitor.

[0012] The present invention also provides a high-precision, low-latency analog-to-digital converter capacitance mismatch self-calibration method, which is implemented using the above-mentioned high-precision, low-latency analog-to-digital converter capacitance mismatch self-calibration circuit. The self-calibration circuit includes a CDAC array, each CDAC array including M-bit main capacitors. The method includes:

[0013] Residue clearing step: clearing the stored upper plate margin voltage of each CDAC array;

[0014] The first sampling step: use each CDAC array to measure the common mode voltage V CM Performing a sampling operation, sampling the stored upper plate margin voltage at the same time, and then comparing the voltages of the upper plates of different CDAC arrays to obtain a first comparison result; m is a positive integer, and the value of m ranges from a preset integer x to M-1, where x is a first preset positive integer; wherein, when the first sampling step is performed for the first time, the voltage value obtained after sampling the stored upper plate margin voltage is 0;

[0015] A first setting step: generating a first calibration code for the m-th capacitor according to the first comparison result, generating a first control code for the m-th capacitor according to the first calibration code for the m-th capacitor, and performing a setting operation on the m-th capacitor according to the first control code for the m-th capacitor;

[0016] The first quantization step: after the mth bit capacitor is set to 1, the m-1th to 1st bit capacitors are quantized for one round, and after the quantization, the calibration code of the m-1th to 1st bit capacitors generated by the quantization is obtained, and the upper plate residual voltage generated by the quantization is amplified by G times and then stored;

[0017] The second sampling step: each CDAC array samples the common-mode voltage V CM for one time, and the stored upper plate residual voltage is also sampled, and then the voltages of the upper plates of different CDAC arrays are compared to obtain a second comparison result;

[0018] The second setting step: a second calibration code of the mth bit capacitor is generated according to the second comparison result, a second control code of the mth bit capacitor is generated according to the second calibration code of the mth bit capacitor, and the mth bit capacitor is set to 0 according to the second control code of the mth bit capacitor;

[0019] The second quantization step: after the mth bit capacitor is set to 0, the m-1th to 1st bit capacitors are quantized for one round, and after the quantization, the calibration code of the m-1th to 1st bit capacitors generated by the quantization is obtained, and the upper plate residual voltage generated by the quantization is amplified by G times and then stored;

[0020] The first sampling step is returned to continue to be executed until the first sampling step to the second quantization step are executed p times, and then the calibration is ended, and the calibration code of the m-1th to 1st bit capacitors generated by each quantization under the setting of the mth bit capacitor to 0 and 1 is obtained;

[0021] Based on the weights of the m-1th to 1st bit capacitors, the amplification G, and the calibration code of the m-1th to 1st bit capacitors generated by each quantization under the setting of the mth bit capacitor to 0 and 1, the weight of the mth bit capacitor is determined, and the calibration of the mth bit capacitor is completed.

[0022] Compared with the prior art, the present application has the following beneficial effects:

[0023] The present application can realize accurate calibration of 24-bit high-precision low-latency ADC capacitor mismatch error under the premise of increasing small hardware overhead, by combining the quantization principle of the exponential increment type ADC, breaking through the original error detection range, enabling errors less than 1 LSB to be estimated, and optimizing the limitation of the calibration DAC itself mismatch on the calibration effect.

[0024] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is the overall circuit structure diagram of the self-calibration circuit provided by the embodiment of the present application;

[0026] Figure 2 is the working clock timing diagram of the self-calibration circuit provided by the embodiment of the present application;

[0027] Figure 3 is the capacitance DAC array of the self-calibration circuit provided by the embodiment of the present application and the specific calibration switching process schematic diagram;

[0028] Figure 4 is the 16384-point FFT spectrum comparison diagram after modeling and verification of the conventional calibration method of expanding the bit number and the calibration method of the present application in Matlab Simulink;

[0029] Figure 5 is the SNDR and SFDR convergence speed comparison diagram of the calibration circuit and method designed by the present application and the conventional calibration circuit and method. DETAILED DESCRIPTION

[0030] The present application will be further described in detail below in combination with specific embodiments, but the embodiments of the present application are not limited thereto.

[0031] The present application provides a high-precision low-latency analog-to-digital converter capacitance mismatch self-calibration circuit, comprising: a CDAC array, a noise shaping unit, a residual removal unit, a sampling switch unit, a setting and quantization unit and a calibration and storage unit; wherein the noise shaping unit and the CDAC array, the residual removal unit are connected respectively, the sampling switch unit is connected with the CDAC array, and the setting and quantization unit and the calibration and storage unit are connected with the CDAC array respectively. The noise shaping unit amplifies, stores and outputs the upper plate residual voltage of the CDAC array according to the control of the signal clk_ns1 and the signal clk_ns2; the residual removal unit removes the upper plate residual voltage stored in the noise shaping unit according to the control of the signal clk_reset; the sampling switch unit intervenes or not intervenes the common-mode voltage V CM according to the control of the signal clk_sample; the setting and quantization unit performs the quantization operation of the capacitance according to the control of the signals clk_set and clk_comp; and the calibration and storage unit performs the weight calculation of the capacitance and the storage and output of the data according to the control of the signal clk_cal.

[0032] The noise shaping unit is used for storing the upper plate residual voltage of the CDAC array in the self-calibration circuit after amplifying G times according to the control of the signal clk_ns1, and inputting the stored residual voltage into the CDAC array according to the control of the signal clk_ns2; each CDAC array contains M-bit main capacitance.

[0033] The residual clearing unit is configured to clear the top plate residual voltage stored in the noise shaping unit according to the control of the signal clk_reset before the mth bit capacitor is calibrated, where M is a positive integer greater than 1, m is a positive integer, the value of m is a preset integer x to M-1, and x is a first preset positive integer.

[0034] The sampling switch unit is configured to connect the common mode voltage VCM for sampling by each CDAC array according to the control of the signal clk_sample when the mth bit capacitor is calibrated.

[0035] The setting and quantization unit is configured to perform two different setting operations on the mth bit capacitor alternately according to the control of the signals clk_set and clk_comp when the mth bit capacitor is calibrated, and perform a round of quantization on the (m-1)th to 1st bit capacitors after each setting operation, input the top plate residual voltage generated in the current round of quantization into the noise shaping unit, and perform the next round of quantization according to the top plate residual voltage stored in the noise shaping unit, until p rounds of quantization are performed on the (m-1)th to 1st bit capacitors under each setting operation, where p is a second preset positive integer.

[0036] The calibration and storage unit is configured to determine the weight of the mth bit capacitor based on the calibration code of the (m-1)th to 1st bit capacitors generated in the p rounds of iterative quantization, and the weight and amplification factor G of the (m-1)th to 1st bit capacitors according to the control of the signal clk_cal, complete the calibration of the mth bit capacitor, and store the weight of the mth bit capacitor for the calibration of the (m+1)th bit capacitor.

[0037] Here, the values of x and p can be set according to actual needs, and the present application does not limit them.

[0038] Please refer to Figure 1 The self-calibration circuit further comprises a first adder and a second adder, as shown by reference signs Figure 1 in the figure. Furthermore, the self-calibration circuit comprises a first CDAC array and a second CDAC array, as shown by reference signs Figure 1CAP-P and CAP-N in the CAP array; the noise shaping unit comprises a first noise shaping module and a second noise shaping module. One input terminal of the first adder is connected with one output terminal of the sampling switch unit, another input terminal of the first adder is connected with an output terminal of the first noise shaping module, and an output terminal of the first adder is connected with a sampling terminal of the first CDAC array CAP-P. One input terminal of the second adder is connected with another output terminal of the sampling switch unit, another input terminal of the second adder is connected with an output terminal of the second noise shaping module, and an output terminal of the second adder is connected with a sampling terminal of the second CDAC array CAP-N. An input terminal of the first noise shaping module is connected with an upper plate excess voltage output terminal of the first CDAC array CAP-P, and the first noise shaping module is configured to store the upper plate excess voltage of the input first CDAC array CAP-P amplified by G times under the control of a signal clk_ns1, and input the stored excess voltage to the first CDAC array CAP-P through the first adder under the control of a signal clk_ns2. An input terminal of the second noise shaping module is connected with an upper plate excess voltage output terminal of the second CDAC array CAP-N, and the second noise shaping module is configured to store the upper plate excess voltage of the input second CDAC array CAP-N amplified by G times under the control of the signal clk_ns1, and input the stored excess voltage to the second CDAC array CAP-N through the second adder under the control of the signal clk_ns2. The upper plate of the first CDAC array CAP-P is connected with a positive input terminal (such as P terminal in Figure 1 ) of the set and quantization unit, and the first CDAC array CAP-P is configured to collect voltage from the output terminal of the first adder; and the upper plate of the second CDAC array CAP-N is connected with a negative input terminal (such as N terminal in Figure 1 ) of the set and quantization unit, and the second CDAC array CAP-N is configured to collect voltage from the output terminal of the second adder.

[0039] Here, the first CDAC array CAP-P and the second CDAC array CAP-N contain main capacitors and redundant capacitors, and the number and arrangement of capacitors in the first CDAC array CAP-P and the second CDAC array CAP-N are the same; for example, the first CDAC array CAP-P and the second CDAC array can each contain 28-bit capacitors, 20-bit capacitors or 18-bit capacitors, etc.; for example, in the case of containing 28-bit capacitors (i.e. 28 capacitors) in the first CDAC array CAP-P and the second CDAC array, it can specifically contain 24-bit main capacitors and 4-bit redundant capacitors. It should be noted that the number of main capacitors and redundant capacitors contained in the CDAC array can be set according to actual needs, and the present application does not limit this.

[0040] Reference continues to be made to Figure 1The first noise shaping module and the second noise shaping module both include: a first switch S1, a margin voltage memory ( Figure 1 The symbol "Z -1 ” indicates), the second switch S2, the amplifier with a magnification of G ( Figure 1 (Indicated by a triangle with the letter G). The first switch S1, the headroom voltage memory, the second switch S2, and the amplifier are connected in series in sequence. The end of the first switch S1 not connected to the headroom voltage memory serves as the output of the noise shaping module, and the end of the amplifier not connected to the second switch S2 serves as the input of the noise shaping module. The first switch S1 is opened or closed under the control of the signal clk_ns1, and the second switch S2 is opened or closed under the control of the signal clk_ns2. It should be noted that the specific value of G can be set according to actual needs and is not limited to this in the present invention. For example, the headroom voltage memory is a capacitor.

[0041] Continue to refer Figure 1 The setting and quantization unit includes: a SAR logic unit and a comparator. The upper plate of the first CDAC array CAP-P is connected to the positive input terminal of the comparator ( Figure 1 The upper plate of the second CDAC array CAP-N is connected to the negative input terminal of the comparator ( Figure 1 The SAR logic unit is connected to the N terminal in the SAR logic. One input terminal of the SAR logic unit is connected to the output terminal of the comparator. Another input / output terminal of the SAR logic unit is connected to the calibration and storage unit. One output terminal of the SAR logic unit is connected to the first CDAC array CAP-P, and the other output terminal is connected to the second CDAC array CAP-N. The SAR logic unit performs a set operation based on the control of the signal clk_set, and the comparator performs a comparison operation based on the control of the signal clk_comp.

[0042] Continue to refer Figure 1 The calibration and storage unit includes a calibration logic unit and a memory. One input / output terminal of the calibration logic unit is connected to the input / output terminal of the SAR logic unit, and another input / output terminal of the calibration logic unit is connected to an input / output terminal of the memory. Both the calibration logic unit and the memory operate under the control of a signal clk_cal.

[0043] Continue to refer Figure 1 The headroom clearing unit includes a third switch S3 and a fourth switch S4. One end of the third switch S3 is connected to both the first switch S1 in the first noise shaping module and one end of the headroom voltage memory, and the other end is grounded. One end of the fourth switch S4 is connected to both the first switch S1 in the second noise shaping module and one end of the headroom voltage memory, and the other end is grounded. The third and fourth switches S3 and S4 are opened or closed simultaneously under the control of the signal clk_reset.

[0044] With reference to the foregoing Figure 1 , the sampling switch unit comprises a fifth switch S5 and a sixth switch S6. One end of the fifth switch S5 is connected to the common-mode voltage V CM , and the other end is connected to one input end of the first adder. One end of the sixth switch S6 is connected to the common-mode voltage V CM , and the other end is connected to one input end of the second adder. The fifth switch S5 and the sixth switch S6 are used to be simultaneously opened or closed under the control of the signal clk_sample.

[0045] In the present application, the sampling switch unit is also used to connect the common-mode voltage V CMThe first noise shaping module is also configured to, according to the control of the signal clk ns1, store the upper plate residual voltage of the first CDAC array amplified by G times after each round of quantization of the (m-1)th to 1th capacitors, and then input the stored upper plate residual voltage into the first adder according to the control of the signal clk ns2, so that the first CDAC array is sampled before the next round of quantization. The second noise shaping module is also configured to, according to the control of the signal clk ns1, store the upper plate residual voltage of the second CDAC array amplified by G times after each round of quantization of the (m-1)th to 1th capacitors, and then input the stored upper plate residual voltage into the second adder according to the control of the signal clk ns2, so that the second CDAC array is sampled before the next round of quantization. The comparator is also configured to, according to the control of the signal clk comp, compare the upper plate voltage of the first CDAC array and the upper plate voltage of the second CDAC array after the setting operation of the (m)th capacitor or any one of the (m-1)th to 1th capacitors, obtain a corresponding comparison result, and output the comparison result to the SAR logic unit. The SAR logic unit is also configured to, when calibrating the (m)th capacitor, generate a first calibration code and a second calibration code of the (m)th capacitor according to the comparison result fed back by the comparator in real time according to the control of the signal clk set, alternately perform two different setting operations on the (m)th capacitor according to the first calibration code and the second calibration code of the (m)th capacitor, and perform a round of quantization of the (m-1)th to 1th capacitors after each setting operation in combination with the comparator, the first CDAC array and the second CDAC array, and convert the comparison result fed back by the comparator in real time into a calibration code of the (m-1)th to 1th capacitors and send it to the calibration and storage unit during the quantization process, until p rounds of quantization of the (m-1)th to 1th capacitors are completed under each setting operation. The calibration logic unit is configured to receive the calibration code generated by the SAR logic unit according to the control of the signal clk cal, and obtain the weight and amplification multiple G of the (m-1)th to 1th capacitors stored in the memory, calculate the weight of the (m)th capacitor according to the received calibration code and the weight and amplification multiple G of the (m-1)th to 1th capacitors, and store the weight of the (m)th capacitor to the memory.

[0046] Specifically, when the self-calibration circuit of the present application needs to perform the jth setting operation on the (m)th capacitor and perform a round of quantization of the (m-1)th to 1th capacitors after the jth setting operation on the (m)th capacitor, the working principles of the SAR logic unit, the first CDAC array and the second CDAC array and the comparator are as follows:

[0047] The SAR logic unit generates the jth calibration code of the (m)th capacitor according to the comparison result fed back by the comparator, generates the jth control code of the (m)th capacitor according to the jth calibration code of the (m)th capacitor (for example,Figure 2 D in calP and D calN ), according to the jth control code of the mth capacitor, the mth capacitor is set to 1 or 0, and then, in combination with the comparator, the first CDAC array and the second CDAC array, a round of quantization is performed on the m-1th to 1st capacitors. During the process of performing the round of quantization on the m-1th to 1st capacitors, a comparison result after the mth capacitor is set to 1 or 0 is fed back by the comparator, and when the received comparison result is 1, 1 is used as the calibration code of the m-1th capacitor, and when the received comparison result is 0, -1 is used as the calibration code of the m-1th capacitor, and the calibration code of the m-1th capacitor is sent to the calibration and storage unit, and the comparison result after the mth capacitor is set to 1 is also sent to the first CDAC array and the second CDAC array; j is a positive integer, and the value of j is 1 to 2p;

[0048] When the comparison result fed back by the comparator after the m-th capacitor is set to 1 is 1, the first CDAC array and the second CDAC array set the m-1-th capacitor to 0; when the comparison result fed back by the comparator after the m-th capacitor is set to 1 is 0, the m-1-th capacitor is set to 1;

[0049] The comparator generates a comparison result after setting the (m-1)th capacitor to 1 or 0 and sends the result to the SAR logic unit;

[0050] The SAR logic unit receives a comparison result fed back by the comparator after a setting operation is performed on the (m-1)th capacitor, and continues to generate a calibration code for the (m-2)th capacitor based on the received comparison result. The calibration code for the (m-2)th capacitor is sent to the calibration and storage unit. The comparison result fed back by the comparator after a setting operation is performed on the (m-1)th capacitor to be set to 1 or 0 is sent to the first CDAC array and the second CDAC array, so that the (m-2)th capacitor is set by the first CDAC array and the second CDAC array. This iterative cycle is repeated until a setting operation is completed once on the (m-1)th to 1st capacitors by combining the comparator, the first CDAC array, and the second CDAC array. This round of quantization for the (m-1)th to 1st capacitors is terminated, and the calibration code for the (m-1)th to 1st capacitors generated by the round of quantization is obtained.

[0051] In the present invention, when the set operation is performed on any capacitor in the first CDAC array and the second CDAC array, when the signal connected to the lower plate of the capacitor in the first CDAC array is switched to the reference voltage V REFAt the same time, when the signal connected to the lower plate of any capacitor in the second CDAC array is switched to GND, it indicates that a set operation is performed on the capacitor in the first CDAC array and the second CDAC array. Such a set operation is called SET1; when the signal connected to the lower plate of any capacitor in the first CDAC array is switched to the reference voltage GND, at the same time, the signal connected to the lower plate of any capacitor in the second CDAC array is switched to V REF When , it indicates that a setting operation is performed on any one capacitor in the first CDAC array and the second CDAC array. Such a setting operation is called SET0.

[0052] For example, Figure 2 FIG. 1 is a timing diagram of the working clock of the self-calibration circuit of the present invention. Figure 3 As shown, before starting to calibrate a certain main capacitor, the signal clk_reset appears at a high level once to control the fifth switch S5 and the sixth switch S6 to be turned on, thereby clearing the upper board margin voltage stored in the margin voltage memory. Then, when starting to calibrate the certain main capacitor, the signal clk_cal changes from a low level to a high level to enable the calibration logic unit and the memory to start working. At the same time, the signal clk_sample appears at a high level once to access a common mode voltage V CM , so that the first CDAC array CAP-P and the second CDAC array CAP-N are sensitive to the common mode voltage V CM A sampling is performed, and then, after the high level of the signal clk_sample ends, the signal clk_set appears a high level to enable the SAR logic unit to perform a set 1 operation on the certain main capacitor. At the same time, the signal clk_ns2 also appears a high level to input the stored upper board margin voltage into the first CDAC array CAP-P and the second CDAC array CAP-N. Then, multiple high levels appear in the signal clk_comp to perform a round of quantization on the low-order capacitance of the certain main capacitor; after that, after a round of quantization of the low-order capacitance of the certain main capacitor ends, the signal clk_ns1 appears a high level to input the upper board voltage generated by this round of quantization into the amplifier with an amplification factor of G for amplification and then storage; then, the signal clk_sample appears a high level again to access the common-mode voltage V again. CM , so that the first CDAC array CAP-P and the second CDAC array CAP-N are sensitive to the common mode voltage V CMAnother sampling is performed, after which the signal clk_ns2 appears at a high level again to input the stored upper board margin voltage into the first CDAC array CAP-P and the second CDAC array CAP-N. At the same time, the signal clk_set appears at a high level again to enable the SAR logic unit to set the main capacitor to 0 once. After that, multiple high levels appear in the signal clk_comp to perform another round of iterative quantization on the low-order capacitance of the main capacitor. This cycle is iterated until p rounds of quantization are completed, and the calibration logic unit calculates the weight of the main capacitor.

[0053] For example, Figure 2 The capacitance DAC array of the self-calibration circuit of the present invention and the specific calibration switching process are as follows. Figure 3 and Figure 3 For further explanation. Figure 3 As shown in FIG, the capacitor DAC array connected to the P-terminal of the comparator (referred to as the P-terminal CDAC array) and the capacitor DAC array connected to the N-terminal of the comparator (referred to as the N-terminal CDAC array) are both composed of 28-bit capacitor bridges, which include 24 main capacitors and 4 redundant capacitors, with the capacitor C m Take α as an example (m can be any main capacitor in the capacitor array), the specific calibration process is as follows:

[0054] 1) Sampling stage: Figure 3 As shown in Figure A, the clk_sample signal goes high, the sampling switches S5 and S6 are closed, and the upper plate of each capacitor in the CDAC array is connected to V CM Connected( Figure 3 In A, the operation of adding the margin voltage is omitted. Figure 3 (As shown in Figures D and E of FIG), the sampling switches S5 and S6 are then disconnected, and the sampling is completed. At this time, the expressions of the upper plate voltages of the P-end CDAC array and the N-end CDAC array are:

[0055] V P =V CM ;

[0056] V N =V CM ;

[0057] 2) Setting stage: Figure 3 As shown in Figure B, the clk_set signal becomes high, and the SAR logic unit responds to C m Set the CDAC in the P terminal to 1. mP Connect V REF At the same time, the N-terminal capacitor C mN Connect to GND, and the other capacitors are connected in the same way, still connected to V CMWhen the top plate voltage of the P-side CDAC array and the N-side CDAC array is connected, the expression of the top plate voltage of the P-side CDAC array and the N-side CDAC array becomes:

[0058]

[0059] Among them, W TOT is the total weight of the single-ended capacitance. It should be noted that in the above expression, W mP With W mN Refers to the capacitance C m The two true weights including the mismatch error.

[0060] 3) Quantification stage: Figure 3 As shown in the figure C, after the sampling and setting are completed, select the capacitor C to be calibrated. m Low capacitance of all bits (i.e. C m-1 To C1) as a calibration DAC, the upper plate voltage of the P-end and N-end CDAC array is quantized. When quantization is performed, the comparator starts working according to the clk_comp clock signal. For the i-th quantized capacitor, when the comparator output is 1, the lower plate of the i-th quantized capacitor in the P-end CDAC array is switched to GND, and the lower plate of the i-th quantized capacitor in the N-end CDAC array is switched to V REF , and record the calibration code D of the i-th quantized capacitor cal,i When the comparator output is 0, the lower plate of the i-th quantized capacitor in the P-terminal CDAC array is switched to V REF , switch the lower plate of the i-th quantized capacitor in the N-end CDAC array to GND, and record the calibration code Dcal of the i-th quantized capacitor i is -1( Figure 3 C6 to C in Figure C 1r The switching is only an example). During the quantization process, the ratio of C m High all bit capacitance with V CM They are connected and remain unchanged, and do not participate in the quantization process. In addition, in each round of quantization, the redundant bit capacitance encountered in this round of quantization is quantized in the same way as the main capacitance to be quantized in this round. After a round of quantization is completed, the expression of the top plate voltage of the P-end CDAC array and the N-end CDAC array becomes:

[0061]

[0062] Among them, n represents the m The number of redundant capacitors between i Represents the weight of the i-th capacitor, W ir Represents the weight of the ir-th redundant capacitor.

[0063] The residual voltage expression is:

[0064]

[0065] 4) Amplification stage: as shown in D figure in Figure 3 , the last time the lower plate switch is switched and the residual voltage is stable, V RES is amplified G times, clk_ns1 becomes high, and the amplified residual voltage is stored through the capacitor.

[0066] 5) Integration stage: as shown in E figure in Figure 4 , after the next sampling, clk_ns2 becomes high, the residual voltage after amplification is added to the sampling voltage V CM , and the expression of the actual voltage compared by the comparator becomes:

[0067]

[0068] Since the calibration capacitor C m , before calibration starts, the integration voltage needs to be reset to zero according to the clk_reset clock, so when calibrating each bit of capacitor, the residual voltage V RES added in the first quantization is 0, and for the i-th bit capacitor, the calibration code obtained after the first quantization is denoted as D cali1 . At this time, the weight calculation formula of the calibration capacitor C m is:

[0069]

[0070] The residual voltage V RES added in the second quantization comes from the first quantization, and for the i-th bit capacitor, the calibration code obtained after the second quantization is denoted as D cal,i,2 . At this time, the weight calculation formula of the calibration capacitor C m is modified to:

[0071]

[0072] In addition to the first quantization, the residual voltage added in other quantizations comes from the last quantization, and the above process is repeated p times. For the i-th bit capacitor, the j-th quantization output code is denoted as D cal,i,j . Then the real weight expression of the calibration capacitor C m is:

[0073]

[0074] Ideally, the real weight of the calibration capacitor containing mismatch error can be represented by D cal,i,j , but considering the system offset error VOFFSET , the true value of the above expression is actually:

[0075]

[0076] In order to eliminate V OFFSET , it is necessary to perform two kinds of settings alternately during the calibration process of each capacitor to be calibrated, and perform a round of quantization after each setting operation. For convenience, the capacitor to be calibrated C at the P end during the setting phase is mP The lower plate is switched to V REF At the same time, the N-terminal capacitor C mN The set operation of switching the lower plate of the capacitor to GND is called SET1; the capacitor to be calibrated C at the P end of the set phase mP Switch the lower plate of the capacitor to be calibrated to GND. mN The lower plate is switched to V REF The set operation is called SET0. After quantizing the error voltage introduced by SET1, it is necessary to quantize the error voltage introduced by SET0 again. During the quantization process, the two calibration codes obtained are D cal,i,j,SET1 and D cal,i,j,SET0 At this time, the capacitance C to be calibrated calculated according to the p-round quantization under each of the two set operations is m The expressions of the weights are:

[0077]

[0078] Therefore, the capacitor C to be calibrated m The weight expression can be calculated using the following formula:

[0079]

[0080] Among them, W m,cal Indicates the capacitance to be calibrated C m The weight, W i represents the weight of the i-th capacitor, D cal,i,(p-k+1),SET1 Indicates that in C m Set to 1 when C m-1 The i-th capacitance C generated when C1 performs the p-k+1th round of quantization i Calibration code, W ir Indicates the irth redundant capacitor C ir The weight of D cal,ir,(p-k+1),SEI1 Indicates that in C m Set to 1 when C m-1 The calibration code of the ir-th redundant capacitor generated when C1 performs the p-k+1th round of quantization, V OFFSET Denotes the system offset error of the ADC, D cal,i,(p-k+1),SET0Indicates that in C m Perform the set 0 operation on C m-1 The calibration code of the i-th capacitor generated when C1 performs the p-k+1th round of quantization, D cal,ir,(p-k+1),SET0 Indicates that in C m Perform the set 0 operation on C m-1 The calibration code of the ir-th redundant capacitor is generated when C1 performs the p-k+1-th round of quantization.

[0081] The calibration logic unit calculates W m,cal After that, W m,cal Write to memory, then you can choose to complete the C in the digital domain or analog domain m The digital domain compensation specifically refers to the use of W m,cal As the digital weight of the final output, analog domain compensation specifically refers to the use of additional programmable capacitor arrays to m The capacitance of the mth bit is corrected on the chip, and the completion of the correction operation indicates that the mth bit main capacitor C m Calibration is complete.

[0082] The entire calibration process of the present invention is performed from bottom to top. After the lower capacitor is calibrated, the next capacitor is calibrated using the updated digital weight or capacitance value.

[0083] Since the capacitance to be calibrated C m The actual capacitance value may be greater than the ideal capacitance value. In order to accurately measure C m The actual capacitance value, theoretically the calibration DAC measurement range provided by the ADC itself should be greater than C m The ideal capacitance is at least 2% (2% is a typical value of capacitance mismatch). In the present invention, 4 bits of redundancy (C 1r ,C 4r ,C 8r and C 16r ) to solve this problem, the specific location of the redundant bits is as follows Figure 5 At the same time, the exponential incremental ADC quantization method adopted by the present invention needs to consider the margin voltage V RES and the sampling voltage V CM Is the actual quantized voltage after addition within the quantization range of the calibration DAC? m When being calibrated, the specific requirements are: Therefore, it is necessary to carefully select the position of the redundant bits and the amplification factor G of the amplifier. An appropriate increase in the redundant bits can allow the amplification factor G to increase, thereby achieving a faster convergence speed. In addition, the present invention adds a margin voltage V after sampling. RES It is completely random and can be regarded as a kind of random jitter, which is conducive to the averaging of noise (such as sampling noise and comparator noise). This relaxes the requirement for the number of calibration rounds for each bit of capacitance and also speeds up the calibration.

[0084] The application also provides a high-precision low-latency analog-to-digital converter capacitor mismatch self-calibration method, which is implemented by using the high-precision low-latency analog-to-digital converter capacitor mismatch self-calibration circuit.

[0085] S1, a residual clearance step: clearing the stored upper plate residual voltage of each CDAC array;

[0086] S2, a first sampling step: sampling the common-mode voltage VCM by using each CDAC array, sampling the stored upper plate residual voltage, then comparing the voltages of the upper plates of different CDAC arrays to obtain a first comparison result; m is a positive integer, the value of m is a preset integer x to M-1, x is a first preset positive integer; wherein, when the first sampling step is performed for the first time, the voltage value obtained after sampling the stored upper plate residual voltage is 0;

[0087] S3, a first setting step: generating a first calibration code of the mth capacitor according to the first comparison result, generating a first control code of the mth capacitor according to the first calibration code of the mth capacitor, and performing a set-1 operation on the mth capacitor according to the first control code of the mth capacitor;

[0088] S4, a first quantization step: after performing the set-1 operation on the mth capacitor, performing a round of quantization on the (m-1)th to the 1st capacitors, and after the round of quantization, obtaining the calibration codes of the (m-1)th to the 1st capacitors generated by the round of quantization, and storing the upper plate residual voltage amplified by G times after the round of quantization;

[0089] S5, a second sampling step: sampling the common-mode voltage VCM by using each CDAC array, sampling the stored upper plate residual voltage, then comparing the voltages of the upper plates of different CDAC arrays to obtain a second comparison result;

[0090] S6, a second setting step: generating a second calibration code of the mth capacitor according to the second comparison result, generating a second control code of the mth capacitor according to the second calibration code of the mth capacitor, and performing a set-0 operation on the mth capacitor according to the second control code of the mth capacitor;

[0091] S7, a second quantization step: after performing the set-0 operation on the mth capacitor, performing a round of quantization on the (m-1)th to the 1st capacitors, and after the round of quantization, obtaining the calibration codes of the (m-1)th to the 1st capacitors generated by the round of quantization, and storing the upper plate residual voltage amplified by G times after the round of quantization;

[0092] S8, return to S2 to continue to execute until the first sampling step to the second quantization step are executed p times, and then end, to obtain the calibration code of the (m-1)th to the 1st capacitors generated by each round of quantization under the 0 and 1 operation of the mth capacitor;

[0093] S9, based on the weight of the (m-1)th to the 1st capacitors, the amplification G, and the calibration code of the (m-1)th to the 1st capacitors generated by each round of quantization under the 0 and 1 operation of the mth capacitor, the weight of the mth capacitor is determined, and the calibration of the mth capacitor is completed.

[0094] It should be noted that since the calibration codes generated in the above first setting step and the second setting step are different, the calibration code in the above first setting step is called the first calibration code, and the calibration code in the above second setting step is called the second calibration code. The first control code and the second control code are the same.

[0095] The present application breaks through the original error detection range by combining the quantization principle of the exponential increment type ADC under the premise of increasing smaller hardware overhead, so that errors less than 1 LSB can also be estimated, and the limitation of the calibration DAC itself mismatch on the calibration effect is optimized, and the accurate calibration of the 24-bit high-precision low-latency ADC capacitor mismatch error can be realized.

[0096] In order to further illustrate the technical effect of the present application, the modeling and verification of the self-calibration circuit of the present application are carried out in the Matlab Simulink software. The number of bits of the calibration DAC can be reduced to optimize the influence of the mismatch of the calibration DAC itself on the calibration accuracy. The entire circuit model uses a 1V power supply voltage, the sampling frequency is 2MS / s, the input signal amplitude is 2V V pp , the input signal frequency is 11.84KHz, the sampling point number is 16384, and the standard deviation of the DAC array mismatch is 2%. The calibration before and after the test is shown in the frequency spectrum diagram as ​ Compared with the calibration before the calibration, the SFDR is improved by 50.23dB, and the SNDR is improved by 33.51dB by using the capacitor mismatch error calibration circuit and method proposed in the present application.

[0097] In order to verify the optimization of the calibration circuit and method designed in the present application to the mismatch of the calibration DAC itself, a conventional calibration circuit and method (the DAC array of the two is exactly the same) is designed for comparison. Compared with the conventional calibration circuit and method, the SFDR is improved by 24.00dB, and the SNDR is improved by 7.49dB by using the calibration circuit and method designed in the present application, and the harmonics related to the input signal frequency are obviously suppressed, and the calibration effect is remarkable.

[0098] From the mathematical formula, if the same calibration effect as the calibration circuit and method designed by the application is to be achieved, the conventional calibration DAC needs to be additionally expanded bits, the unit capacitance will be reduced times, the mismatch error will be worsened times, the DAC area will also increase, and the calibration circuit and method designed by the application optimize these problems. ​ The comparison chart of the SNDR and SFDR convergence speed of the calibration circuit and method designed by the application and the conventional calibration circuit and method, in the modeling verification, when the calibration round p of each bit capacitance is 8, the SFDR and SNDR are greatly improved, compared with the conventional calibration circuit and method, the stability of the SNDR after calibration of the calibration circuit and method designed by the application is also greatly improved, the calibration effect is stable, the speed is significantly improved compared with the conventional self-calibration commonly used round 128, and fast foreground self-calibration is realized.

[0099] It should be noted that the terms "first", "second" are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can be explicitly or implicitly included one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0100] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present application.

[0101] In the description, the word "comprising" does not exclude other components or steps, and "one" or "a" does not exclude multiple cases. Some measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0102] The above is a further detailed description of the present application in combination with specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be regarded as falling within the protection scope of the present application.

Claims

1. A high-precision low-latency analog-to-digital converter capacitor mismatch self-calibration circuit, characterized in that, The self-calibration circuit comprises: a noise shaping unit configured to store a top-plate residue voltage of a CDAC array in the self-calibration circuit after amplification by G times according to control of a signal clk_ns1, and input the stored residue voltage into the CDAC array according to control of a signal clk_ns2; each CDAC array comprises M-bit main capacitors; a residue clearing unit configured to clear the top-plate residue voltage stored in the noise shaping unit according to control of a signal clk_reset before calibration of an mth-bit capacitor; M is a positive integer greater than 1, m is a positive integer, the value of m is a preset integer x to M-1, and x is a first preset positive integer; A sampling switch unit is configured to, when calibrating the mth bit capacitor, perform sampling according to the control of a signal clk_sample and a common-mode voltage V CM access by each CDAC array; a setting and quantization unit configured to, when the mth-bit capacitor is calibrated, perform two different setting operations on the mth-bit capacitor alternately according to control of signals clk_set and clk_comp, perform a round of quantization on the (m-1)th-bit capacitor to the 1st-bit capacitor after each setting operation, input a top-plate residue voltage generated in the current round of quantization into the noise shaping unit, and perform the next round of quantization according to the top-plate residue voltage stored in the noise shaping unit, until p rounds of quantization are performed on the (m-1)th-bit capacitor to the 1st-bit capacitor under each setting operation; p is a second preset positive integer; a calibration and storage unit configured to, according to control of a signal clk_cal, determine a weight of the mth-bit capacitor based on a calibration code of the (m-1)th-bit capacitor to the 1st-bit capacitor generated in the p rounds of quantization, and a weight and an amplification multiple G of the (m-1)th-bit capacitor to the 1st-bit capacitor, complete calibration of the mth-bit capacitor, and store the weight of the mth-bit capacitor for calibration of an (m+1)th-bit capacitor; the two different setting operations comprise a set-1 operation and a set-0 operation; when each CDAC array further comprises a redundant capacitor, an expression of the weight of the mth-bit capacitor in each CDAC array calculated by the calibration and storage unit is as follows: wherein, represents a weight of the mth bit capacitor, n represents an n-bit redundant capacitor between the 1st bit capacitor and the mth bit capacitor, represents a weight of the ith bit capacitor, represents a calibration code of the ith bit capacitor generated when the p-k+1th round quantization is performed on the m-1th to 1st bit capacitors under the set-1 operation on the mth bit capacitor, represents a weight of the irth bit redundant capacitor, represents a calibration code of the irth bit redundant capacitor generated when the p-k+1th round quantization is performed on the m-1th to 1st bit capacitors under the set-1 operation on the mth bit capacitor, represents a system offset error of the ADC, represents a calibration code of the ith bit capacitor generated when the p-k+1th round quantization is performed on the m-1th to 1st bit capacitors under the set-0 operation on the mth bit capacitor, represents a calibration code of the irth bit redundant capacitor generated when the p-k+1th round quantization is performed on the m-1th to 1st bit capacitors under the set-0 operation on the mth bit capacitor.

2. The high precision low latency analog-to-digital converter capacitance mismatch self-calibration circuit of claim 1, wherein, The self-calibration circuit further comprises a first adder, a second adder, a first CDAC array, and a second CDAC array; and the noise shaping unit comprises a first noise shaping module and a second noise shaping module. The first adder has one input end connected to one output end of the sampling switch unit, another input end connected to an output end of the first noise shaping module, and an output end connected to a sampling end of the first CDAC array. The second adder has one input end connected to another output end of the sampling switch unit, another input end connected to an output end of the second noise shaping module, and an output end connected to a sampling end of the second CDAC array. The first noise shaping module has an input end connected to a top-plate residue voltage output end of the first CDAC array, is configured to store a top-plate residue voltage of the first CDAC array after amplification by G times according to control of the signal clk_ns1, and input the stored residue voltage into the first CDAC array through the first adder according to control of the signal clk_ns2. The second noise shaping module is connected with the upper plate excess voltage output end of the second CDAC array, and is used for storing the amplified G times upper plate excess voltage of the second CDAC array according to the control of the signal clk_ns1, and inputting the stored excess voltage into the second CDAC array through the second adder according to the control of the signal clk_ns2. The upper plate of the first CDAC array is connected with the positive input end of the set and quantization unit, and is used for collecting the voltage from the output end of the first adder; and the upper plate of the second CDAC array is connected with the negative input end of the set and quantization unit, and is used for collecting the voltage from the output end of the second adder.

3. The high precision low latency analog-to-digital converter capacitance mismatch self-calibration circuit of claim 2, wherein, The first noise shaping module and the second noise shaping module each comprise a first switch, an excess voltage storage, a second switch and an amplifier; the first switch, the excess voltage storage, the second switch and the amplifier are connected in series; one end of the first switch not connected with the excess voltage storage is used as the output end of the noise shaping module; one end of the amplifier not connected with the second switch is used as the input end of the noise shaping module; the amplification multiple of the amplifier is G; the first switch is controlled to be disconnected or closed under the control of the signal clk_ns1; and the second switch is controlled to be disconnected or closed under the control of the signal clk_ns2.

4. The high precision low latency analog-to-digital converter capacitance mismatch self-calibration circuit of claim 2, wherein, The set and quantization unit comprises a SAR logic unit and a comparator. The upper plate of the first CDAC array is connected with the positive input end of the comparator; and the upper plate of the second CDAC array is connected with the negative input end of the comparator. One input end of the SAR logic unit is connected with the output end of the comparator; another input / output end is connected with the calibration and storage unit; one output end is connected with the first CDAC array; and another output end is connected with the second CDAC array. The SAR logic unit is controlled to perform the set operation according to the signal clk_set; and the comparator is controlled to perform the comparison operation according to the signal clk_comp.

5. The high-precision low-latency ADC capacitance mismatch self-calibration circuit according to claim 4, wherein The sampling switch unit is further configured to connect the common-mode voltage V once before each set operation of the mth bit capacitor according to control of the signal clk_sample CM ; The first noise shaping module is further used for storing the amplified G times upper plate excess voltage of the first CDAC array generated in each round of quantization of the m-1th to 1st bit capacitors according to the control of the signal clk_ns1, and then inputting the stored upper plate excess voltage into the first adder according to the control of the signal clk_ns2, so that the first CDAC array is sampled before the next round of quantization. The second noise shaping module is further configured to, according to the signal clk ns1, store the upper plate residue voltage of the second CDAC array after being amplified by G times at the end of each round of quantization of the (m-1)th to 1st capacitors, and then, according to the signal clk ns2, input the stored upper plate residue voltage into the second adder to sample the second CDAC array before the next round of quantization; The comparator is further configured to, according to the signal clk comp, compare the upper plate voltage of the first CDAC array with the upper plate voltage of the second CDAC array after any one of the (m)th capacitor or the (m-1)th to 1st capacitors is subjected to the set operation, obtain a corresponding comparison result, and output the comparison result to the SAR logic unit; The SAR logic unit is further configured to, when calibrating the (m)th capacitor, according to the signal clk set, generate a first calibration code and a second calibration code of the (m)th capacitor according to the comparison result fed back by the comparator in real time, alternately perform two different set operations on the (m)th capacitor according to the first calibration code and the second calibration code of the (m)th capacitor, and after each set operation, perform one round of quantization of the (m-1)th to 1st capacitors in combination with the comparator, the first CDAC array and the second CDAC array, and convert the comparison result fed back by the comparator in real time into a calibration code of the (m-1)th to 1st capacitors and send the calibration code to the calibration and storage unit until p rounds of quantization of the (m-1)th to 1st capacitors are completed under each set operation.

6. The high-precision low-latency ADC capacitor mismatch self-calibration circuit according to claim 5, characterized in that, The SAR logic unit is further configured to, according to the comparison result fed back by the comparator, generate a jth calibration code of the (m)th capacitor, generate a jth control code of the (m)th capacitor according to the jth calibration code of the (m)th capacitor, perform a set-1 operation or a set-0 operation on the (m)th capacitor according to the jth control code of the (m)th capacitor, and then perform one round of quantization of the (m-1)th to 1st capacitors in combination with the comparator, the first CDAC array and the second CDAC array, in the process of which, the comparison result after the set-1 operation or the set-0 operation on the (m)th capacitor is received, and when the received comparison result is 1, 1 is taken as the calibration code of the (m-1)th capacitor, and when the received comparison result is 0, -1 is taken as the calibration code of the (m-1)th capacitor, and the calibration code of the (m-1)th capacitor is sent to the calibration and storage unit, and the comparison result after the set-1 operation on the (m)th capacitor is also sent to the first CDAC array and the second CDAC array; j is a positive integer, and j is 1 to 2p. The first CDAC array and the second CDAC array are further configured to perform a 0-setting operation on the (m-1)th capacitor when the comparison result of the comparator after the 1-setting operation on the mth capacitor is 1, or perform a 1-setting operation on the (m-1)th capacitor otherwise. The comparator is further configured to generate a comparison result of the (m-1)th capacitor after the 1-setting or 0-setting operation and send the comparison result to the SAR logic unit. The SAR logic unit is further configured to receive the comparison result of the (m-1)th capacitor after the 1-setting or 0-setting operation from the comparator, continue to generate a calibration code of an (m-2)th capacitor according to the received comparison result, send the calibration code of the (m-2)th capacitor to the calibration and storage unit, and send the comparison result of the (m-1)th capacitor after the 1-setting or 0-setting operation from the comparator to the first CDAC array and the second CDAC array, so that the first CDAC array and the second CDAC array set the (m-2)th capacitor, and the iteration continues until the (m-1)th to the first capacitor are set once in combination with the comparator, the first CDAC array and the second CDAC array, and the round of quantization of the (m-1)th to the first capacitor is completed, thereby obtaining the calibration code of the (m-1)th to the first capacitor generated by the round of quantization.

7. The high precision low latency analog-to-digital converter capacitance mismatch self-calibration circuit of claim 4, wherein, The calibration and storage unit comprises a calibration logic unit and a memory. The calibration logic unit has one input / output end connected to the input / output end of the SAR logic unit and another input / output end connected to one input / output end of the memory, and is configured to receive the calibration code generated by the SAR logic unit and the weight and the amplification factor G of the (m-1)th to the first capacitor stored in the memory according to the control of the signal clk_cal, calculate the weight of the mth capacitor according to the received calibration code, the weight of the (m-1)th to the first capacitor and the amplification factor G, and store the weight of the mth capacitor in the memory.

8. The high precision low latency analog-to-digital converter capacitance mismatch self-calibration circuit of claim 3, wherein, The excess removal unit comprises a third switch and a fourth switch. One end of the third switch is connected to one end of the first switch in the first noise shaping module and the excess voltage storage, and the other end is grounded. One end of the fourth switch is connected to one end of the first switch in the second noise shaping module and the excess voltage storage, and the other end is grounded. The third switch and the fourth switch are simultaneously opened or closed under the control of the signal clk_reset.

9. A high-precision low-latency analog-to-digital converter capacitance mismatch self-calibration method, characterized in that, The high-precision low-latency analog-to-digital converter capacitor mismatch self-calibration circuit is implemented by using the high-precision low-latency analog-to-digital converter capacitor mismatch self-calibration circuit according to any one of the preceding claims, and the self-calibration circuit comprises a CDAC array, and each CDAC array comprises M main capacitors. An excess removal step: removing the stored upper plate excess voltage of each CDAC array. The first sampling step: each CDAC array is used to sample the common-mode voltage V CM sample the stored upper plate residual voltage, and then compare the voltages of the upper plates of different CDAC arrays to obtain a first comparison result; m is a positive integer, the value of m is a preset integer x to M-1, and x is a first preset positive integer; wherein, when the first sampling step is performed for the first time, the voltage value obtained after sampling the stored upper plate residual voltage is 0; The first setting step: generating the first calibration code of the mth capacitor according to the first comparison result, generating the first control code of the mth capacitor according to the first calibration code of the mth capacitor, and setting 1 to the mth capacitor according to the first control code of the mth capacitor; The first quantization step: after setting 1 to the mth capacitor, quantizing the m-1th to the 1st capacitor for one round, storing the upper plate residual voltage amplified by G times after the round quantization, and obtaining the calibration code of the m-1th to the 1st capacitor generated by the round quantization; The second sampling step: using each CDAC array to sample the common-mode voltage V CM sample once, sample the stored anode excess voltage at the same time, then compare the voltages of the anodes of different CDAC arrays to obtain a second comparison result; The second setting step: generating the second calibration code of the mth capacitor according to the second comparison result, generating the second control code of the mth capacitor according to the second calibration code of the mth capacitor, and setting 0 to the mth capacitor according to the second control code of the mth capacitor; The second quantization step: after setting 0 to the mth capacitor, quantizing the m-1th to the 1st capacitor for one round, storing the upper plate residual voltage amplified by G times after the round quantization, and obtaining the calibration code of the m-1th to the 1st capacitor generated by the round quantization; Returning to the first sampling step to continue execution until the first sampling step to the second quantization step are executed p times, and the calibration code of the m-1th to the 1st capacitor generated by each round quantization under setting 0 and setting 1 to the mth capacitor is obtained; Based on the weights of the m-1th to the 1st capacitor, the amplification multiple G, and the calibration code of the m-1th to the 1st capacitor generated by each round quantization under setting 0 and setting 1 to the mth capacitor, the weight of the mth capacitor is determined, and the calibration of the mth capacitor is completed.

Images