A current folding calibration method and system for a digital-to-analog converter

Abstract

The present invention discloses a current folding calibration method and system for a digital-to-analog converter, and belongs to the technical field of DAC calibration. The present invention reduces the requirement for the gate area of ​​a current source, and by folding the working current, ensures that the current value of the middle current unit selected after folding is half of the current value of the remaining two-by-two addition units, and the difference between the current values ​​of each two-by-two addition unit is reduced, thereby improving the problem of DAC performance degradation caused by current deviation; it can reduce the system deviation and random deviation caused by process problems such as doping concentration, edge effect, and temperature gradient, and each working current will maintain the same comparator deviation, which can reduce the system deviation caused by the comparator deviation, and save the relevant register value in the storage module, and read out the setting before working, which will not increase the working current.

Description

Technical Field

[0001] The present invention relates to the technical field of DAC calibration, and in particular to a current folding calibration method and system for a digital-to-analog converter. Background Art

[0002] Information in the world mainly exists in analog form, rather than discrete digital signals. Therefore, when processing information, tools are needed to build a bridge for signal transmission between analog and digital, and digital-to-analog converters (DACs) are the tools that play a role in this. For example, in wired or wireless communications, video signal processing, direct digital signal synthesis, etc., the performance of high-speed and high-precision converters largely determines the performance of the entire system. In the field of high-speed and high-precision communications, the performance of the converter may even become a bottleneck for the overall performance of the system. Therefore, both in academia and industry, research on converter performance has always been a hot topic.

[0003] In the CMOS process, due to device mismatch, uneven doping concentration distribution, uneven temperature distribution, IR voltage drop and other process manufacturing reasons, these non-ideal factors affect the matching characteristics of the DAC and have a relatively large impact on the performance of the DAC. In recent years, with the continuous development of semiconductor technology, the characteristic size of transistors has become smaller and smaller. The reduction in device size has enabled DAC to have a faster conversion frequency and a larger signal bandwidth. However, the power supply voltage is also getting lower and lower under small-size processes, and the secondary effect of the device is becoming more and more prominent, resulting in the increasing difficulty of designing high-speed and high-precision DACs.

[0004] The performance of the DAC can be optimized by improving the matching accuracy of the current source. Increasing the size of the transistor is a way to improve the matching accuracy of the current source, making the current mirror replication more accurate. The random deviation of the DAC caused by process errors such as doping concentration deviation during the manufacturing process can be reduced by optimizing the layout. As the requirements for DAC accuracy and speed become higher and higher, it is very difficult to achieve such high matching requirements through the above methods. Therefore, the use of current calibration technology in DAC design has become an increasingly common approach.

[0005] Increasing the size of transistors can improve the matching accuracy of the current source and thus improve the static performance of the DAC. However, as the chip area becomes smaller and smaller, the gate area of ​​the current source becomes more important for DAC design. In addition, excessive transistor size will cause more serious parasitic and gradient effects, resulting in reduced SFDR at high frequencies. In the layout, measures such as adjusting the transistor layout and adding dummy tubes can be used to optimize the matching situation, but the layout optimization method has limited effect on eliminating matching deviations caused by process manufacturing problems such as uneven doping concentration, uneven temperature distribution, and IR voltage drop. Therefore, it is urgent to design a calibration method for high-precision DAC matching performance. Summary of the invention

[0006] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a current folding calibration method and system for a digital-to-analog converter, which can combine current sources into a binary weighted array based on current comparison to achieve matching performance of a high-precision DAC.

[0007] In order to solve the above technical problems, the present invention is implemented by adopting the following technical solutions:

[0008] In one aspect, the present invention provides a current folding calibration method for a digital-to-analog converter, comprising:

[0009] The working current of the lower N bits is added to the working current of the least significant bit to form the most significant bit ideal current, and the most significant bit ideal current is compared with the reference current to obtain a first comparison result; according to the first comparison result, the reference current is calibrated to obtain the calibrated reference current and its corresponding DAC register value; wherein N≥2;

[0010] Compare the most significant bit operating current instead of the most significant bit ideal current with the calibrated reference current to obtain a second comparison result; calibrate the most significant bit operating current according to the second comparison result to obtain the calibrated most significant bit operating current and its corresponding DAC register value;

[0011] Sorting the most significant bit operating current of each channel after calibration to obtain the sorted most significant bit operating current;

[0012] Select the second one after sorting M-1 The working current of the most significant bit of the first path is taken as an independent bit in the high M bits, and the working current of the most significant bit of the first path after sorting is combined with the working current of the most significant bit of the second path after sorting. M -1 channel most significant bit working current is added, the sorted second channel most significant bit working current is added to the sorted second M - The operating currents of the most significant bits of the two channels are added together, and the operating current of the most significant bit of the third channel after sorting is added together with the operating current of the most significant bit of the second channel after sorting. M- Add the working current of the most significant bit of the 3 channels, and so on, until the second one after sorting M-1 -1 channel most significant bit working current and the sorted 2nd M-1 The +1 most significant bit working current is added to obtain the current source combination after folding calibration; wherein M≥2.

[0013] The principle of folding the working current is that the current value of the middle current unit selected after folding is half of the current value of the remaining two-by-two addition units, and the difference between the current values ​​of each two-by-two addition unit is reduced, thereby improving the DAC performance degradation problem caused by current deviation.

[0014] Optionally, the step of determining the calibrated reference current and its corresponding DAC register value includes:

[0015] Calibrate the reference current according to a preset first calibration number to obtain multiple reference currents and their corresponding DAC register values;

[0016] An average value of the DAC register values ​​corresponding to the multiple reference currents is taken as the DAC register value corresponding to the calibrated reference current.

[0017] The purpose of repeatedly taking the average value is to avoid random problems in the comparison process, affect the comparison results, and introduce new random errors to the DAC as a whole.

[0018] Optionally, the step of determining the calibrated most significant bit operating current and its corresponding DAC register value includes:

[0019] Calibrate the most significant bit operating current of the nth channel according to a preset second calibration number of times to obtain multiple most significant bit operating currents of the nth channel and their corresponding DAC register values;

[0020] The average value of the DAC register values ​​corresponding to the most significant bit working current of the nth channel is taken as the DAC register value corresponding to the most significant bit working current of the nth channel after calibration; where n≤2 M -1.

[0021] Optionally, also include:

[0022] Re-ordering the most significant bit operating current of each channel after calibration to obtain the re-ordered most significant bit operating current;

[0023] Select the second after reordering M-2 The working current of the most significant bit of the first path is taken as an independent bit in the high M-1 bits, and the working current of the most significant bit of the first path after reordering is combined with the working current of the most significant bit of the second path after reordering. M-1-1 most significant bit operating current is added, the reordered second most significant bit operating current is added to the reordered second M-1 - Add the operating currents of the most significant bits of the two channels, and the operating current of the most significant bit of the third channel after reordering and the operating current of the most significant bit of the second channel after reordering M-1 -3 most significant bit working currents are added, and so on, until the second after reordering M-2 -1 channel most significant bit operating current and reordered second M-2 +1 channel most significant bit working current is added;

[0024] The process is repeated until a preset number of folding times is reached, and a current source combination after folding calibration is obtained.

[0025] Optionally, the folded and calibrated current source combination obtained by folding once includes a first current source and two M -1 - 1 second current source, the current value of the second current source is twice the current value of the first current source.

[0026] Optionally, a comparator is used to compare the most significant bit ideal current with a reference current, the most significant bit operating current is used instead of the most significant bit ideal current to compare with the calibrated reference current, and each calibrated most significant bit operating current is sorted.

[0027] Optionally, the DAC register value corresponding to the calibrated reference current, the DAC register value corresponding to the calibrated most significant bit operating current, and the current source combination after the folding calibration are respectively saved in a storage module.

[0028] On the other hand, the present invention provides a current folding calibration system for a digital-to-analog converter, the system adopts the method described in the first aspect to perform current folding calibration, the system includes a main DAC, a correction DAC, a reference DAC, a comparator and a digital calibration logic circuit;

[0029] The main DAC and the correction DAC are connected to the first input terminal of the comparator, the reference DAC is connected to the second input terminal of the comparator, and the output terminal of the comparator is connected to the digital calibration logic circuit.

[0030] Optionally, the operating current of the lower N bits and the least significant bit operating current are both derived from the main DAC, the reference current is derived from the reference DAC, and the most significant bit operating current is derived from the main DAC and the correction DAC;

[0031] The reference DAC is used to: control a reference current;

[0032] The modified DAC is used to: control the most significant bit operating current;

[0033] The comparator is used to: compare the most significant bit ideal current with the reference current to obtain a first comparison result; replace the most significant bit ideal current with the most significant bit working current and compare it with the calibrated reference current to obtain a second comparison result; sort the calibrated most significant bit working currents of each channel to obtain the sorted most significant bit working currents;

[0034] The digital calibration logic circuit is used to: calibrate the reference current according to the first comparison result to obtain the DAC register value corresponding to the calibrated reference current; calibrate the most significant bit working current according to the second comparison result to obtain the calibrated most significant bit working current and its corresponding DAC register value; select the sorted second M-1 The working current of the most significant bit of the first path is taken as an independent bit in the high M bits, and the working current of the most significant bit of the first path after sorting is combined with the working current of the most significant bit of the second path after sorting. M -1 channel most significant bit working current is added, the sorted second channel most significant bit working current is added to the sorted second M - The operating currents of the most significant bits of the two channels are added together, and the operating current of the most significant bit of the third channel after sorting is added together with the operating current of the most significant bit of the second channel after sorting. M - Add the working current of the most significant bit of the 3 channels, and so on, until the second one after sorting M-1 -1 channel most significant bit working current and the sorted 2nd M-1 The +1 most significant bit operating current is added to obtain the current source after folding calibration.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] The present invention reduces the requirement on the gate area of ​​the current source. By folding the working current, it is ensured that the current value of the middle current unit selected after folding is half of the current value of the other two-by-two adding units. The difference between the current values ​​of each two-by-two adding unit is reduced, and the problem of DAC performance degradation caused by current deviation is improved; the system deviation and random deviation caused by process problems such as doping concentration, edge effect, temperature gradient, etc. can be reduced. The same comparator deviation is maintained between each working current, which can reduce the system deviation caused by comparator deviation. The relevant register value is stored in the storage module, and the setting is read out before working, which will not increase the working current; the system only uses the minimum analog circuit and some digital circuits, and the analog circuit only adds a comparator and a correction DAC and a reference DAC circuit, and the digital logic process is not complicated. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1FIG. 1 is a flow chart of a current folding calibration method for a digital-to-analog converter according to an embodiment of the present invention;

[0038] Figure 2 FIG. 1 is a schematic structural diagram of a current folding calibration system for a digital-to-analog converter according to an embodiment of the present invention;

[0039] Figure 3 The figure shows a schematic diagram of the structure of the most significant bit working current after calibration in one embodiment of the present invention;

[0040] Figure 4 The figure shows a schematic diagram of the structure of the most significant bit operating current after sorting in one embodiment of the present invention;

[0041] Figure 5 Shown is a schematic structural diagram of a folded and calibrated current source combination in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations on the technical solution of the present invention. The embodiments of the present invention and the technical features in the embodiments may be combined with each other unless there is a conflict.

[0043] The term "and / or" is only a description of the association relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " generally indicates that the related objects are in an "or" relationship.

[0044] Example 1

[0045] like Figure 1 As shown, this embodiment introduces a current folding calibration method for a digital-to-analog converter, comprising the following steps:

[0046] Step 1: Add the working current of the lower N bits to the working current of the least significant bit (LSB) to form the most significant bit (MSB) ideal current, and compare the MSB ideal current with the reference current to obtain a first comparison result; wherein N≥2;

[0047] According to the first comparison result, the reference current is calibrated to obtain a DAC register value corresponding to the calibrated reference current, and the step of determining the DAC register value corresponding to the calibrated reference current includes:

[0048] The reference current is calibrated according to a preset first calibration number of times to obtain DAC register values ​​corresponding to a plurality of reference currents; the calibration number of times is controlled by a corresponding register.

[0049] The DAC register values ​​corresponding to multiple reference currents are averaged as the DAC register value corresponding to the calibrated reference current, making the reference current closer to the MSB ideal current. Repeated calibration and averaging are done to avoid random problems in the comparison process, affecting the comparison results, and introducing new random errors to the DAC as a whole.

[0050] When this embodiment is applied, the calibrated reference current can be closer to the MSB ideal current. The reason for comparing all the working currents of the lower N bits plus one LSB working current with the reference current is to reduce the error between the MSB current and the LSB current and reduce the differential nonlinearity (DNL) of the overall circuit. The step of the DAC corresponding to the reference current is as small as possible, and the adjustment range must be guaranteed at the same time, so the resolution is higher than that of the DAC corresponding to the MSB working current, so that the reference current is closer to the MSB ideal current and the error is reduced.

[0051] Step 2: Replace the MSB ideal current with the MSB operating current and compare it with the calibrated reference current to obtain a second comparison result; according to the second comparison result, calibrate the MSB operating current to obtain the calibrated MSB operating current and its corresponding DAC register value, and the steps of determining the calibrated MSB operating current and its corresponding DAC register value include:

[0052] The n-th MSB operating current is calibrated according to a preset second calibration number of times to obtain multiple MSB operating currents of the n-th channel and their corresponding DAC register values; the calibration number of times is controlled by the corresponding register.

[0053] The average value of the DAC register values ​​corresponding to the multiple MSB working currents of the nth channel is taken as the DAC register value corresponding to the MSB working current of the nth channel after calibration; where n≤2 M -1. This makes the calibrated MSB operating current of each channel consistent with the calibrated reference current.

[0054] Step 3: The circuit before folding adopts segmented coding, the high M bits are thermometer coding, the low N bits are binary coding, and the high M bits are composed of 2 M The lower N bits are composed of N current units. The current source of the lower N bits plus an LSB working current is theoretically equal to the current value of a current unit of the M-bit thermometer code, which is the MSB ideal current.

[0055] The calibrated MSB operating currents of each channel are sorted to obtain sorted MSB operating currents. In this embodiment, the sorted MSB operating currents are from 1 to 2. M -1.

[0056] Select the second one after sorting M-1 The MSB working current of the first MSB after sorting is used as an independent bit in the high M bits, and the working current of the first MSB after sorting is compared with the working current of the second MSB after sorting. M -1 MSB operating current is added, and the sorted second MSB operating current is added to the sorted second M - The operating currents of the most significant bits of the two channels are added together, and the operating current of the most significant bit of the third channel after sorting is added together with the operating current of the most significant bit of the second channel after sorting. M - Add the working current of the most significant bit of the 3 channels, and so on, until the second one after sorting M-1 -1 MSB operating current and the sorted 2 M-1 The +1 MSB operating current is added to obtain a current source combination after folding calibration; wherein M≥2.

[0057] This is to complete a weighted operation on the thermometer code, fold it once as a whole, and the circuit becomes a thermometer code with the upper M-1 bits and a binary code with the lower N+1 bits. The folded and calibrated current source obtained by folding once includes a first current source and 2 M-1 - 1 second current source, the current value of the second current source is twice the current value of the first current source.

[0058] Re-order each MSB operating current after calibration to obtain the re-ordered MSB operating current.

[0059] Select the second after reordering M-2 The MSB operating current of the first MSB after reordering is used as an independent bit in the high M-1 bits, and the MSB operating current of the first MSB after reordering is combined with the MSB operating current of the second MSB after reordering. M-1 -1 MSB operating current is added, and the reordered second MSB operating current is added to the reordered second M-1 - Add the operating currents of the most significant bits of the two channels, and the operating current of the most significant bit of the third channel after reordering and the operating current of the most significant bit of the second channel after reordering M-1 -3 most significant bit working currents are added, and so on, until the second after reordering M-2 -1 MSB operating current and reordered 2 M-2 +1 MSB operating current is added.

[0060] The process is repeated in this way until the preset folding times are reached to obtain the current source combination after folding calibration. In this embodiment, the maximum folding times is M-1 times.

[0061] After folding M-1 times, the circuit becomes a thermometer code with the high 1 bit and a binary code with the low N+M-1 bits. The principle of folding the working current is that the current value of the middle current unit selected after folding is half of the current value of the remaining two-by-two addition units, and the difference between the current values ​​of each two-by-two addition unit is reduced, which improves the DAC performance degradation problem caused by current deviation.

[0062] In a specific embodiment, Figure 3 The figure shows the MSB operating current after 7-channel calibration, taking the MSB operating current after 7-channel calibration as an example.

[0063] First, Figure 4 As shown, the 7 calibrated MSB operating currents are sorted to obtain the sorted MSB operating currents, either from large to small or from small to large.

[0064] like Figure 5 As shown, the sorted 4th MSB working current is selected as the independent bit in the high M bits, the sorted 1st MSB working current is added to the sorted 7th MSB working current, the sorted 2nd MSB working current is added to the sorted 6th MSB working current, and the sorted 3rd MSB working current is added to the sorted 5th MSB working current to obtain the current source after folding calibration. At this time, the current value of the sorted 4th MSB working current unit is half of the current values ​​of the remaining two-by-two addition units, and the difference between the current values ​​of each two-by-two addition unit is reduced, thereby improving the problem of DAC performance degradation caused by current deviation.

[0065] In this embodiment, a comparator is used to compare the MSB ideal current with a reference current, to replace the MSB ideal current with an MSB operating current and compare it with a calibrated reference current, and to sort each calibrated MSB operating current.

[0066] After completion, the DAC register value corresponding to the calibrated reference current, the DAC register value corresponding to the calibrated working current and the folded calibrated current source combination are respectively saved to the storage module, and the contents of the storage module can be directly imported during operation.

[0067] Example 2

[0068] On the basis of Example 1, Figure 2 As shown, this embodiment introduces a current folding calibration system for a digital-to-analog converter, the system adopts the method described in Example 1 to perform current folding calibration, and the system includes a main DAC, a correction DAC, a reference DAC, a comparator, a digital calibration logic circuit and an OTP circuit;

[0069] The main DAC and the correction DAC are connected to the first input terminal of the comparator, the reference DAC is connected to the second input terminal of the comparator, the output terminal of the comparator is connected to the input terminal of the digital calibration logic circuit, and the output terminal of the digital calibration logic circuit is connected to the OTP circuit.

[0070] The working current of the lower N bits and the least significant bit working current are both derived from the main DAC, the reference current is derived from the reference DAC, and the most significant bit working current is derived from the main DAC and the correction DAC;

[0071] The reference DAC is used to control the reference current, and the correction DAC is used to control the MSB working current, so that the MSB working current is consistent with the reference current, and each current has a corresponding register address;

[0072] The comparator is used to: compare the MSB ideal current with the reference current to obtain a first comparison result; replace the MSB ideal current with the MSB working current and compare it with the calibrated reference current to obtain a second comparison result; sort each calibrated MSB working current to obtain a sorted MSB working current;

[0073] The digital calibration logic circuit is used to: calibrate the reference current according to the first comparison result to obtain the calibrated reference current and its corresponding DAC register value; calibrate the MSB working current according to the second comparison result to obtain the calibrated MSB working current and its corresponding DAC register value; select the sorted second M-1 The MSB working current of the first MSB after sorting is used as an independent bit in the high M bits, and the working current of the first MSB after sorting is compared with the working current of the second MSB after sorting. M -1 MSB operating current is added, and the sorted second MSB operating current is added to the sorted second M - The operating currents of the most significant bits of the two channels are added together, and the operating current of the most significant bit of the third channel after sorting is added together with the operating current of the most significant bit of the second channel after sorting. M - Add the working current of the most significant bit of the 3 channels, and so on, until the second one after sorting M-1 -1 MSB operating current and the sorted 2 M-1 The +1 MSB operating current is added to obtain the current source after folding calibration. That is, the comparison result from the comparator is received to adjust the correction DAC register value and the reference DAC register value, sort and perform binary weighting.

[0074] The OTP circuit is a storage module, which is used to: save the DAC register value corresponding to the calibrated reference current, the DAC register value corresponding to the calibrated MSB working current and the current source combination after the folding calibration, that is, the result of the correction DAC register value, the reference DAC register value and the current source folding combination.

[0075] The working principle of current calibration is to compensate the main DAC by adjusting the correction DAC. In a specific embodiment, the step of the correction DAC is 0.5LSB, the resolution is 8 bits, and the DNL after the comparison is completed is ≤±0.25LSB; the calibration range is ±64LSB.

[0076] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0077] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0078] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0079] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0080] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims

1. A current folding calibration method for a digital-to-analog converter, characterized in that: include: Adding the working current of the lower N bits to the working current of the least significant bit forms an ideal current of the most significant bit, and comparing the ideal current of the most significant bit with the reference current to obtain a first comparison result; According to the first comparison result, calibrate the reference current to obtain a calibrated reference current and a corresponding DAC register value; Where N≥2; The most significant bit working current is used to replace the most significant bit ideal current and is compared with the calibrated reference current to obtain a second comparison result; According to the second comparison result, calibrate the most significant bit operating current to obtain the calibrated most significant bit operating current and its corresponding DAC register value; Sorting the most significant bit operating current of each channel after calibration to obtain the sorted most significant bit operating current; Select the second one after sorting M-1 The working current of the most significant bit of the first path is taken as an independent bit in the high M bits, and the working current of the most significant bit of the first path after sorting is combined with the working current of the most significant bit of the second path after sorting. M -1 channel most significant bit working current is added, the sorted second channel most significant bit working current is added to the sorted second M - The operating currents of the most significant bits of the two channels are added together, and the operating current of the most significant bit of the third channel after sorting is added together with the operating current of the most significant bit of the second channel after sorting. M - Add the working current of the most significant bit of the 3 channels, and so on, until the second one after sorting M -1 -1 channel most significant bit working current and the sorted 2nd M-1 The +1 most significant bit working current is added to obtain the current source combination after folding calibration; wherein M≥2.

2. The current folding calibration method of a digital-to-analog converter according to claim 1, characterized in that: The step of determining the calibrated reference current and its corresponding DAC register value comprises: Calibrate the reference current according to a preset first calibration number to obtain multiple reference currents and their corresponding DAC register values; An average value of the DAC register values ​​corresponding to the multiple reference currents is taken as the DAC register value corresponding to the calibrated reference current.

3. The current folding calibration method of a digital-to-analog converter according to claim 1, characterized in that: The step of determining the calibrated most significant bit operating current and its corresponding DAC register value comprises: Calibrate the most significant bit operating current of the nth channel according to a preset second calibration number of times to obtain multiple most significant bit operating currents of the nth channel and their corresponding DAC register values; The average value of the DAC register values ​​corresponding to the most significant bit working current of the nth channel is taken as the DAC register value corresponding to the most significant bit working current of the nth channel after calibration; where n≤2 M -1.

4. The current folding calibration method of a digital-to-analog converter according to claim 1, characterized in that: Also includes: Re-ordering the most significant bit operating current of each channel after calibration to obtain the re-ordered most significant bit operating current; Select the second after reordering M-2 The working current of the most significant bit of the first path is taken as an independent bit in the high M-1 bits, and the working current of the most significant bit of the first path after reordering is combined with the working current of the most significant bit of the second path after reordering. M-1 -1 most significant bit operating current is added, the reordered second most significant bit operating current is added to the reordered second M-1 - Add the operating currents of the most significant bits of the two channels, and the operating current of the most significant bit of the third channel after reordering and the operating current of the most significant bit of the second channel after reordering M-1 -3 most significant bit working currents are added, and so on, until the second after reordering M-2 -1 channel most significant bit operating current and reordered second M-2 +1 channel most significant bit working current is added; The process is repeated until a preset number of folding times is reached, and a current source combination after folding calibration is obtained.

5. The current folding calibration method of a digital-to-analog converter according to claim 1, characterized in that: The folded and calibrated current source combination obtained by folding once includes a first current source and two M-1 - 1 second current source, the current value of the second current source is twice the current value of the first current source.

6. The current folding calibration method of a digital-to-analog converter according to claim 1, characterized in that: By using a comparator, the most significant bit ideal current is compared with a reference current, the most significant bit operating current is replaced by the most significant bit ideal current and compared with the calibrated reference current, and each calibrated most significant bit operating current is sorted.

7. The current folding calibration method of a digital-to-analog converter according to claim 1, characterized in that: The DAC register value corresponding to the calibrated reference current, the DAC register value corresponding to the calibrated most significant bit working current, and the current source combination after the folding calibration are respectively saved in the storage module.

8. A current folding calibration system for a digital-to-analog converter, characterized in that: The system adopts the method described in any one of claims 1 to 7 to perform current folding calibration, and the system includes a main DAC, a correction DAC, a reference DAC, a comparator and a digital calibration logic circuit; The main DAC and the correction DAC are connected to the first input terminal of the comparator, the reference DAC is connected to the second input terminal of the comparator, and the output terminal of the comparator is connected to the digital calibration logic circuit.

9. The current folding calibration system for a digital-to-analog converter according to claim 8, characterized in that: The working current of the lower N bits and the least significant bit working current are both derived from the main DAC, the reference current is derived from the reference DAC, and the most significant bit working current is derived from the main DAC and the correction DAC; The reference DAC is used to: control a reference current; The modified DAC; Used for: controlling the most significant bit operating current; The comparator is used to compare the most significant bit ideal current with a reference current to obtain a first comparison result; The most significant bit working current is used to replace the most significant bit ideal current and is compared with the calibrated reference current to obtain a second comparison result; Sorting the most significant bit operating current of each channel after calibration to obtain the sorted most significant bit operating current; The digital calibration logic circuit is used to: calibrate the reference current according to the first comparison result to obtain the calibrated reference current and its corresponding DAC register value; According to the second comparison result, the most significant bit operating current is calibrated to obtain the calibrated most significant bit operating current and its corresponding DAC register value; the sorted second M-1 The working current of the most significant bit of the first path is taken as an independent bit in the high M bits, and the working current of the most significant bit of the first path after sorting is combined with the working current of the most significant bit of the second path after sorting. M -1 channel most significant bit working current is added, the sorted second channel most significant bit working current is added to the sorted second M - The operating currents of the most significant bits of the two channels are added together, and the operating current of the most significant bit of the third channel after sorting is added together with the operating current of the most significant bit of the second channel after sorting. M - Add the working current of the most significant bit of the 3 channels, and so on, until the second one after sorting M-1 -1 channel most significant bit working current and the sorted 2nd M-1 The +1 most significant bit operating current is added to obtain the current source after folding calibration.

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