Circuit module, data receiving device and electronic device for clock signal detection and adjustment

Abstract

The present application relates to a circuit module for clock signal detection and adjustment, including: a clock signal interface unit, configured to obtain clock adjustment parameters and output a data acquisition clock signal; a phase-locked unit, configured to perform frequency processing on the received internal clock signal to adjust the frequency range of the external clock signal that the circuit module can detect; a detection unit, configured to detect the external clock signal to obtain indication information of the external clock signal, the indication information including frequency information and phase information; and an adjustment unit, configured to generate a data acquisition clock signal based on the clock adjustment parameters and the indication information. The present application also provides a data receiving device and an electronic device. The present application realizes the integration of the detection and adjustment functions of the external clock signal within an IP, and can adjust and detect the external clock signal in a large range with high precision and flexibility, occupies less chip logic resources, has a simple and clear structure, and has good reusability.

Description

Technical Field

[0001] The present application relates to a clock signal device, and in particular to a circuit module, a data receiving device and an electronic device for realizing automatic detection and adjustment of a clock signal. Background Art

[0002] In today's Internet society, the demand and requirements for data transmission volume, transmission distance and signal stability are also increasing. When conducting long-distance communication, simply transmitting data signals often leads to errors in signal acquisition and decoding because the receiving end has no benchmark for signal acquisition and processing, affecting the communication quality. Or in the field of electronic reconnaissance, multiple radar antennas detect the same signal, and the detected signal needs to be transmitted to the same host for processing, which requires a unified clock signal to synchronize multiple signals.

[0003] At present, the external clock signal checking and switching functions are widely used in analog to digital converters (ADC), digital to analog converters (DAC), clock data recovery circuits (CDR) and system on chip (SOC), and the performance of external clock signal processing will affect the overall performance of the circuit.

[0004] The external clock signal adjustment device in the prior art mainly relies on hardware circuits to detect or adjust the clock signal. The detected clock signal frequency is usually relatively single, and only fixed clock signals can be detected; for adjusting the clock signal, the existing design has a small adjustment range and cannot take into account both the large-scale frequency adjustment of the clock signal and the high-precision adjustment of the phase.

[0005] Therefore, there is an urgent need for a device that can detect and adjust clock signals. Summary of the invention

[0006] In view of the technical problems existing in the prior art, the present application proposes a device and a data receiving device that can realize the detection and adjustment of clock signals.

[0007] On the one hand, the present application proposes a circuit module for clock signal detection and adjustment, including: a clock signal interface unit, configured to obtain clock adjustment parameters and output a data acquisition clock signal; a phase-locked unit, configured to perform frequency processing on the received internal clock signal to adjust the frequency range of the external clock signal that can be detected by the circuit module; a detection unit, configured to detect the external clock signal to obtain indication information of the external clock signal, the indication information including frequency information and phase information; and an adjustment unit, configured to generate the data acquisition clock signal based on the clock adjustment parameters and the indication information.

[0008] In one embodiment, the clock signal interface unit is further configured to obtain a mode control signal so that the circuit module is in a first mode or a second mode, wherein, when the circuit module is in the first mode, the adjustment unit uses the clock signal specified by the clock adjustment parameter as the data acquisition clock signal; when the circuit module is in the second mode, the adjustment unit uses the internal clock signal as the data acquisition clock signal by default, and after detecting the external clock signal and the stabilization time of the external clock signal reaches a first threshold time, the adjustment unit uses the external clock signal as the data acquisition clock signal.

[0009] In one embodiment, the detection unit is further configured as follows: if the external clock signal is used as the data acquisition clock signal or in the second mode, the detection unit detects whether there is a first type of transition in the external clock signal, and if the first type of transition is not detected within the second threshold time, enters the next detection cycle; if the first type of transition is detected, the first level is counted, and when the second type of transition is detected, the second level is counted, and based on the counting results of the first and second levels, the frequency and phase of the external clock signal are determined, wherein the first level and the second level correspond to the first type of transition and the second type of transition, respectively.

[0010] In one embodiment, the clock adjustment parameter includes a gain coefficient, and the adjustment unit is further configured to: adjust the voltage of the external clock signal based on the gain coefficient to adjust the phase of the external clock signal, wherein the gain coefficient includes a proportional gain coefficient and / or an integral gain coefficient.

[0011] In one embodiment, the clock adjustment parameter includes a frequency coefficient, and the adjustment unit is further configured to: adjust the frequency of the external clock signal based on the frequency coefficient, wherein the frequency coefficient includes a multiplication coefficient or a division coefficient.

[0012] In one embodiment, the clock adjustment parameter includes a clock signal adjustment value, and the adjustment unit is further configured to: determine the number of clock signal cycles required to be adjusted in each data acquisition cycle based on the clock signal adjustment value, and then adjust the clock signal through multiple data acquisition cycles.

[0013] The present application also proposes a data receiving device, comprising: a communication interface module, configured to obtain control instructions from a host computer and determine clock signal section parameters based on the control instructions; a control module, coupled to the communication interface module, configured to send the clock adjustment parameters from the communication interface module; a circuit module as in any of the preceding items, configured to generate the data acquisition clock signal based on the clock adjustment parameters and the received clock signal; a data processing module, configured to obtain the control instructions, and based on the control instructions and the data acquisition clock signal, process the data, and transmit the processed data and the data acquisition clock signal to the communication interface module.

[0014] In one embodiment, the communication interface module includes at least one of the following interfaces: SPI, IIC, UART and ETH.

[0015] In one embodiment, the communication interface module further includes a filtering unit.

[0016] The present application also proposes an electronic device, comprising: an antenna, and a data receiving device as described in any one of the above items, which is coupled to the antenna to obtain data and clock signals.

[0017] By implementing the technical solution of the present invention, the functions of detecting and adjusting the external clock signal are integrated within an IP, and the external clock signal can be adjusted and detected over a large range with high precision and flexibility, occupying less chip logic resources, having a simple and clear structure, and good reusability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0019] Figure 1 is a schematic diagram of a clock signal detection and adjustment module according to an embodiment of the present application;

[0020] Figure 2 A flowchart of a clock signal detection and adjustment module according to an embodiment of the present application;

[0021] Figure 3 A schematic diagram of external clock signal detection according to an embodiment of the present application;

[0022] Figure 4is a flow chart of a clock signal adjustment method according to an embodiment of the present application;

[0023] Figure 5 A schematic diagram of a clock signal adjustment process according to another embodiment of the present application;

[0024] Figure 6 Schematic diagram of the structure of a data receiving device according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0026] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0027] The technologies, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods and devices shall be considered as part of the specification. The lines between the units in the drawings are only for the convenience of explanation, indicating that at least the units at both ends of the lines are communicating with each other, and are not intended to limit the unconnected units from being unable to communicate. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the output terminals, and is not configured to limit the two units to only communicate with each other through the signals shown in the figure.

[0028] This application proposes a clock signal detection and adjustment module with strong versatility, which integrates the detection and adjustment functions of external clock signals, and integrates a phase-locked unit, which can adjust and detect external clock signals in a large range, with high precision and flexibility. This module occupies less chip logic resources, has a simple and clear structure, and has good reusability. It can be directly designed as a dedicated chip for use, or it can be used in conjunction with other modules (IP).

[0029] Figure 1is a schematic diagram of a clock signal detection and adjustment module according to an embodiment of the present application. Figure 2 4 is a flowchart of a clock signal detection and adjustment module according to an embodiment of the present application.

[0030] like Figure 1 As shown, the clock signal detection and adjustment module includes: a phase-locked unit 11, configured to perform frequency processing on the received internal clock signal, for example, the frequency of the internal clock signal (INTCLK) can be changed so that the module can detect a larger range of external clock signals (EXTCLK); a detection unit 12, configured to detect whether the external clock signal exists and provide the frequency and phase of the external clock signal; an adjustment unit 13, configured to adjust the received clock signal in response to the control signal control, and generate an adjusted clock signal clk_adj; a clock signal interface unit 14 includes at least a first interface and a second interface, wherein the first interface is used to provide the adjusted clock clk_adj, and the second interface is used to communicate data data with the host computer. The data data here can be a mode control signal or communication data.

[0031] It can be understood that the clock signal detection and adjustment module can be integrated as a circuit module inside an IP, or used as a separate IP, thereby realizing both detection and adjustment functions, and the detectable clock signal frequency range is variable, and the user can control it in real time.

[0032] After acquiring the mode control signal, the clock signal interface unit 14 can make the clock signal detection and adjustment module in the first mode or the second mode. When the clock signal detection and adjustment module is in the first mode, the adjustment unit 13 uses the clock signal specified by the clock adjustment parameter as the data acquisition clock signal. In other words, the mode control signal can be set by the user. For example, in the first mode, the user can specify to use the internal / external clock signal as the data acquisition clock signal; in the second mode, the internal clock signal can be used by default, and when the external clock signal is input and stable, it automatically switches to the external clock signal.

[0033] Combination Figure 2 The working process of the clock signal detection and adjustment module is explained.

[0034] First, execute step S201 to determine the working mode of the clock signal detection and adjustment module. If it is the first mode, which clock signal specified by the clock adjustment parameter is used as the data acquisition clock signal (step S202); if it is the second mode, the detected valid clock signal can be adjusted. For example, the internal clock signal is used by default. After the external clock signal is detected and the stabilization time of the external clock signal reaches the first threshold time (for example, 1s), the adjustment unit adjusts the external clock signal (step S203). It can be understood that the judgment rules in this step can be set according to the application scenario. When an external clock signal is connected, the detection unit 12 can determine whether the external clock signal meets the preset conditions based on the frequency and phase of the external clock signal. If not, the clock signal is adjusted by the adjustment unit 13 based on the preset rules to generate a data acquisition clock signal.

[0035] It can be understood that, corresponding to the selection of different clock signals, the clock signal (clk_adj) output by the adjustment unit 13 can be an internal clock signal, an external clock signal, or an adjusted external clock signal. For example, when the detection unit 12 determines that the external clock signal meets the preset conditions, the external clock signal can be used as a data acquisition clock signal; if it does not meet the conditions, the adjustment unit 13 adjusts the external clock signal based on the preset rules to generate a data acquisition clock signal. The data acquisition and processing module (not shown) collects and processes data according to the data acquisition clock signal provided by the clock signal detection and adjustment module, and sends it to the host computer through the communication interface, and the host computer further analyzes the data, extracts signals, decrypts, etc.

[0036] For external clock signal detection, the present application provides a detection method. Specifically, the frequency and phase of the clock signal can be determined according to the number of rising edges or falling edges detected.

[0037] Figure 3 Schematic diagram of clock signal detection according to an embodiment of the present application.

[0038] As shown in the figure, the rising edge and falling edge of the clock signal can be detected to determine the frequency and phase of the clock signal. The clock signal detection and adjustment module can detect the above clock signal through a counter.

[0039] Specifically, if the rising edge of the clock signal is detected, the first counter starts counting, that is, counting the high level. When counting the high level, the falling edge of the clock signal is always detected. After the falling edge of the clock signal is detected, the low level starts to be counted, that is, the first counter stops counting and the second counter starts counting. When counting the low level again, the rising edge of the clock signal is detected, and the counting of the low level is stopped after the rising edge of the clock signal is detected. For example, the high and low level changes are detected N times (for example, N=3) in a cycle, and the averages of the first counter and the second counter are taken respectively, so that the frequency and phase of the clock signal can be obtained.

[0040] It is understandable that the above detection method can also be implemented in other ways, for example, first measuring N rising edges and then measuring N falling edges, and determining the corresponding frequency and phase through 2N clock signals.

[0041] The present application also proposes a clock signal adjustment method, which is described using ADC as an example. Figure 4 Flow chart of a clock signal adjustment method according to an embodiment of the present application.

[0042] Step S301: determine the adjustment type, if it is frequency division or frequency multiplication adjustment, if so, execute step S302 to divide or multiply the external clock signal, otherwise, execute subsequent steps.

[0043] Step S303: Calculate the number of clock signal cycles z1 that needs to be adjusted in each ADC conversion cycle according to the value x1 that the user needs to adjust. In this step, the number of clock signal cycles y1 corresponding to one ADC conversion cycle is determined according to the preset adjustment conditions, and then the number of clock signal cycles z1 that needs to be adjusted in each ADC conversion cycle is calculated according to the value that the user needs to adjust.

[0044] Step S304: Determine whether the clock signal offset to be adjusted is less than 1 clock signal cycle, that is, one ADC conversion cycle is not enough to adjust one clock signal cycle, or the number of clock signal cycles to be adjusted is not an integer. If not, that is, the number of adjustments is greater than or equal to 1 and is an integer, then execute step S305, and evenly insert the clock signal with a changed frequency within the ADC conversion cycle; if so, execute step S306 to determine whether an integer number (z2) of ADC conversion cycles are required to adjust a clock signal based on the clock signal offset value to be adjusted. If so, execute step S307, use z2 ADC conversion cycles to insert a clock signal with a changed frequency, that is, adjust a clock signal; if not, execute step S308, and determine the number of clock signals for non-integer ADC conversion cycles based on the number of conversion cycles and the adjustment value of the clock signal. Specifically, when the ADC conversion cycle remainder w2 ≥ x1, z4 clock signal cycles are determined based on w2 / x1 (i.e., z31) to adjust one clock signal; otherwise, z4 clock signal cycles are determined based on x1 / w2 (i.e., z32) to adjust one clock signal. In this embodiment, the value of z4 can be determined by formula (1):

[0045] z2 * y1 + z3 = z4 (1)

[0046] In the formula, z3 is determined to be z31 or z32 according to the relationship between x1 and w1.

[0047] The following is an explanation using an ADC system with a main clock signal frequency of 8M as an example.

[0048] For an ADC system with a main clock signal frequency of 8M and an output data rate of 250Hz, the time required to convert one data is 16384 clock signal cycles. Set the number of clock signals to be adjusted x1 to 1340, n to 27 (adjust the output data rate positively by 1340*(7.45)ppb), and the value of y1 to 16384.

[0049] Therefore, after executing step S302, it can be determined that z1 is 0 and w1 is 21954560; by executing step S303, it can be determined that step S304 should be continued, and then z2 is determined to be 6 and w2 is 2490368, that is, 6 ADC conversion cycles are required to adjust a clock signal. Since w2 is greater than x1, the value of z3 is 1858. By executing step S305, it can be determined that z4 is 100162, that is, when the system executes 100162 clock signal cycles, two 16M frequency clock signals are inserted for adjustment.

[0050] By following the above steps, the 250Hz data rate can be adjusted to 1340*(7.45)ppb, and the new data rate is 250*(1+1340*(7.45) / 1000000000)Hz.

[0051] Figure 5 FIG. 1 is a schematic diagram of a clock signal adjustment process according to another embodiment of the present application. In this process, the phase and frequency of the clock signal are processed separately. It is understandable that the frequency can be processed first and then the phase.

[0052] Execute step S401 to determine whether the clock signal needs to be phase adjusted. For example, the adjustment requirement can be adaptively generated according to the application scenario, or the adjustment instruction from the user can be obtained. It can be understood that the adjustment requirement, adjustment instruction, etc. here all include the method and gain coefficient for processing the clock signal. If the clock signal does not need to be phase adjusted, execute step S403.

[0053] When the phase of the clock signal needs to be adjusted, step S402 is performed: the voltage value of the clock signal is calculated and adjusted according to the gain coefficient determined in the previous step, thereby adjusting the phase. The gain coefficient in this step includes a proportional gain coefficient Kp and / or an integral gain coefficient Ki.

[0054] Execute step S403: determine whether the frequency of the clock signal needs to be adjusted at present. Similarly, the adjustment requirements can be adaptively generated according to the application scenario, or the adjustment instructions from the user can be obtained. The adjustment requirements and adjustment instructions here all include the method and frequency coefficient of the clock signal to be processed. If the clock signal does not need to be phase adjusted, execute step S405 to generate a new clock signal according to the new clock signal frequency and the voltage values ​​at different times.

[0055] If the phase of the clock signal needs to be adjusted, step S404 is performed: the frequency of the clock signal is adjusted according to the frequency coefficient. It can be understood that the frequency coefficient can be a multiplication coefficient or a division coefficient.

[0056] Figure 6 Schematic diagram of the structure of a data receiving device according to an embodiment of the present application.

[0057] The data receiving device includes a universal communication interface module 51 , a control module 52 , a clock signal detection and adjustment module 53 , and a data processing module 54 .

[0058] The communication interface module 51 is configured to obtain various working parameters of the working mode of the clock signal detection and adjustment module 53 and the processing mode (such as digital filtering, communication decoding, etc.) of the data processing module 54. After the receiver receives the data signal and the synchronous clock signal from the outside, the clock signal adjustment and detection module 53 detects and adjusts the external clock signal according to the settings, outputs the data sampling clock signal to the data processing module 54 for data collection and processing, and outputs the external clock signal information (current frequency and phase) to the control module 52. The control module 52 and the data processing module 54 then transmit the collected data and external clock signal information through the communication interface module 51.

[0059] In one embodiment, the communication interface module 51 further includes a filtering unit and at least one of the following communication interfaces: SPI, IIC, UART, and ETH.

[0060] The present application also discloses an electronic device, which includes: an antenna and a data receiving device, wherein the data receiving device is coupled to the antenna to obtain data and a clock signal.

[0061] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A circuit module for clock signal detection and adjustment, characterized in that: include: A clock signal interface unit is configured to obtain clock adjustment parameters and output a data acquisition clock signal; a phase-locked unit configured to perform frequency processing on the received internal clock signal to adjust the frequency range of the external clock signal that can be detected by the circuit module; a detection unit, configured to detect the external clock signal to obtain indication information of the external clock signal, wherein the indication information includes frequency information and phase information; as well as, an adjustment unit, configured to generate the data acquisition clock signal based on the clock adjustment parameter and the indication information; The clock signal interface unit is further configured to obtain a mode control signal so that the circuit module is in the first mode or the second mode, wherein: When the circuit module is in the first mode, the adjustment unit adjusts the clock signal specified by the clock adjustment parameter to generate the data acquisition clock signal; When the circuit module is in the second mode, the adjustment unit uses the internal clock signal as the data acquisition clock signal by default, and after detecting the external clock signal and the stabilization time of the external clock signal reaches a first threshold time, the adjustment unit adjusts the external clock signal based on the frequency and phase of the external clock signal to generate the data acquisition clock signal.

2. The circuit module according to claim 1, characterized in that: The detection unit is further configured to: If the external clock signal is used as the data acquisition clock signal or in the second mode, the detection unit detects whether the external clock signal has a first type of transition, If the first type of jump is not detected within the second threshold time, enter the next detection cycle; If the first type of transition is detected, the first level is counted, and when the second type of transition is detected, the second level is counted, and the frequency and phase of the external clock signal are determined based on the counting results of the first and second levels. The first level and the second level correspond to the first type of transition and the second type of transition respectively.

3. The circuit module according to claim 2, characterized in that: The clock adjustment parameter includes a gain coefficient, and the adjustment unit is further configured to: The voltage of the external clock signal is adjusted based on the gain coefficient to adjust the phase of the external clock signal, wherein the gain coefficient includes a proportional gain coefficient and / or an integral gain coefficient.

4. The circuit module according to claim 2, characterized in that: The clock adjustment parameter includes a frequency coefficient, and the adjustment unit is further configured to: The frequency of the external clock signal is adjusted based on the frequency coefficient, wherein the frequency coefficient includes a frequency multiplication coefficient or a frequency division coefficient.

5. The circuit module according to claim 2, characterized in that: The clock adjustment parameter includes a clock signal adjustment value, and the adjustment unit is further configured to: The number of clock signal cycles required to be adjusted in each data acquisition cycle is determined based on the clock signal adjustment value, and the clock signal is adjusted through multiple data acquisition cycles.

6. A data receiving device, characterized in that: include: The communication interface module is configured to obtain a control instruction from a host computer and determine a clock adjustment parameter based on the control instruction; a control module, coupled to the communication interface module, and configured to send the clock adjustment parameter from the communication interface module; The circuit module according to any one of claims 1 to 5, configured to generate the data acquisition clock signal based on the clock adjustment parameter and the received clock signal; The data processing module is configured to obtain the control instruction, and process the data based on the control instruction and the data acquisition clock signal, and transmit the processed data and the data acquisition clock signal to the communication interface module.

7. The data receiving device according to claim 6, characterized in that: The communication interface module includes at least one of the following interfaces: SPI, IIC, UART and ETH.

8. The data receiving device according to claim 6, characterized in that: The communication interface module also includes a filtering unit.

9. An electronic device, characterized in that: include: Antenna, and The data receiving device according to any one of claims 6 to 8, coupled to the antenna to obtain data and clock signals.

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