A signal receiving method and a chip

Abstract

The present application discloses a signal receiving method and a chip. When the chip is in a non anti-interference mode, an anti-interference detection signal is generated based on the received first start signal and the first external signal. The anti-interference detection signal includes an anti-interference enable signal, a reception start signal, and a reception end signal. After receiving the anti-interference generation signal, an anti-interference processing signal is generated based on the reception start signal and the reception end signal. When the chip is in an anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal. The anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal. Compared with receiving an external signal based on a start signal, it is possible to reduce the probability that the timing error of the start signal caused by interference results in an incomplete external signal being received, thereby improving the stability and accuracy of signal transmission of the chip.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and particularly to a signal receiving method and a chip. Background Art

[0002] With the rapid development of information technology, chips have become an indispensable core component in modern electronic devices. Chips play a crucial role in multiple fields such as military, civilian, communication, and finance. In addition, as the foundation of the information technology industry, chips play a fundamental and supportive role in the development of all walks of life. Especially in the development of high-tech industries such as artificial intelligence, the Internet of Things, and 5G, chips play a leading role.

[0003] However, when a chip receives external signals, it is easily affected by various interferences, such as electromagnetic interference (EMI), radio frequency interference (RFI), etc. Since there is no response mechanism for some signal transmissions, these interferences may cause a decline in signal quality and even lead to abnormal operation of the chip. For example, although the serial peripheral interface (SPI) communication protocol has the advantages of high speed, full duplex, and synchronous communication, it lacks a response mechanism. For example, during video data transmission, usually when the chip receives a frame synchronization signal and starts to receive SPI signals, if due to interference, the chip encounters an unreasonably timed vertical synchronization (Vsync) signal when receiving a frame of image data, it will cause incorrect image display and affect the normal operation of the internal logic of the chip. Summary of the Invention

[0004] This application provides a signal receiving method and a chip to solve the problem that the normal operation of the internal logic of the chip is affected by interference when the chip receives signals.

[0005] In a first aspect, this application provides a signal receiving method, including:

[0006] When the chip is in a non-antijamming mode, based on the received first start signal and the first external signal, generate an anti-interference detection signal, where the anti-interference detection signal includes an anti-interference enable signal, a reception start signal, and a reception end signal;

[0007] After receiving an anti-interference generation signal, based on the reception start signal and the reception end signal in the anti-interference detection signal, generate an anti-interference processing signal;

[0008] When the chip is in the anti-interference mode, the received second external signal is regarded as a complete signal based on the first anti-interference processing signal, where the anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal.

[0009] In a possible implementation, generating the anti-interference detection signal based on the received first start signal and the first external signal includes:

[0010] Generating the received start signal at the end moment of the first start signal;

[0011] Generating the received end signal at the end moment of the first external signal;

[0012] And generating the anti-interference enable signal after receiving the first start signal and / or the first external signal;

[0013] Wherein, the received start signal and the received end signal include communication signals of a communication protocol.

[0014] In a possible implementation, generating the anti-interference processing signal based on the received start signal and the received end signal in the anti-interference detection signal includes:

[0015] At the moment of receiving the received start signal, flipping the original level signal to obtain the first level signal;

[0016] At the moment of receiving the received end signal, flipping the first level signal to obtain the anti-interference processing signal.

[0017] In a possible implementation, if the original level signal is a low level signal, the moment of receiving the received start signal is used as the rising edge of the anti-interference processing signal, and the moment of receiving the received end signal is used as the falling edge of the anti-interference processing signal;

[0018] If the original level signal is a high level signal, the moment of receiving the received start signal is used as the falling edge of the anti-interference processing signal, and the moment of receiving the received end signal is used as the rising edge of the anti-interference processing signal.

[0019] In a possible implementation, regarding the received second external signal as a complete signal based on the first anti-interference processing signal includes:

[0020] Regarding the signal received between the rising edge and the falling edge of the first anti-interference processing signal as a complete signal; or

[0021] Take the signal received between the falling edge and the rising edge of the first anti-interference processing signal as a complete signal.

[0022] In a possible implementation, before taking the received second external signal as a complete signal based on the first anti-interference processing signal, it further includes:

[0023] Periodically control the anti-interference processing signal to be valid, or control the anti-interference processing signal to be valid after receiving the second start signal.

[0024] In a possible implementation, the method further includes:

[0025] During the process of taking the received second external signal as a complete signal based on the first anti-interference processing signal, if a second anti-interference processing signal is received, ignore the second anti-interference processing signal, where the second anti-interference processing signal is a valid anti-interference processing signal.

[0026] In a second aspect, the present application provides a chip, including: an anti-interference processing module, a signal receiving module, and an anti-interference detection module;

[0027] The anti-interference processing module is configured to send the received first start signal and first external signal to the signal receiving module in a non-anti-interference mode, and send the received second external signal to the signal receiving module based on the received first anti-interference processing signal in an anti-interference mode, where the anti-interference mode is set after receiving an anti-interference enable signal, and the first anti-interference processing signal is a valid anti-interference processing signal;

[0028] The signal receiving module is configured to generate an anti-interference detection signal based on the received first start signal and first external signal after receiving an anti-interference generation signal, and take the received second external signal as a complete signal in the anti-interference mode, where the anti-interference detection signal includes an anti-interference enable signal, a received start signal, and a received end signal;

[0029] The anti-interference detection module is configured to generate the anti-interference processing signal based on the received received start signal and received end signal after receiving the anti-interference generation signal, and send the anti-interference enable signal to the anti-interference processing module.

[0030] In a possible implementation, the signal receiving module is specifically configured to:

[0031] Generate the received start signal at the end moment of the first start signal;

[0032] Generate the reception end signal at the end moment of the first external signal;

[0033] And generate the anti-interference enable signal after receiving the first start signal and / or the first external signal;

[0034] Wherein, the reception start signal and the reception end signal include communication signals of a communication protocol.

[0035] In a possible implementation manner, the anti-interference detection module is specifically configured to:

[0036] At the moment of receiving the reception start signal, invert the original level signal to obtain a first level signal;

[0037] At the moment of receiving the reception end signal, invert the first level signal to obtain the anti-interference processing signal.

[0038] In a possible implementation manner, the anti-interference detection module is specifically configured to:

[0039] If the original level signal is a low-level signal, use the moment of receiving the reception start signal as the rising edge of the anti-interference processing signal, and use the moment of receiving the reception end signal as the falling edge of the anti-interference processing signal;

[0040] If the original level signal is a high-level signal, use the moment of receiving the reception start signal as the falling edge of the anti-interference processing signal, and use the moment of receiving the end signal as the rising edge of the anti-interference processing signal.

[0041] In a possible implementation manner, the anti-interference detection module is specifically configured to:

[0042] Regard the signal received between the rising edge and the falling edge of the first anti-interference processing signal as a complete signal; or

[0043] Regard the signal received between the falling edge and the rising edge of the first anti-interference processing signal as a complete signal.

[0044] In a possible implementation manner, the signal reception module is further configured to:

[0045] Periodically send the first anti-interference processing signal to the anti-interference detection module; or

[0046] After receiving the second start signal, send the first anti-interference processing signal to the anti-interference detection module.

[0047] In a possible implementation, the anti-interference processing module is further configured to:

[0048] During the process of receiving the second external signal based on the first anti-interference processing signal, if a second anti-interference processing signal is received, the second anti-interference processing signal is ignored, where the second anti-interference processing signal is a valid anti-interference processing signal.

[0049] The beneficial effects of the present invention are as follows:

[0050] The present application discloses a signal receiving method and a chip. When the chip is in a non-anti-interference mode, based on the received first start signal and the first external signal, an anti-interference detection signal is generated, where the anti-interference detection signal includes an anti-interference enable signal, a reception start signal, and a reception end signal; after receiving the anti-interference generation signal, based on the reception start signal and the reception end signal, an anti-interference processing signal is generated; when the chip is in an anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, where the anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal. Since when the chip is in the anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, compared with receiving the external signal based on the start signal, it is possible to reduce the probability that the timing error of the start signal caused by interference results in an incomplete external signal being received, thereby improving the stability and accuracy of signal transmission of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0052] Figure 1 It is a schematic diagram of image data transmission provided by an embodiment of the present application;

[0053] Figure 2 It is another schematic diagram of image data transmission provided by an embodiment of the present application;

[0054] Figure 3a It is a schematic diagram of image data transmission and display provided by an embodiment of the present application;

[0055] Figure 3b It is a schematic diagram of image data transmission and display provided by an embodiment of the present application;

[0056] Figure 4Schematic flowchart of a signal receiving method provided by an embodiment of this application;

[0057] Figure 5 Schematic diagram of generating an anti-interference detection signal provided by an embodiment of this application;

[0058] Figure 6 Schematic diagram of generating an anti-interference processing signal provided by an embodiment of this application;

[0059] Figure 7 Another schematic diagram of generating an anti-interference processing signal provided by an embodiment of this application;

[0060] Figure 8 Schematic diagram of the structure of a chip provided by an embodiment of this application. Detailed implementation manners

[0061] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0062] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of this application described here can be implemented in an order different from those illustrated or described here. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with this application. On the contrary, they are merely examples of devices and methods consistent with some aspects of this application as detailed in the appended claims.

[0063] Communication between chips is achieved through signal transmission. For example, the SPI communication protocol. SPI is a high-speed, full-duplex, synchronous communication bus. The advantages of the SPI communication protocol are that it supports full-duplex communication, the communication method is relatively simple, and the relative data transmission rate is relatively fast; the disadvantages are that there is no specified flow control and no response mechanism, and there are certain defects in data reliability.

[0064] In the field of image display, video images have the property of refresh rate. The refresh rate of a video refers to the number of times the screen is refreshed per second, measured in Hertz (Hz). When using SPI signals for video data transmission, a vertical synchronization signal (Vsync signal) needs to be added. VSync is a technology used to synchronize the display refresh rate and the graphics rendering frame rate, aiming to avoid screen tearing and reduce power consumption.

[0065] The principle of the Vsync signal is to limit the graphics rendering frame rate to a fixed frequency according to the refresh rate of the display, so that each refresh occurs at the moment when the display scan line finishes refreshing. The Vsync signal is generally the first signal that the chip needs to recognize during the overall signal transmission process. After the chip recognizes this signal, it will recognize the SPI signal, which is the data of a frame of image.

[0066] In specific implementation, when the chip is receiving the data of a frame of image, if an unreasonably timed Vsync signal appears, it may be sent incorrectly or may be a signal caused by interference. At this time, after the chip receives the Vsync signal, it will fill the data in the middle of the image into the first data, resulting in incorrect image display. In severe cases, it may cause the internal logic of the chip to malfunction.

[0067] For example, as Figure 1 shown, a frame of image has 4096 data. Under normal circumstances, after the chip receives the Vsync signal, it will receive 4096 signals transmitted by the SPI signal and fill the 4096 signals in order from the first position of the display area to the 4096th position.

[0068] If an unreasonable Vsync signal appears during the transmission of these 4096 signals by the chip, for example, as Figure 2 shown, the unreasonable Vsync signal appears at the position of the 2048th image data transmitted by the SPI signal, which will cause the 2049th image data to be filled into the first image data position of the display area, the 2050th image data to be filled into the second image data position of the display area... And there is no image data to fill after the 2049th position. The filling of the incorrect position of the image data will cause incorrect display on the screen.

[0069] As Figure 3a shown, it is a schematic diagram of normal display in the display area. As Figure 3b shown, the upper half of the display area shows the image of the lower half, and the lower half of the display area does not show the image.

[0070] When the signal receiving method and chip provided by the embodiments of the present application are adopted, when the chip is in the anti-interference mode, the chip uses the anti-interference processing signal to regard the received external signal as a complete signal. Compared with receiving the external signal based on the start signal, it can reduce the probability that the received external signal is an incomplete signal caused by the timing error of the start signal due to interference, thereby improving the stability and accuracy of the signal transmitted by the chip.

[0071] The following will combine the accompanying drawings to detail a signal receiving method and a chip provided by the embodiments of the present application.

[0072] As Figure 4 shown, it is a schematic flowchart of a signal receiving method provided by the embodiments of the present application, which specifically includes the following steps:

[0073] S401: When the chip is in the non-anti-interference mode, generate an anti-interference detection signal based on the received first start signal and the first external signal, where the anti-interference detection signal includes an anti-interference enable signal, a received start signal, and a received end signal;

[0074] S402: After receiving the anti-interference generation signal, generate an anti-interference processing signal based on the received start signal and the received end signal in the anti-interference detection signal;

[0075] S403: When the chip is in the anti-interference mode, regard the received second external signal as a complete signal based on the first anti-interference processing signal, where the anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal.

[0076] A signal receiving method disclosed in the present application generates an anti-interference detection signal based on the received first start signal and the first external signal when the chip is in the non-anti-interference mode, where the anti-interference detection signal includes an anti-interference enable signal, a received start signal, and a received end signal; after receiving the anti-interference generation signal, generate an anti-interference processing signal based on the received start signal and the received end signal; when the chip is in the anti-interference mode, regard the received second external signal as a complete signal based on the first anti-interference processing signal, where the anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal. Since when the chip is in the anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal. Compared with receiving the external signal based on the start signal, it can reduce the probability that the received external signal is an incomplete signal caused by the timing error of the start signal due to interference, thereby improving the stability and accuracy of the signal transmitted by the chip.

[0077] It should be noted that in specific implementation, the first external signal, the second external signal, the first start signal, and the second start signal can be communication signals of various types of communication protocols, that is, communication protocol signals. For example, communication signals of the SPI communication protocol, MIPI communication protocol signals, etc. When the first external signal and the second external signal are both SPI signals, and the first start signal and the second start signal are both frame synchronization signals.

[0078] In specific implementation, after the chip is powered on, it is in an initial state and then enters the working state. When the chip does not receive the anti-interference enable signal, the chip is in the non-anti-interference mode. In the non-anti-interference mode, the chip generates an anti-interference detection signal based on the received first start signal and the first external signal. Among them, the anti-interference detection signal includes a receive start signal, a receive end signal, and an anti-interference enable signal.

[0079] Among them, the first external signal and the second external signal can be a single signal or a group of signals. That is to say, when there is only one signal that needs anti-interference processing, the first external signal and the second external signal are both single signals. When there are multiple signals that need anti-interference processing, the first external signal and the second external signal are both groups of signals.

[0080] Specifically, the chip generates a receive start signal at the end moment of receiving the first start signal, generates a receive end signal at the moment of receiving the last signal in the first external signal, and generates an anti-interference enable signal after receiving the first start signal and / or the first external signal. Among them, the receive start signal and the receive end signal include communication signals of the communication protocol, that is, communication protocol signals. For example, communication protocol signals between multiple devices, communication protocol signals between multiple modules in a single device. Here, the communication protocol, such as the SPI communication protocol, the MIPI communication protocol, etc.

[0081] As Figure 5 shown, it is a schematic diagram of generating an anti-interference detection signal provided by an embodiment of the present application. When receiving the Vsync signal (the first start signal), a receive start signal S1 is generated. At the same time, the SPI signal (the first external signal) is also transmitted; at the moment when the SPI signal transmission is completed, that is, at the moment when the last signal of the SPI signal is transmitted, a receive end signal E1 is generated.

[0082] In the embodiments of the present application, the anti-interference enable signal is the switching signal of the anti-interference function. After the anti-interference enable signal is generated, the operator can determine whether to enable the anti-interference function according to the interference enable signal. For example, when the external signal received by the chip has a simple structure, the operator can set the anti-interference enable signal to 0, that is, not to turn on the anti-interference function of the chip; when the external signal received by the chip has a complex structure and high timing requirements, the anti-interference enable signal is 1, that is, to turn on the anti-interference function of the chip. The anti-interference enable signal being 1 means that the anti-interference enable signal is generated after receiving the start signal and / or the first external signal.

[0083] In one embodiment, after receiving the anti-interference generation signal, based on the received start signal and received end signal in the anti-interference detection signal, an anti-interference processing signal is generated. Specifically, the moment of receiving the received start signal is used as the rising edge of the anti-interference processing signal, and the moment of receiving the received end signal is used as the falling edge of the anti-interference processing signal.

[0084] Reference Figure 6 , the moment of generating the received start signal S1 is used as the rising edge of the anti-interference processing signal A1; the moment of generating the received end signal E1 is used as the falling edge of the anti-interference processing signal A1.

[0085] In a specific implementation, after the chip generates a valid anti-interference enable signal and an anti-interference processing signal, the chip is switched from the non-anti-interference mode to the anti-interference mode. When the chip is in the anti-interference mode, based on the anti-interference processing signal, the received second external signal is regarded as a complete signal. Here, the anti-interference processing signal is the valid anti-interference processing signal.

[0086] In a specific implementation, the anti-interference processing signal can be controlled to be valid periodically, or the anti-interference processing signal can be controlled to be valid after receiving the second start signal.

[0087] For example, if the second external signal is an SPI signal and the screen refresh rate remains unchanged, the anti-interference processing signal can be controlled to be valid periodically. If the screen refresh rate changes, the anti-interference processing signal can be controlled to be valid after receiving the frame synchronization signal.

[0088] In the embodiments of the present application, the anti-interference enable signal is valid, that is, the anti-interference enable signal is 1.

[0089] Specifically, when the chip is in the anti-interference mode, the signal received between the rising edge and the falling edge of the anti-interference processing signal is regarded as a complete signal.

[0090] For example, the signal received between the rising edge and the falling edge of the anti-interference processing signal is regarded as a frame of image data.

[0091] In a specific implementation, when the second start signal is received, the anti-interference processing signal is made effective, that is, the first anti-interference processing signal. The second external signal received between the rising edge and the falling edge of the first anti-interference processing signal is regarded as a complete signal. If, during the process of regarding the second external signal received between the rising edge and the falling edge of the first anti-interference processing signal as a complete signal, a valid anti-interference processing signal, that is, the second anti-interference processing signal, is received, then the second anti-interference processing signal is ignored.

[0092] For example, as Figure 7 shown, when the chip is in the anti-interference mode, when the first Vsync signal triggers the anti-interference processing signal A1, the chip regards the SPI signal received between the rising edge and the falling edge of the anti-interference processing signal A1 as a frame of image data. When, between the rising edge and the falling edge of the anti-interference processing signal A1, the second Vsync signal triggers the anti-interference processing signal A2, at this time, the anti-interference processing signal A2 is ignored.

[0093] Since the anti-interference processing signal A2 is ignored, and the anti-interference processing signal A2 is triggered after the second Vsync signal is received, therefore, the second Vsync signal is also ignored. The second Vsync signal is an unreasonably timed Vsync signal. Therefore, an unreasonably timed Vsync signal will not affect the transmission of normal signals.

[0094] Based on the same inventive concept, an embodiment of the present application further provides a chip. The principle of the chip for solving technical problems is similar to the above signal receiving method. The implementation of the chip can refer to the implementation of the signal receiving method, and the repeated parts will not be elaborated.

[0095] As Figure 8 shown, it is a schematic structural diagram of a chip provided by an embodiment of the present application, including: an anti-interference processing module 81, a signal receiving module 82, and an anti-interference detection module 83;

[0096] The first input end of the anti-interference processing module 81 is used to input a start signal and an external signal. The output end of the anti-interference processing module 81 is electrically connected to the input end of the signal receiving module 82. The first output end of the signal receiving module 82 is electrically connected to the input end of the anti-interference detection module 83. The output end of the anti-interference detection module 83 is electrically connected to the second input end of the anti-interference processing module 81.

[0097] An anti-interference processing module 81, configured to send the received first start signal and first external signal to the signal receiving module in a non-anti-interference mode, and in an anti-interference mode, based on the received first anti-interference processing signal, send the received second external signal to the signal receiving module, where the anti-interference mode is set after receiving an anti-interference enable signal, and the first anti-interference processing signal is a valid anti-interference processing signal;

[0098] A signal receiving module 82, configured to generate an anti-interference detection signal based on the received first start signal and first external signal after receiving an anti-interference generation signal, and in the anti-interference mode, use the received second external signal as a complete signal, where the anti-interference detection signal includes an anti-interference enable signal, a received start signal, and a received end signal;

[0099] An anti-interference detection module 83, configured to generate the anti-interference processing signal based on the received received start signal and received end signal after receiving an anti-interference generation signal, and send the anti-interference enable signal to the anti-interference processing module.

[0100] It should be noted that the signal receiving module 82 in the embodiment of the present application is further provided with a second output terminal. The second output terminal of the signal receiving module 82 outputs the first external signal or the complete signal after anti-interference processing. For example, if the external signal is image data, the signal receiving module 82 processes the image data sent by the anti-interference processing module 81 it receives, outputs the processed image data, and the output processed image data will be filled into the display area in sequence.

[0101] In the embodiment of the present application, after the chip is powered on, the anti-interference processing module 81 receives the start signal and the external signal. At this time, the chip is in the non-anti-interference mode after power-on. Therefore, the anti-interference processing module 81, the signal receiving module 82, and the anti-interference detection module 83 are all in the non-anti-interference mode;

[0102] When the anti-interference processing module 81 is in the non-anti-interference mode, it directly sends the received start signal and external signal to the signal receiving module 82. When the signal receiving module 82 receives the anti-interference generation signal and then receives the first start signal and the first external signal, it generates an anti-interference detection signal based on the first start signal and the first external signal, and sends the anti-interference detection signal to the anti-interference detection module 83, where the anti-interference detection signal includes a received start signal, a received end signal, and an anti-interference enable signal;

[0103] After the anti-interference detection module 83 receives the anti-interference generation signal, based on the received start signal in the anti-interference detection signal and the received end signal in the anti-interference detection signal, it generates an anti-interference processing signal. The anti-interference detection module 83 sends the anti-interference enable signal in the anti-interference detection signal to the anti-interference processing module 81, and at this time, the anti-interference enable signal is valid;

[0104] After the anti-interference processing module 81 receives the valid anti-interference enable signal, it enables the anti-interference function, and the anti-interference processing module 81 switches from the non-anti-interference mode to the anti-interference mode;

[0105] After the anti-interference processing module 81 is in the anti-interference mode, after receiving the start signal, it sends the start signal to the anti-interference detection module 83 through the signal receiving module 82. After the anti-interference detection module 83 receives the start signal, it sends the anti-interference processing signal to the anti-interference processing module 81. After the anti-interference processing module 81 receives the anti-interference processing signal, it regards the received external signal as a complete signal based on the anti-interference processing signal.

[0106] In a specific implementation, when the anti-interference processing module 81 is in the non-anti-interference mode, it will not ignore the received initial signal. When the anti-interference processing module 81 is in the anti-interference mode, if it receives another anti-interference processing signal within the valid duration of the anti-interference processing signal, it will ignore the anti-interference processing signal. Since the other anti-interference processing signal is triggered by another initial signal, the anti-interference processing module 81 ignores the other initial signal.

[0107] The valid duration of the anti-interference processing signal generated by the anti-interference detection module 83 is the same as the duration of the complete signal.

[0108] The received start signal is generated by the signal receiving module 82 when it receives the first start signal, and the received end signal is generated by the signal receiving module 82 when it finishes receiving the first external signal. The anti-interference detection module 83 generates the anti-interference processing signal through the received start signal and the received end signal.

[0109] In one embodiment, the signal receiving module is specifically used for:

[0110] Generating the received start signal at the end moment of the first start signal;

[0111] Generating the received end signal at the end moment of the first external signal;

[0112] And generating the anti-interference enable signal after receiving the first start signal and / or the first external signal.

[0113] Among them, the received start signal and the received end signal include communication signals of a communication protocol.

[0114] In one embodiment, the anti-interference detection module is specifically configured to:

[0115] At the moment of receiving the received start signal, flip the original level signal to obtain a first level signal;

[0116] At the moment of receiving the received end signal, flip the first level signal to obtain the first anti-interference processed signal.

[0117] In one embodiment, the anti-interference detection module is specifically configured to:

[0118] If the original level signal is a low-level signal, take the moment of receiving the received start signal as the rising edge of the anti-interference processed signal, and take the moment of receiving the received end signal as the falling edge of the anti-interference processed signal;

[0119] If the original level signal is a high-level signal, take the moment of receiving the received start signal as the falling edge of the anti-interference processed signal, and take the moment of receiving the end signal as the rising edge of the anti-interference processed signal.

[0120] In one embodiment, the anti-interference detection module is specifically configured to:

[0121] Take the signal received between the rising edge and the falling edge of the first anti-interference processed signal as a complete signal; or

[0122] Take the signal received between the falling edge and the rising edge of the first anti-interference processed signal as a complete signal.

[0123] In one embodiment, the signal receiving module is further configured to:

[0124] Periodically send the first anti-interference processed signal to the anti-interference detection module; or

[0125] After receiving the second start signal, send the first anti-interference processed signal to the anti-interference detection module.

[0126] In one embodiment, the signal receiving module is further configured to:

[0127] After receiving the second start signal, trigger the anti-interference detection module to send the first anti-interference processed signal.

[0128] In one embodiment, the anti-interference processing module is further configured to:

[0129] In the process of receiving the second external signal based on the first anti-interference processing signal, if a second anti-interference processing signal is received, the second anti-interference processing signal is ignored, where the second anti-interference processing signal is a valid anti-interference processing signal.

[0130] This application discloses a signal receiving method and a chip. When the chip is in a non-anti-interference mode, based on the received first start signal and first external signal, an anti-interference detection signal is generated, where the anti-interference detection signal includes an anti-interference enable signal, a reception start signal, and a reception end signal; after receiving an anti-interference generation signal, an anti-interference processing signal is generated based on the reception start signal and the reception end signal; when the chip is in an anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, where the anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal. Since when the chip is in the anti-interference mode, based on the first anti-interference processing signal, the received second external signal is regarded as a complete signal, compared with receiving the external signal based on the start signal, it is possible to reduce the probability that the timing error of the start signal caused by interference results in an incomplete external signal being received, thereby improving the stability and accuracy of signal transmission of the chip.

[0131] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0132] This application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for realizing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0133] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce a manufacture including an instruction device that implements the function specified in one or more of the processes and / or blocks Figure 1 one or more of the processes and / or blocks Figure 1 specified in the block or blocks.

[0134] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable apparatus provide steps for implementing the function specified in one or more of the processes and / or blocks Figure 1 one or more of the processes and / or blocks Figure 1 specified in the block or blocks.

[0135] It is apparent that those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A signal receiving method, characterized in that: include: When the chip is in a non-anti-interference mode, an anti-interference detection signal is generated based on the received first start signal and the first external signal, wherein the anti-interference detection signal includes an anti-interference enable signal, a receiving start signal, and a receiving end signal; After receiving the anti-interference generation signal, at the moment of receiving the receiving start signal, the original level signal is flipped to obtain the first level signal; at the moment of receiving the receiving end signal, the first level signal is flipped to obtain the anti-interference processing signal; When the chip is in an anti-interference mode, based on a first anti-interference processing signal, the received second external signal is regarded as a complete signal, wherein the anti-interference mode is set when the anti-interference enable signal is valid, and the first anti-interference processing signal is a valid anti-interference processing signal; The method of treating the received second external signal as a complete signal based on the first anti-interference processing signal includes: treating a signal received between a rising edge of the first anti-interference processing signal and a falling edge of the first anti-interference processing signal as a complete signal; or The signal received between the falling edge of the first anti-interference processing signal and the rising edge of the first anti-interference processing signal is regarded as a complete signal.

2. The method according to claim 1, characterized in that The step of generating an anti-interference detection signal based on the received first start signal and the first external signal comprises: At the end time of the first start signal, generating the receiving start signal; At the end moment of the first external signal, generating the reception end signal; and generating the anti-interference enable signal after receiving the first start signal and / or the first external signal; Wherein, the receiving start signal and the receiving end signal include communication protocol signals.

3. The method according to claim 1, characterized in that If the original level signal is a low level signal, the moment of receiving the receiving start signal is used as the rising edge of the anti-interference processing signal, and the moment of receiving the receiving end signal is used as the falling edge of the anti-interference processing signal; If the original level signal is a high level signal, the moment of receiving the receiving start signal is used as the falling edge of the anti-interference processing signal, and the moment of receiving the receiving end signal is used as the rising edge of the anti-interference processing signal.

4. The method according to any one of claims 1 to 3, characterized in that: Before treating the received second external signal as a complete signal based on the first anti-interference processing signal, the method further includes: The anti-interference processing signal is controlled to be effective periodically, or after receiving a second start signal, the anti-interference processing signal is controlled to be effective.

5. The method according to claim 4, characterized in that The method further includes: In the process of treating the received second external signal as a complete signal based on the first anti-interference processing signal, if a second anti-interference processing signal is received, the second anti-interference processing signal is ignored, wherein the second anti-interference processing signal is a valid anti-interference processing signal.

6. A chip, characterized in that: include: Anti-interference processing module, signal receiving module and anti-interference detection module; The anti-interference processing module is configured to send the received first start signal and the first external signal to the signal receiving module in a non-anti-interference mode, and send the received second external signal to the signal receiving module based on the received first anti-interference processing signal in an anti-interference mode, wherein the anti-interference mode is set after receiving an anti-interference enable signal, and the first anti-interference processing signal is a valid anti-interference processing signal; The signal receiving module is used to generate an anti-interference detection signal based on the received first start signal and the first external signal after receiving the anti-interference generation signal, and in the anti-interference mode, regard the received second external signal as a complete signal, wherein the anti-interference detection signal includes an anti-interference enable signal, a receiving start signal and a receiving end signal; The anti-interference detection module is used to generate the anti-interference processing signal based on the received receiving start signal and the received end signal after receiving the anti-interference generation signal, and send the anti-interference enabling signal to the anti-interference processing module; The anti-interference detection module is specifically used for: When the receiving start signal is received, the original level signal is flipped to obtain a first level signal; At the moment of receiving the receiving end signal, flipping the first level signal to obtain the anti-interference processing signal; The anti-interference detection module is specifically used for: treating a signal received between a rising edge of the first anti-interference processing signal and a falling edge of the first anti-interference processing signal as a complete signal; or The signal received between the falling edge of the first anti-interference processing signal and the rising edge of the first anti-interference processing signal is regarded as a complete signal.

7. The chip according to claim 6, characterized in that: The signal receiving module is specifically used for: At the end time of the first start signal, generating the receiving start signal; At the end moment of the first external signal, generating the reception end signal; and generating the anti-interference enable signal after receiving the first start signal and / or the first external signal; Wherein, the receiving start signal and the receiving end signal include communication signals of a communication protocol.

8. The chip according to claim 6, characterized in that: The anti-interference detection module is specifically used for: If the original level signal is a low level signal, the moment of receiving the receiving start signal is used as the rising edge of the anti-interference processing signal, and the moment of receiving the receiving end signal is used as the falling edge of the anti-interference processing signal; If the original level signal is a high level signal, the moment of receiving the start signal is used as the falling edge of the anti-interference processing signal, and the moment of receiving the end signal is used as the rising edge of the anti-interference processing signal.

9. The chip according to any one of claims 6 to 8, characterized in that: The signal receiving module is also used for: periodically sending the first anti-interference processing signal to the anti-interference detection module; or After receiving the second start signal, the first anti-interference processing signal is sent to the anti-interference detection module.

10. The chip according to claim 9, characterized in that: The anti-interference processing module is also used for: In the process of receiving the second external signal based on the first anti-interference processing signal, if a second anti-interference processing signal is received, the second anti-interference processing signal is ignored, wherein the second anti-interference processing signal is a valid anti-interference processing signal.

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