Printed circuit board, circuit board assembly and preparation method

Abstract

The invention provides a printed circuit board, a circuit board assembly and a preparation method, and relates to the field of microelectronics. The printed circuit board comprises a core board and stacking groups at two sides of the core board, each stacking group comprises at least three stacking layers, and the stacking layers are divided into a grounding layer and a signal layer; in the first direction of the printed circuit board, the grounding layers and the signal layers are arranged at intervals; in the second direction of the printed circuit board, the grounding holes are arranged between the adjacent differential signal pairs, and the partial differential signal pairs close to the center of the printed circuit board in the second direction and the grounding holes are connected with the core board via holes in the core board; and on two sides of the differential signal pair arranged on one signal layer, the depth of the grounding hole close to one side of the edge of the printed circuit board is smaller than that of the differential signal pair on the same layer, and the depth of the grounding hole far away from one side of the edge of the printed circuit board is larger than that of the differential signal pair on the same layer. Through the structure, the signal transmission reliability of the printed circuit board can be improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a printed circuit board, a circuit board assembly and a preparation method thereof. Background Art

[0002] With the development of network technology, more devices need to be deployed on the circuit boards in network equipment. The connectivity between devices and the input and output of signals require connectivity structures such as lines and vias on the circuit boards. Therefore, the density of the connection structures that need to be formed on the circuit boards is getting higher and higher.

[0003] On a circuit board, due to the transmission of high-speed signals, crosstalk is easily generated between connection structures. As the density of circuit boards becomes higher and higher, how to reduce the crosstalk is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0004] In order to overcome the problems existing in the related art, this specification provides a printed circuit board, a circuit board assembly and a preparation method.

[0005] According to a first aspect of an embodiment of this specification, there is provided a printed circuit board, comprising:

[0006] A core plate, on which a core plate via hole penetrating the core plate is arranged;

[0007] Two stacking groups are respectively pressed onto two surfaces of the core board, each stacking group comprises at least three stacking layers, a plurality of differential signal pairs and a plurality of grounding holes are arranged on the two stacking groups, a stacking layer in one stacking group comprises a grounding layer and a signal layer, and a signal line connected to the differential signal pair arranged on the signal layer is fanned out toward the edge of the printed circuit board;

[0008] Wherein, in a first direction from the first surface to the second surface of the printed circuit board, the ground layer and the signal layer are arranged alternately;

[0009] In a second direction from the edge to the center of the printed circuit board, the grounding holes are arranged between adjacent differential signal pairs, and part of the differential signal pairs and the grounding holes close to the center of the printed circuit board in the second direction are connected to the core board vias on the core board;

[0010] On both sides of a differential signal pair set on a signal layer, the depth of the grounding hole on the edge side close to the printed circuit board is less than the depth of the differential signal pair set on the signal layer, and the depth of the grounding hole on the edge side away from the printed circuit board is greater than the depth of the differential signal pair set on the signal layer.

[0011] Optionally, at least two columns of differential signal pairs are arranged on a signal layer, and a differential signal pair includes a first differential signal hole close to the edge of the printed circuit board and a second differential signal hole away from the edge of the printed circuit board, the first differential signal hole fans out through a first signal line, and the second differential signal hole fans out through a second signal line.

[0012] Optionally, the first signal line includes an avoidance section and a return section, wherein the first end of the avoidance section is connected to a first differential signal hole in a differential signal pair and is bent toward a side away from a second differential signal hole in the differential signal pair, and the return section is connected to the second end of the avoidance section and is bent toward a side close to the second differential signal hole in the differential signal pair.

[0013] Optionally, the distance between the avoidance section and the second differential signal hole in the same differential signal pair is not less than the width of the signal line;

[0014] The distance between the return segment and the second signal line connected to the second differential signal hole in the same differential signal pair is not less than the width of the signal line, and the distance between the return segment and the avoidance segment of the first signal line connected to the first differential signal hole in the differential signal pair in different columns on the same signal layer is not less than three times the width of the signal line.

[0015] Optionally, the grounding holes between the differential signal pairs in different columns on the same signal layer are formed with a plurality of grounding hole groups, and a gap is formed between each of the grounding hole groups;

[0016] Among the differential signal pairs on the same signal layer, signal lines connected to the differential signal pairs away from the edge of the printed circuit board fan out from between adjacent ground hole groups.

[0017] Optionally, on the same signal layer, the signal vias of the differential signal pairs in the same column are eccentrically arranged to the same side as their own pads, and the vias of the differential signal pairs in different columns are eccentrically arranged to different sides as their own pads;

[0018] Wherein, the center distance between the signal via of a differential signal pair and the pad of the differential signal pair is not less than 4 mils and not more than 5 mils.

[0019] Optionally, an anti-pad is formed by etching on the ground layer through which the signal via of the differential signal pair passes;

[0020] The distance from the pad included in the differential signal pair to the edge of the anti-pad of the differential signal pair is not less than 4 mils and not more than 5 mils.

[0021] According to the second aspect of the embodiments of this specification, a circuit board assembly is provided, comprising a chip and a printed circuit board as described in any one of the above items, wherein the chip is plugged into the printed circuit board, the signal pin of the chip is electrically connected to the differential signal pair, and the ground pin on the chip is electrically connected to the ground hole.

[0022] Optionally, the signal pins on the chip include input pins and output pins, wherein the input pins are close to the edge of the chip, and the output pins are close to the center of the chip.

[0023] According to a third aspect of an embodiment of this specification, a method for preparing a printed circuit board is provided, comprising:

[0024] Drilling through holes on the core board, forming core board vias by electroplating, and etching on both sides of the core board to form core board patterns;

[0025] Laminating the stacked layers one by one on both sides of the core board, preparing stacked layer vias on the laminated stacked layers by a laser micro-hole process, and preparing stacked layer patterns corresponding to the vias by etching until the printed circuit board is completed;

[0026] Wherein, a stacking group is formed on each side of the core board, each stacking group includes at least three stacking layers, a plurality of differential signal pairs and a plurality of grounding holes are arranged on the two stacking groups, a stacking layer in one stacking group includes a grounding layer and a signal layer, a signal line connected to the differential signal pair arranged on the signal layer fans out to the edge of the printed circuit board, and the differential signal pair and the grounding hole are respectively formed by connecting the stacking layer vias prepared on the stacking layer, or the differential signal pair and the grounding hole are respectively formed by connecting the stacking layer vias prepared on the stacking layer and the core board vias;

[0027] In a first direction from the first surface to the second surface of the printed circuit board, the ground layer and the signal layer are arranged alternately;

[0028] In a second direction from the edge to the center of the printed circuit board, the grounding holes are arranged between adjacent differential signal pairs, and part of the differential signal pairs and the grounding holes close to the center of the printed circuit board in the second direction are connected to the core board vias on the core board;

[0029] On both sides of a differential signal pair set on a signal layer, the depth of the grounding hole on the edge side close to the printed circuit board is less than the depth of the differential signal pair set on the signal layer, and the depth of the grounding hole on the edge side away from the printed circuit board is greater than the depth of the differential signal pair set on the signal layer.

[0030] The technical solutions provided by the embodiments of this specification may have the following beneficial effects:

[0031] In the embodiments of the present specification, a stacking group formed by a number of stacked layers is pressed layer by layer on the upper and lower surfaces of a core board, core board vias are prepared on the core board, and differential signal pairs and grounding holes on both sides of the core board are connected through the core board vias. When a chip is inserted on a printed circuit board, the signal pins and grounding pins on the chip can be electrically connected to each stacked layer on the printed circuit board, and high-speed signals are fanned out on the signal layer in the stacked layer, and grounding is achieved in the ground layer in the stacked layer. In addition, the differential signal pairs and the grounding holes are spaced from the edge to the center of the printed circuit board, so that the crosstalk between the differential signal pairs can be effectively suppressed by grounding, thereby improving the signal transmission reliability of the printed circuit board.

[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0034] Figure 1 It is a structural schematic diagram of a printed circuit board involved in the implementation mode of the present application;

[0035] Figure 2 is a top view of a signal layer in a printed circuit board involved in an embodiment of the present application;

[0036] Figure 3 is a top view of a signal layer in a printed circuit board involved in an embodiment of the present application;

[0037] Figure 4 is a top view of a signal layer in a printed circuit board involved in an embodiment of the present application;

[0038] Figure 5 It is a top view of differential signal pairs, pads and anti-pads in different columns in a printed circuit board involved in an embodiment of the present application;

[0039] Figure 6 It is a structural schematic diagram of a circuit board assembly involved in an embodiment of the present application;

[0040] Figure 7 It is a flow chart of a method for preparing a printed circuit board involved in the present application. DETAILED DESCRIPTION

[0041] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this specification. Instead, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.

[0042] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. The singular forms "a", "the" and "the" used in this specification and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0043] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0044] The present application provides a printed circuit board 100, such as Figure 1 As shown, including:

[0045] A core board 1, which may include a substrate 10 and metal layers 11 attached to two surfaces of the substrate 10, and a core board via 12 penetrating the core board 1 is provided on the core board 1, and the core board via 12 may be formed by drilling, electroplating, plugging and surface copper coating, so that the metal layer 11 on one surface of the substrate 10 is connected to the metal layer 11 on the other surface through the core board via 12;

[0046] Two stacking groups 2, 3 are pressed onto two surfaces 1A, 1B of the core board, respectively. Each stacking group 2, 3 includes at least three stacking layers. A plurality of differential signal pairs and a plurality of grounding holes are arranged on the two stacking groups 2, 3. The stacking layers in one stacking group 2, 3 include a grounding layer and a signal layer. The signal lines connected to the differential signal pairs arranged on the signal layer fan out toward the edge of the printed circuit board 100.

[0047] Wherein, in a first direction X from the first surface 100A to the second surface 100B of the printed circuit board 100, the ground layer and the signal layer are arranged alternately;

[0048] In a second direction Y from the edge to the center of the printed circuit board 100, the grounding holes are arranged between adjacent differential signal pairs, and part of the differential signal pairs and the grounding holes close to the center of the printed circuit board 100 in the second direction Y are connected to the core board vias 12 on the core board 1;

[0049] On both sides of the differential signal pair set on a signal layer, the depth of the grounding hole close to the edge of the printed circuit board 100 is less than the depth of the differential signal pair set on the signal layer, and the depth of the grounding hole away from the edge of the printed circuit board 100 is greater than the depth of the differential signal pair set on the signal layer.

[0050] like Figure 1 As shown, a core board via 12 is formed between the upper surface 1A and the lower surface 1B of the core board 1, and the position of the core board via 12 is close to the middle of the printed circuit board 100, while no core board via 12 is provided near the edge of the printed circuit board 100. Since a chip will be soldered or plugged into one side of the printed circuit board 100, the chip is provided with signal pins and ground pins, and some of the signal pins and ground pins fan out from the stacking group 2 on the upper surface 1A side of the core board 1, and the other part of the signal pins and ground pins fan out from the stacking group 3 on the lower surface 1B side of the core board 1, so that the signal lines led out on both sides can be isolated, thereby reducing mutual crosstalk.

[0051] exist Figure 1 In the example shown, an insulating layer 4A, 4B (which may be a resin layer) is covered on the upper surface 1A and the lower surface 1B of the core board 1 for lamination, the first stacking group 2 is laminated on one side of the upper surface 1A of the core board 1, and the second stacking group 3 is laminated on one side of the lower surface 1B. In the first stacking group 2, there are five stacking layers 20, 21, 22, 23, 24 and a top layer 40 covering the first stacking group 2, and in the second stacking group 3, there are three stacking layers 30, 31, 32, 33, 34 and a bottom layer 41 covering the second stacking group 3. Each stacking layer includes an insulating material layer and a metal layer. The insulating material layer is used to separate the metal layers in the two stacking layers. The metal layer is used to prepare graphics, such as signal lines, pads, and anti-pads for isolating ground vias. The specific preparation method of each structure is similar to the current implementation and will not be repeated. Among them, the top layer 40 and the bottom layer 41 can be metal layers, wherein the insulating layer is laminated to the insulating layers of the first stacking group 2 and the second stacking group 3.

[0052] Among them, the five stacking layers of the first stacking group 2 from the first surface 100A of the printed circuit board 100 to the upper surface 1A of the core board 1 can be the first ground layer 20, the first signal layer 21, the second ground layer 22, the second signal layer 23 and the third ground layer 24 in sequence, and the second stacking group 3 from the second surface 100B of the printed circuit board 100 to the lower surface 1B of the core board 1 can be the fourth ground layer 30, the third signal layer 31, the fifth ground layer 32, the fourth signal layer 33 and the sixth ground layer 34 in sequence. The first signal layer 21 can be provided with a first differential signal pair, the second signal layer 23 can be provided with a second differential signal pair, the third signal layer 31 can be provided with a third differential signal pair, and the fourth signal layer 33 can be provided with a fourth differential signal pair. The number of the first differential signal pairs, the number of the second differential signal pairs, the number of the third differential signal pairs and the number of the fourth differential signal pairs can be multiple, and the differential signal pairs on one signal layer can be arranged in multiple rows and columns, such as Figure 2 As shown, it is a top view of the first signal layer, where the settings in the up and down direction are columns, and the settings in the left and right direction are rows. The specific number of rows and columns can be set according to actual needs without limitation.

[0053] It should be noted that the number of stacking layers set in the first stacking group 2 and the second stacking group 3 can be more than 3, and the number of differential signal pairs corresponding to the signal input pins in the signal pins of the chip and the number of differential signal pairs corresponding to the signal output pins in the signal pins of the chip are consistent. If the number of differential signal pairs set on each signal layer is the same, in order to keep the number of differential signal pairs of the input signal and the number of differential signal pairs of the output signal consistent, the same number of signal layers needs to be set in the first stacking group 2 and the second stacking group 3 on the printed circuit board 100. That is, in the printed circuit board 100, the first stacking group 2 and the second stacking group 3 on both sides of the core board 1 can form a symmetrical structure.

[0054] by Figure 1 Taking the figure as an example, when showing the leap-layer setting of the differential signal pair, only one via of the differential signal pair starting from the signal layer is shown on a signal layer, and only one via of the ground hole starting from the ground layer is shown on a ground layer as an example to more clearly show the leap-layer setting of the vias on the printed circuit board 100, and it is not used as a limitation on the number of differential signal pairs set on the signal layer and the number of ground holes set on the ground layer.

[0055] from Figure 1In the example shown, it can be seen that on the printed circuit board 100, the first grounding layer 20 is located at the uppermost layer in the first stacking group 2, the top layer 40 is drilled downward from the first surface 100A, and grounding vias 20A are prepared to the first grounding layer 20 and connected to the metal layer in the first grounding layer 20. Since the top layer 40 is generally used for grounding, the metal layer in the first grounding layer 20 can be connected to the metal layer in the top layer through the grounding vias 20A.

[0056] In the first stacking group 2, the first signal layer 21 is located one layer below the first ground layer 20. The signal via 21A formed after drilling extends from the top layer 40 through the first ground layer 20 to the first signal layer 21. In addition, when the signal via 21A passes through the first ground layer 20, an anti-pad needs to be etched to avoid short circuit. When the chip is connected, the signal pin can be connected to the signal line set on the first signal layer 21 through the signal via 21A and fan out to the edge of the printed circuit board 100. In the above description, a differential signal pair can include a pad located on the signal layer and a signal via extending to the signal layer, and a grounding hole can also include a pad located on the grounding layer and a grounding via extending to the grounding layer.

[0057] In the first stacking group 2, the second ground layer 22 is located below the first signal layer 21. The ground via 22A formed after drilling extends from the top layer 40 through the first ground layer 20 and the first signal layer 21 to the second ground layer 22, so that when the chip is connected, the ground pin can be connected to the second ground layer 22 through the ground via 22A to achieve grounding.

[0058] In the first stacking group 2, the second signal layer 23 is located one layer below the second ground layer 22. The signal via 23A formed after drilling passes through the first ground layer 20, the first signal layer 21 and the second ground layer 22 from the top layer 40. When the signal via 21A passes through the first ground layer 20 and the second ground layer 22, an anti-pad needs to be etched to avoid short circuit. When the chip is connected, the signal pin can be connected to the signal line set on the second signal layer 23 through the signal via 23A and fan out to the edge of the printed circuit board 100.

[0059] In the first stacking group 2, the third ground layer 24 is located below the second signal layer 23. The ground via 24A formed after drilling passes through the first ground layer 20, the first signal layer 21, the second ground layer 22 and the second signal layer 23 from the top layer 40, so that when the chip is connected, the ground pin can be connected to the third ground layer 24 through the ground via 24A to achieve grounding.

[0060] On the other side of the core board 1, i.e., the lower surface 1B, a second stacking group 3 is provided. Since the chip will be provided on one side surface of the printed circuit board 100, i.e., the first surface 100A, in order to fan out some signal pins of the chip and realize grounding of the ground pins, it is necessary to extend from the first surface 100A of the printed circuit board 100 downward through the first stacking group 2 and the core board 1 to the second stacking group 3 through signal vias and ground vias, and in the second stacking group 3, along the second direction Y, the signal vias and ground vias also need to meet the requirement of gradually increasing depth in the first direction X.

[0061] Specifically, on the second stacking layer 3, the fourth grounding layer 30 is close to the lower surface 1B of the core board 1, and the grounding via 30A of the fourth grounding layer 30 needs to be configured to extend downward from the first surface 100A of the printed circuit board 100 through the top layer 40, the first grounding layer 20, the first signal layer 21, the second grounding layer 22, the second signal layer 23, the third grounding layer 24, the core board 1, and the insulating layer 4B pressed on the lower surface 1B of the core board 1 to reach the fourth grounding layer 30. The grounding via 30A can be understood as being divided into two parts by the core board 1, namely, the part located in the first stacking group 2 and the part located in the second stacking group 2, and the two parts are connected through the core board via 12 corresponding to the core board 1.

[0062] Similarly, the signal via 31A of the third signal layer 31 needs to extend downward in sequence through the top layer 40, the first ground layer 20, the first signal layer 21, the second ground layer 22, the second signal layer 23, the third ground layer 24, the insulating layer 4A pressed onto the upper surface 1A of the core board 1, the core board 1, the insulating layer 4B pressed onto the lower surface 1B of the core board 1, and the fourth ground layer 30 to reach the metal layer in the third signal layer 31.

[0063] The ground via 32A of the fifth ground layer 32 needs to extend downward in sequence through the top layer 40, the first ground layer 20, the first signal layer 21, the second ground layer 22, the second signal layer 23, the third ground layer 24, the insulating layer 4A pressed onto the upper surface 1A of the core board 1, the core board 1, the insulating layer 4B pressed onto the lower surface 1B of the core board 1, the fourth ground layer 30, and the third signal layer 31 to reach the metal layer in the fifth ground layer 32.

[0064] The signal via 33A of the fourth signal layer 33 needs to extend downward in sequence through the top layer 40, the first ground layer 20, the first signal layer 21, the second ground layer 22, the second signal layer 23, the third ground layer 24, the insulating layer 4A pressed onto the upper surface 1A of the core board 1, the core board 1, the insulating layer 4B pressed onto the lower surface 1B of the core board 1, the fourth ground layer 30, the third signal layer 31, and the fifth ground layer 32 to reach the metal layer of the fourth signal layer 33.

[0065] The grounding via 34A of the sixth grounding layer 34 needs to extend downward in sequence through the top layer 40, the first grounding layer 20, the first signal layer 21, the second grounding layer 22, the second signal layer 23, the third grounding layer 24, the insulating layer 4A pressed onto the upper surface 1A of the core board 1, the core board 1, the insulating layer 4B pressed onto the lower surface 1B of the core board 1, the fourth grounding layer 30, the third signal layer 31, the fifth grounding layer 32, and the fourth signal layer 33 to reach the metal layer in the sixth grounding layer 34.

[0066] In the first stacking group 2, the depths of the ground vias 20A of the first grounding layer 20, the signal vias 21A of the first signal layer 21, the ground vias 22A of the second grounding layer 22, the signal vias 23A of the second signal layer 23, and the ground vias 24A of the third grounding layer 24 are from shallow to deep, i.e., closer to the upper surface 1A of the core board 1. In the second stacking group 3, the depths of the ground vias 30A of the fourth grounding layer 30, the signal vias 31A of the third signal layer 31, the ground vias 32A of the fifth grounding layer 32, the signal vias 33A of the fourth signal layer 33, and the ground vias 34A of the sixth grounding layer 34 are from shallow to deep, i.e., farther away from the lower surface 1B of the core board 1. Such an arrangement enables staggered arrangement between different stacking layers, and the signal vias between adjacent signal layers can be blocked from crosstalk by the ground vias. For example, the ground via 22A is deeper than the signal via 21A but shallower than the signal via 23A. On the one hand, this avoids interference with the fan-out of the signal line connected to the second signal layer 23 by the signal via 23A, and on the other hand, it can more reliably prevent crosstalk between the signal via 21A and the signal via 23A.

[0067] Optionally, at least two columns of differential signal pairs are arranged on a signal layer, and a differential signal pair includes a first differential signal hole close to the edge of the printed circuit board 100 and a second differential signal hole away from the edge of the printed circuit board 100, the first differential signal hole fans out through a first signal line, and the second differential signal hole fans out through a second signal line.

[0068] Taking the first signal layer 21 as an example, Figure 2 For example, it is a partial top view of the first signal layer 21, which shows two rows and two columns of differential signal pairs 5. One of the differential signal pairs 5 may include a first differential signal hole 50 and a second differential signal hole 51, wherein the first differential signal hole 50 is closer to the edge of the printed circuit board 100, and the second differential signal hole 51 is closer to the center of the printed circuit board 100.

[0069] Since the first differential signal hole 50 and the second differential signal hole 51 need to fan out to the edge of the printed circuit board 100 respectively, the first differential signal hole 50 needs to be connected to the first signal line 60 fan-out on the first signal layer 20, and the second differential signal hole 51 needs to be connected to the second signal line 61 fan-out on the first signal layer 20.

[0070] When there are multiple columns of differential signal pairs 5 on the same signal layer, two adjacent columns of differential signal pairs 5 belonging to the same row need to be staggered. Of course, on the same signal layer, the differential signal pairs may also include one or more columns, which is not limited.

[0071] Optional, such as Figure 3 As shown, the first signal line 60 includes an avoidance section 60A and a return section 60B, wherein the first end of the avoidance section 60A is connected to the first differential signal hole 50 in a differential signal pair and is bent toward a side away from the second differential signal hole 51 in the differential signal pair, and the return section 60B is connected to the second end of the avoidance section 60A and is bent toward a side close to the second differential signal hole 51 in the differential signal pair.

[0072] from Figure 3 It can be seen that in a differential signal pair 5, the first differential signal hole 50 is located on the left side of the second differential signal hole 51 (i.e., close to the center of the printed circuit board 100), and the second differential signal hole 51 is relatively located close to the edge of the printed circuit board 100. Therefore, in the process of the first signal line 60 connected to the first differential signal hole 50 fanning out, it needs to pass through the position where the second differential signal hole 51 is located. Compared with the crosstalk effect of one signal line on another signal line, the influence of the via on the signal line is greater. Making the distance between the signal line and the via meet the requirements can greatly reduce the crosstalk of the via. Therefore, in the process of the first signal line 60 fanning out, it needs to be kept moderately away from the via.

[0073] A specific method may be to start from the position where the first signal line 60 is connected to the first differential signal hole 50, first bend in the direction away from the second differential signal hole 51, then bend back to the side close to the second differential signal hole 51 after passing through the second differential signal hole 51, and then fan out in parallel with the second signal line 61 connected to the second differential signal hole 51. In this way, on the one hand, it is possible to avoid the via portion of the second differential signal hole 51 from generating crosstalk to the first signal line 60, and on the other hand, after avoiding the via portion of the second differential signal hole 51, it returns to the second signal line 61, avoiding the signal line of a differential signal pair occupying a large space on the edge side of the printed circuit board 100, so as to maintain a high density of signal line fan-out.

[0074] In addition, it should be noted that Figure 3Only the structure of the signal lines connected to some differential signal pairs on one signal layer is described, and the signal lines of other differential signal pairs on the signal layer can be set in the same or similar manner, or the signal lines connected to other partial differential signal pairs are set in the same or similar manner, and other differential signal pairs are implemented in other manners to meet the space requirements of the printed circuit board 100, the distance between signal lines, and the distance between signal lines and vias, and there is no limitation on this. Of course, the same or similar manner can be used for other signal layers.

[0075] Optional, such as Figure 4 As shown, the distance between the avoidance section and the second differential signal hole in the same differential signal pair is not less than the width of the signal line. For example, the width of the signal line on the printed circuit board 100 has the same or similar settings, such as W, then the distance between the avoidance section and the second differential signal hole in the same differential signal pair is not less than W;

[0076] The distance between the return segment and the second signal line connected to the second differential signal hole in the same differential signal pair is not less than the width of the signal line, and the distance between the return segment 60B and the avoidance segment of the first signal line connected to the first differential signal hole in the differential signal pair in different columns on the same signal layer is not less than three times the width of the signal line.

[0077] exist Figure 4 In the embodiment, two columns of differential signal pairs are used as an example for description. In the differential signal pair 5A in the first column, a first differential signal hole 50 and a second differential signal hole 51 are included. The first differential signal hole 50 is connected to the first signal line 60, and the second differential signal hole 51 is connected to the second signal line 61. The distance S1 between the avoidance section 60A of the first signal line 60 and the second differential signal hole 51 is not less than the width W of the signal line, so as to reduce the crosstalk caused by the second differential signal hole 51 to the first signal line 60.

[0078] For the return section 60B of the first signal line 60 , the distance S2 between it and the second signal line 61 of the second differential signal hole 51 needs to be not less than the width W of the signal line to reduce the crosstalk of the second signal line 61 to the first signal line 60 .

[0079] Moreover, there is also the influence of crosstalk between the differential signal pairs in different columns. For example, between the differential signal pair 5A in the first column and the differential signal pair 5B in the second column, there is also the risk of crosstalk between the first signal line 60 of the differential signal pair 5A and the differential signal pair 5B. Therefore, if a grounding hole cannot be provided between the two, the distance between them needs to be increased as much as possible to reduce the crosstalk.

[0080] Specifically, the first differential signal hole 52 of the differential signal pair 5B is connected to the first signal line 62, and the second differential signal hole 53 is connected to the second signal line 63. The distance S3 between the first signal line 60 of the first differential signal hole 50 of the differential signal pair 5A and the first signal line 62 of the first differential signal hole 52 of the differential signal pair 5B needs to be maintained to be not less than 3W (i.e., three times the width of the signal line) to reduce the crosstalk between the two first signal lines.

[0081] Optionally, the grounding holes between the differential signal pairs in different columns on the same signal layer are formed with a plurality of grounding hole groups, and a gap is formed between each of the grounding hole groups;

[0082] Among the differential signal pairs on the same signal layer, signal lines connected to the differential signal pairs away from the edge of the printed circuit board fan out from between adjacent ground hole groups.

[0083] like Figure 3 As shown, grounding holes 70 are provided between differential signal pairs in different columns to isolate the crosstalk between two adjacent columns of differential signal pairs. In order to improve the isolation effect of crosstalk between differential signal pairs in different columns, multiple grounding holes 70 can be provided between differential signal pairs in different columns to form a grounding hole group 7. A gap 71 can be formed between adjacent grounding hole groups 7, and the differential signal pair 5B near the center can pass through the gap 71 when fanning out to the edge of the printed circuit board 100, and pass between adjacent differential signal pairs 5A in the same column.

[0084] Optional, such as Figure 5 As shown, on the same signal layer, the signal vias of the differential signal pairs in the same column are eccentrically arranged to the same side as their own pads, and the vias of the differential signal pairs in different columns are eccentrically arranged to different sides as their own pads;

[0085] The center distance D1 between the signal via of a differential signal pair and the pad of the differential signal pair is not less than 4 mils and not more than 5 mils.

[0086] like Figure 5 As shown, the relationship between the pad and the signal via is demonstrated through the differential signal pair on the ground layer. In order to further leave more space between the differential signal pairs in different columns, the differential signal pair 5A in the first column can be moved upward relative to the larger pad 8A, and the adjacent differential signal pair 5B in the second column can be moved downward relative to the pad 8B, so that when the signal line of the differential signal pair 5B in the second column is fanned out, there can be more sufficient space, further reducing crosstalk.

[0087] Optional, such as Figure 5 As shown, an anti-pad 8C is etched and formed on the ground layer through which the signal via of the differential signal pair passes;

[0088] A distance D2 from the pad included in the differential signal pair to the edge of the anti-pad of the differential signal pair is not less than 4 mils and not more than 5 mils.

[0089] Correspondingly, the present application also provides a circuit board assembly 200, such as Figure 6 As shown, it includes a chip 9 and a printed circuit board 100 as described in any one of the above items, wherein the chip 9 is plugged into the printed circuit board 100, the signal pin 90 of the chip 9 is electrically connected to the differential signal pair, and the ground pin 91 on the chip 9 is electrically connected to the ground hole.

[0090] Optionally, the signal pin 90 on the chip 9 includes an input pin 90A and an output pin 90B, wherein the input pin 90A is close to the edge of the chip 9 , and the output pin 90B is close to the center of the chip 9 .

[0091] Of course, depending on the structure of the chip 9 , the positions of the input pin 90A and the output pin 90B may be different, but the structural arrangement of the printed circuit board 100 is not changed.

[0092] Correspondingly, the present application also provides a method for preparing a printed circuit board, such as Figure 7 As shown, including:

[0093] S100, drilling through holes on the core board, forming core board vias by electroplating, and etching on both sides of the core board to form core board patterns.

[0094] S101 laminates the stacked layers one by one on both sides of the core board, prepares stacked layer vias on the laminated stacked layers by a laser micro-hole process, and prepares stacked layer patterns corresponding to the vias by etching until the printed circuit board is completed.

[0095] Specifically, core board vias are prepared in advance on the core board so that the differential signal pairs and grounding holes on one side of the core board can be connected to the other side of the core board. After the insulating layers are pressed on both sides of the core board, the stacking layers are pressed one by one, and the stacking layer vias are prepared and the stacking layer patterns are etched one by one through the laser micro-hole process, such as the signal vias of the signal layer and the grounding vias of the grounding layer, and the pads connected to the grounding vias and the pads connected to the signal vias are etched, and anti-pads need to be etched on the grounding layer for the signal vias.

[0096] Through the above steps, the prepared structure needs to meet the following requirements:

[0097] Wherein, a stacking group is formed on each side of the core board, each stacking group includes at least three stacking layers, a plurality of differential signal pairs and a plurality of grounding holes are arranged on the two stacking groups, a stacking layer in one stacking group includes a grounding layer and a signal layer, a signal line connected to the differential signal pair arranged on the signal layer fans out to the edge of the printed circuit board, and the differential signal pair and the grounding hole are respectively formed by connecting the stacking layer vias prepared on the stacking layer, or the differential signal pair and the grounding hole are respectively formed by connecting the stacking layer vias prepared on the stacking layer and the core board vias;

[0098] In a first direction from the first surface to the second surface of the printed circuit board, the ground layer and the signal layer are arranged alternately;

[0099] In a second direction from the edge to the center of the printed circuit board, the grounding holes are arranged between adjacent differential signal pairs, and part of the differential signal pairs and the grounding holes close to the center of the printed circuit board in the second direction are connected to the core board vias on the core board;

[0100] On both sides of a differential signal pair set on a signal layer, the depth of the grounding hole on the edge side close to the printed circuit board is less than the depth of the differential signal pair set on the signal layer, and the depth of the grounding hole on the edge side away from the printed circuit board is greater than the depth of the differential signal pair set on the signal layer.

[0101] The technical solutions provided by the embodiments of this specification may have the following beneficial effects:

[0102] In the embodiments of the present specification, a stacking group formed by a number of stacked layers is pressed layer by layer on the upper and lower surfaces of a core board, core board vias are prepared on the core board, and differential signal pairs and grounding holes on both sides of the core board are connected through the core board vias. When a chip is inserted on a printed circuit board, the signal pins and grounding pins on the chip can be electrically connected to each stacked layer on the printed circuit board, and high-speed signals are fanned out on the signal layer in the stacked layer, and grounding is achieved in the ground layer in the stacked layer. In addition, the differential signal pairs and the grounding holes are spaced from the edge to the center of the printed circuit board, so that the crosstalk between the differential signal pairs can be effectively suppressed by grounding, thereby improving the signal transmission reliability of the printed circuit board.

[0103] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0104] Those skilled in the art will readily appreciate other embodiments of the specification after considering the specification and practicing the invention claimed herein. The specification is intended to cover any variations, uses or adaptations of the specification that follow the general principles of the specification and include common knowledge or customary techniques in the art that are not claimed in the specification. The specification and examples are to be considered exemplary only, and the true scope and spirit of the specification are indicated by the following claims.

[0105] It should be understood that the present description is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

[0106] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A printed circuit board, characterized in that: include: A core plate, on which a core plate via hole penetrating the core plate is arranged; Two stacking groups are respectively pressed onto two surfaces of the core board, each stacking group comprises at least three stacking layers, a plurality of differential signal pairs and a plurality of grounding holes are arranged on the two stacking groups, a stacking layer in one stacking group comprises a grounding layer and a signal layer, and a signal line connected to the differential signal pair arranged on the signal layer is fanned out toward the edge of the printed circuit board; Wherein, in a first direction from the first surface to the second surface of the printed circuit board, the ground layer and the signal layer are arranged alternately; In a second direction from the edge to the center of the printed circuit board, the grounding holes are arranged between adjacent differential signal pairs, and part of the differential signal pairs and the grounding holes close to the center of the printed circuit board in the second direction are connected to the core board vias on the core board; On both sides of a differential signal pair set on a signal layer, the depth of the grounding hole on the edge side close to the printed circuit board is less than the depth of the differential signal pair set on the signal layer, and the depth of the grounding hole on the edge side away from the printed circuit board is greater than the depth of the differential signal pair set on the signal layer.

2. The printed circuit board according to claim 1, characterized in that: At least two columns of differential signal pairs are arranged on a signal layer, and a differential signal pair includes a first differential signal hole close to the edge of the printed circuit board and a second differential signal hole away from the edge of the printed circuit board. The first differential signal hole fans out through a first signal line, and the second differential signal hole fans out through a second signal line.

3. The printed circuit board according to claim 2, characterized in that: The first signal line includes an avoidance section and a return section, wherein a first end of the avoidance section is connected to a first differential signal hole in a differential signal pair and is bent toward a side away from a second differential signal hole in the differential signal pair, and the return section is connected to a second end of the avoidance section and is bent toward a side close to the second differential signal hole in the differential signal pair.

4. The printed circuit board according to claim 3, characterized in that: The distance between the avoidance section and the second differential signal hole in the same differential signal pair is not less than the width of the signal line; The distance between the return segment and the second signal line connected to the second differential signal hole in the same differential signal pair is not less than the width of the signal line, and the distance between the return segment and the avoidance segment of the first signal line connected to the first differential signal hole in the differential signal pair in different columns on the same signal layer is not less than three times the width of the signal line.

5. The printed circuit board according to claim 2, characterized in that: The ground holes between the differential signal pairs in different columns on the same signal layer form a plurality of ground hole groups, and a gap is formed between each ground hole group; Among the differential signal pairs on the same signal layer, signal lines connected to the differential signal pairs away from the edge of the printed circuit board fan out from between adjacent ground hole groups.

6. The printed circuit board according to claim 2, characterized in that: On the same signal layer, the signal vias of the differential signal pairs in the same column are eccentrically arranged to the same side as their own pads, and the vias of the differential signal pairs in different columns are eccentrically arranged to different sides as their own pads; Wherein, the center distance between the signal via of a differential signal pair and the pad of the differential signal pair is not less than 4 mils and not more than 5 mils.

7. The printed circuit board according to claim 2, characterized in that: An anti-pad is formed by etching on the ground layer through which the signal via of the differential signal pair passes; The distance from the pad included in the differential signal pair to the edge of the anti-pad of the differential signal pair is not less than 4 mils and not more than 5 mils.

8. A circuit board assembly, characterized in that: A printed circuit board comprising a chip and any one of claims 1 to 7, wherein the chip is plugged into the printed circuit board, a signal pin of the chip is electrically connected to the differential signal pair, and a ground pin on the chip is electrically connected to the ground hole.

9. The circuit board assembly according to claim 8, characterized in that: The signal pins on the chip include input pins and output pins, wherein the input pins are close to the edge of the chip, and the output pins are close to the center of the chip.

10. A method for preparing a printed circuit board, characterized in that: include: Drilling through holes on the core board, forming core board vias by electroplating, and etching on both sides of the core board to form core board patterns; Laminating the stacked layers one by one on both sides of the core board, preparing stacked layer vias on the laminated stacked layers by a laser micro-hole process, and preparing stacked layer patterns corresponding to the vias by etching until the printed circuit board is completed; Wherein, a stacking group is formed on each side of the core board, each stacking group includes at least three stacking layers, a plurality of differential signal pairs and a plurality of grounding holes are arranged on two stacking groups, a stacking layer in one stacking group includes a grounding layer and a signal layer, a signal line connected to a differential signal pair arranged on the signal layer fans out toward an edge of the printed circuit board, and the differential signal pair and the grounding hole are respectively formed by connecting the stacking layer vias prepared on the stacking layer, or the differential signal pair and the grounding hole are respectively formed by connecting the stacking layer vias prepared on the stacking layer and the core board vias; In a first direction from the first surface to the second surface of the printed circuit board, the ground layer and the signal layer are arranged alternately; In a second direction from the edge to the center of the printed circuit board, the grounding holes are arranged between adjacent differential signal pairs, and part of the differential signal pairs and the grounding holes close to the center of the printed circuit board in the second direction are connected to the core board vias on the core board; On both sides of a differential signal pair set on a signal layer, the depth of the grounding hole on the edge side close to the printed circuit board is less than the depth of the differential signal pair set on the signal layer, and the depth of the grounding hole on the edge side away from the printed circuit board is greater than the depth of the differential signal pair set on the signal layer.

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