Printed circuit board

Abstract

The present disclosure provides a printed circuit board, which may include: a first substrate unit including a plurality of stacked insulating layers and a plurality of stacked wiring layers disposed on or in the plurality of stacked insulating layers, respectively; the second substrate unit comprises a glass layer, a first wiring layer, a second wiring layer, an insulating layer and a third wiring layer, the first wiring layer and the second wiring layer are arranged above and below the glass layer respectively, the insulating layer is arranged above the glass layer, and the third wiring layer is arranged above the insulating layer. And a second substrate unit stacked on or embedded in the first substrate unit, in which an average pitch of circuits of each of the first wiring layer, the second wiring layer, and the third wiring layer is smaller than an average pitch of circuits of each of the plurality of stacked wiring layers.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0096506 filed on July 25, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] In a multi-chip package (MCP), technology using a silicon interposer or an embedded multi-die interconnect bridge (EMIB) using silicon (Si)-based technology is being developed instead of implementing a microcircuit for connecting heterogeneous semiconductors in a package substrate, but there may be a problem of very high cost.

[0004] On the other hand, recently, packaging technology has attempted to use glass materials (by getting rid of the use of organic materials as a traditional substrate manufacturing method) to improve the warping problem of the package, but the glass substrate may have a high risk of damaging the substrate during processes such as clamping and moving, so its yield may be reduced. Summary of the invention

[0005] An aspect of the present disclosure is to provide a printed circuit board including a microcircuit that can be manufactured at a lower cost than a silicon interposer.

[0006] Another aspect of the present disclosure is to provide a printed circuit board that can improve mass productivity by improving yield problems caused by handling, clamping, and moving of a glass substrate.

[0007] One of various solutions proposed by the present disclosure is to manufacture a micro circuit board by forming a wiring layer including a micro circuit in a glass layer and an insulating layer using a first detachable carrier, and then perform a build-up process on the micro circuit board manufactured using the first detachable carrier to realize a multi-layer substrate.

[0008] According to one aspect of the present disclosure, a printed circuit board may include: a first substrate unit, including a plurality of stacked insulating layers and a plurality of stacked wiring layers respectively arranged on or in the plurality of stacked insulating layers, each of the plurality of stacked wiring layers including a circuit; and a second substrate unit, including a glass layer, a first wiring layer and a second wiring layer respectively arranged on a first surface and a second surface of the glass layer, an insulating layer arranged on the glass layer, and a third wiring layer arranged on the insulating layer, each of the first wiring layer, the second wiring layer and the third wiring layer including a circuit, wherein the second substrate unit is stacked on or embedded in the first substrate unit, wherein the first surface of the glass layer is opposite to the second surface of the glass layer, and wherein an average pitch of the circuit of each of the first wiring layer, the second wiring layer and the third wiring layer is smaller than an average pitch of the circuit of each of the plurality of stacked wiring layers.

[0009] According to another aspect of the present disclosure, a printed circuit board may include: a first substrate unit, including a plurality of stacked insulating layers and a plurality of stacked wiring layers respectively arranged on or in the plurality of stacked insulating layers; and a second substrate unit, including a glass layer, a first wiring layer and a second wiring layer respectively arranged on a first surface and a second surface of the glass layer, an insulating layer arranged on the first surface of the glass layer, and a third wiring layer arranged on a surface of the insulating layer, wherein the first surface of the glass layer is opposite to the second surface of the glass layer, wherein the second substrate unit is stacked on or embedded in the first substrate unit, and wherein the total thickness of the plurality of stacked insulating layers is thicker than the thickness of the insulating layer.

[0010] According to another aspect of the present disclosure, a printed circuit board may include: a glass layer; a first insulating layer disposed on a first surface of the glass layer; a second insulating layer disposed on a second surface of the glass layer, wherein the second surface of the glass layer is opposite to the first surface of the glass layer; a first wiring layer disposed between the glass layer and the first insulating layer; a second wiring layer disposed on the second insulating layer; and a first via layer penetrating both the glass layer and the second insulating layer and connecting the first wiring layer and the second wiring layer.

[0011] One effect of the present disclosure is to provide a printed circuit board including a microcircuit that can be manufactured at a lower cost than a silicon interposer.

[0012] Another effect of the present disclosure is to provide a printed circuit board that can improve mass productivity by improving yield problems caused by handling, clamping, and moving of a glass substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a block diagram schematically illustrating an example of an electronic device system;

[0015] Figure 2 is a perspective view schematically showing an example of an electronic device;

[0016] Figure 3 is a cross-sectional view schematically showing a state in which a ball grid array (BGA) package is mounted on a main board of an electronic device;

[0017] Figure 4 is a cross-sectional view schematically showing a state where a silicon interposer package is mounted on a main board;

[0018] Figure 5 is a cross-sectional view schematically showing a state where an organic interposer package is mounted on a main board;

[0019] Figure 6 is a cross-sectional view schematically showing an example of a printed circuit board;

[0020] 7A to 7J is a schematic diagram showing the manufacturing Figure 6 A process cross-sectional view of an example of a second substrate unit in FIG.

[0021] FIG. 8A to FIG. 8F is a schematic diagram showing the manufacturing Figure 6 A process cross-sectional view of an example of a printed circuit board in FIG.

[0022] Fig. 9 It is schematically shown Figure 6 A cross-sectional view of a modified example of a printed circuit board in FIG.

[0023] Fig.10 is a cross-sectional view schematically showing another example of a printed circuit board;

[0024] FIG. 11A to FIG. 11G is a schematic diagram showing the manufacturing Fig.10 A process cross-sectional view of an example of a printed circuit board in FIG.

[0025] Fig.12 It is schematically shown Fig.10 A cross-sectional view of a modified example of a printed circuit board in FIG.

[0026] Fig.13 is a cross-sectional view schematically showing another example of a printed circuit board;

[0027] FIG. 14A to FIG. 14J is a schematic diagram showing the manufacturing Fig.13 A process cross-sectional view of an example of a second substrate unit in FIG.

[0028] FIG. 15A to FIG. 15F is a schematic diagram showing the manufacturing Fig.13 A process cross-sectional view of an example of a printed circuit board in FIG.

[0029] Fig.16 It is schematically shown Fig.13 A cross-sectional view of a modified example of a printed circuit board in FIG.

[0030] Fig.17 is a cross-sectional view schematically showing another example of a printed circuit board;

[0031] FIG. 18A to FIG. 18G is a schematic diagram showing the manufacturing Fig.17 A process cross-sectional view of an example of a printed circuit board in FIG. 1 ; and

[0032] Fig.19 It is schematically shown Fig.17 sectional view of a modified example of the printed circuit board in FIG. DETAILED DESCRIPTION

[0033] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer description, the shapes and sizes of elements in the drawings may be exaggerated or reduced.

[0034] Electronic Devices

[0035] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0036] Reference Figure 1 , the electronic device 1000 may accommodate a mainboard 1010. Chip-related components 1020, network-related components 1030, other components 1040, etc. are physically and / or electrically connected to the mainboard 1010. These components may also be connected to other electronic components described below via various signal lines 1090.

[0037] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, etc.); application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0038] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wireless Fidelity (Wi-Fi) (such as the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Enhanced Digital Cordless Telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G) protocols, fourth generation mobile communication technology (4G) protocols, and fifth generation mobile communication technology (5G) protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also include components compatible with or operating according to any of a variety of other wireless standards or protocols and wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020.

[0039] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited thereto, and may also include passive components in the form of chip components for various other purposes. In addition, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0040] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically or electrically connected to the mainboard 1010 or that are not physically or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080, etc. However, these other electronic components are not limited thereto, but may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive (HDD)), a compact disc (CD), a digital versatile disc (DVD), etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components for various purposes.

[0041] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may also be any other electronic device that processes data.

[0042] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0043] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. The smart phone 1100 may house a mainboard 1110, and various components 1120 may be physically connected or electrically connected to the mainboard 1110. In addition, the smart phone 1100 may house other electronic components that are physically connected or electrically connected to the mainboard 1110 or are not physically connected or electrically connected to the mainboard 1110, such as a camera module 1130 and / or a speaker 1140. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component including active components and / or passive components is surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are embedded. On the other hand, the electronic device need not be limited to the smart phone 1100, and may be other electronic devices as described above.

[0044] Semiconductor Package

[0045] Generally, many fine circuits are integrated in a semiconductor chip. However, the semiconductor chip itself may not be used as a finished semiconductor product and may be damaged due to external physical impact or chemical impact. Therefore, instead of using the semiconductor chip itself, it may be packaged in a packaged state and used in an electronic device or the like.

[0046] Here, since there is a difference in the circuit width between the semiconductor chip and the mainboard of the electronic device in terms of electrical connection, a semiconductor packaging technology is required. In detail, the size of the connection pad of the semiconductor chip and the interval between the connection pads of the semiconductor chip are very fine, but the size of the component mounting pad of the mainboard used in the electronic device is significantly larger than the size of the connection pad of the semiconductor chip, and the interval between the component mounting pads of the mainboard used in the electronic device is significantly larger than the interval between the connection pads of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and a packaging technology for buffering the circuit width difference between the semiconductor chip and the mainboard is required.

[0047] Hereinafter, a semiconductor package including an interposer manufactured by such a packaging technology will be described in more detail with reference to the accompanying drawings.

[0048] Figure 3 is a cross-sectional view schematically showing a state in which a BGA package is mounted on a main board of an electronic device.

[0049] Among semiconductor chips, a chip provided in an application specific integrated circuit (ASIC) such as a graphics processing unit (GPU) is very expensive, and therefore, performing packaging with a high yield may be very critical. To this end, a ball grid array (BGA) substrate 2210 capable of redistributing thousands to millions of connection pads may be prepared before mounting the semiconductor chip, and an expensive semiconductor chip such as a GPU 2220 may be mounted on the BGA substrate 2210 and packaged by a surface mounting technology (SMT), and then finally mounted on the main board 2110.

[0050] In addition, in the case of the GPU 2220, it may be necessary to significantly reduce the signal path to the memory such as the high bandwidth memory (HBM 2240), and for this purpose, a semiconductor chip such as the HBM 2240 is generally mounted on the interposer 2230, then packaged, and stacked and used in the form of a package on package (POP) on the package on which the GPU 2220 is mounted. However, in this case, the thickness of the device may increase significantly, and there may be limitations in reducing the signal path.

[0051] Figure 4 is a cross-sectional view schematically showing a state where a silicon interposer package is mounted on a main board.

[0052] In order to solve the above problems, a semiconductor package 2310 including an organic interposer may be considered, which uses an interposer technology that mounts a first semiconductor chip (such as a GPU 2220) and a second semiconductor chip (such as an HBM 2240) side by side on a silicon interposer 2250 and packages the semiconductor chips. In this case, the GPU 2220 and the HBM 2240 having thousands to millions of connection pads may be redistributed through the silicon interposer 2250 and may be electrically connected with a minimum path. In addition, when the semiconductor package 2310 including an organic interposer is mounted again on a BGA substrate 2210 or the like and redistributed, the semiconductor package 2310 may be finally mounted on the mainboard 2110.

[0053] However, in the case of the silicon interposer 2250 , it may be difficult to form a through silicon via (TSV) and the manufacturing cost may also be high, which may be disadvantageous for a large area and low cost.

[0054] Figure 5 is a cross-sectional view schematically showing a state in which an organic interposer package is mounted on a main board.

[0055] In order to solve the above-mentioned problems, an organic interposer 2260 may be used instead of the silicon interposer 2250. For example, a semiconductor package 2320 including an organic interposer may be manufactured using an interposer technology that mounts a first semiconductor chip (such as a GPU 2220) and a second semiconductor chip (such as an HBM 2240) side by side on the surface of the organic interposer 2260 and packages the semiconductor chips. In this case, the GPU 2220 and the HBM 2240 having thousands to millions of connection pads may be redistributed through the organic interposer 2260, and furthermore, the GPU 2220 and the HBM 2240 may be electrically connected to each other through significantly reduced paths. In addition, by remounting the semiconductor package 2320 including the organic interposer on a BGA substrate 2210 or the like and redistributing the semiconductor package 2320, the semiconductor package may be finally mounted on the mainboard 2110. Therefore, a large area may be achieved at a low cost.

[0056] However, in the case of using the organic interposer 2260, the GPU 2220 and the HMB 2240 must be mounted on the organic interposer 2260 and then mounted again on the BGA substrate 2210, so the process may be somewhat complicated and the package yield may be reduced.

[0057] Printed Circuit Board

[0058] Figure 6 is a cross-sectional view schematically showing an example of a printed circuit board.

[0059] Reference Figure 6According to an example, a printed circuit board 300A may include a first substrate unit 100A and a second substrate unit 200A stacked on the first substrate unit 100A. The first substrate unit 100A may include a plurality of buildup insulating layers 111, a plurality of buildup wiring layers 121 respectively disposed on or in the plurality of buildup insulating layers 111, and a plurality of buildup via layers 131 respectively penetrating at least one of the plurality of buildup insulating layers 111. The second substrate unit 200A may include a glass layer 211, a first wiring layer 221 and a second wiring layer 222 disposed above and below the glass layer 211, respectively (e.g., on the upper and lower surfaces (e.g., the first and second surfaces) of the glass layer 211), an insulating layer 212 disposed above the glass layer 211 (e.g., on the upper surface (e.g., the first surface) of the glass layer 211), a third wiring layer 223 disposed above the insulating layer 212 (e.g., on the upper surface of the insulating layer 212), a first via layer 231 penetrating the glass layer 211 and connecting the first wiring layer 221 and the second wiring layer 222, and a second via layer 232 penetrating the insulating layer 212 and connecting the first wiring layer 221 and the third wiring layer 223. The second substrate unit 200A may be stacked on the uppermost (or outermost) buildup insulating layer 111 so as to completely cover the buildup insulating layer 111 disposed on the uppermost (or outermost) side among the plurality of buildup insulating layers 111 of the first substrate unit 100A. The second substrate unit 200A may include an interconnection region R1 including a microcircuit for die-to-die connection and a wiring region R2 for die-to-substrate connection.

[0060] In this case, each of the first wiring layer 221, the second wiring layer 222, and the third wiring layer 223 of the second substrate unit 200A may include a circuit with a density (e.g., wiring density) that is relatively higher than the density of each of the plurality of built-up wiring layers 121 of the first substrate unit 100A. For example, including a circuit with a relatively high density may mean including a relatively fine circuit. For example, each of the first wiring layer 221, the second wiring layer 222, and the third wiring layer 223 may have a relatively smaller thickness, line width / spacing, and pitch, etc. than each of the plurality of built-up wiring layers 121. For example, the average pitch of each circuit of the first wiring layer 221, the second wiring layer 222, and the third wiring layer 223 may be smaller than the average pitch of each circuit of the plurality of built-up wiring layers 121. The average pitch of the circuit may be determined based on each trace pattern. In addition, the average spacing between adjacent layers between the first wiring layer 221, the second wiring layer 222, and the third wiring layer 223 may be smaller than the average spacing between adjacent layers between the plurality of built-up wiring layers 121. In addition, the thickness of each of the glass layer 211 and the insulating layer 212 may be thinner than the thickness of each of the plurality of stacked insulating layers 111. In addition, the total thickness of the plurality of stacked insulating layers 111 may be thicker than the thickness of the insulating layer 212. In addition, the total number of layers of the plurality of stacked insulating layers 111 may be greater than the total number of layers of the insulating layer 212. In some embodiments, the plurality of stacked insulating layers 111 may have more layers than the insulating layer 212. The total thickness of the plurality of stacked insulating layers 111 may be greater than the total thickness of the insulating layer 212.

[0061] In this way, the printed circuit board 300A according to the example forms the second substrate unit 200A by forming the first wiring layer 221, the second wiring layer 222 and the third wiring layer 223 including the microcircuit on the glass layer 211 and the insulating layer 212, and the second substrate unit 200A can be used as a microcircuit board capable of die-to-die interconnection. Therefore, the printed circuit board 300A can replace conventional silicon interposers, etc., and can be manufactured at a lower cost. In addition, since the glass layer 211 is included, a substrate having a low thermal expansion coefficient and a high modulus compared to a typical organic substrate can be manufactured, and the substrate can be made thinner. In addition, a glass-organic hybrid substrate can be realized by combining the glass layer 211 with the insulating layer 212, thereby solving the problems caused by handling, clamping and moving the substrate, and improving mass production rate. In addition, on its opposite side, a first substrate unit 100A of a multilayer substrate including a plurality of stacked insulating layers 111 and a plurality of stacked wiring layers 121 is formed by a stacking process. Therefore, the first substrate unit 100A can be used as a multilayer packaging substrate.

[0062] In addition, in the cross-sectional view, each of the first via layer 231 and the second via layer 232 may be tapered in a direction opposite to each of the plurality of stacked via layers 131. For example, as in the process described below, when the second substrate unit 200A is formed using the first detachable carrier, the insulating layer 212 may be stacked in only one direction based on the glass layer 211, and in the process, the first via layer 231 and the second via layer 232 may be formed. In addition, when the first substrate unit 100A is formed on the second substrate unit 200A using the first detachable carrier, the plurality of stacked insulating layers 111 may be stacked in only a direction opposite to the direction in which the insulating layers 212 are stacked based on the glass layer 211, and in the process, the plurality of stacked via layers 131 may be formed. Therefore, in the cross-sectional view, each of the first via layer 231 and the second via layer 232 may be tapered in a direction opposite to each of the plurality of stacked via layers 131.

[0063] Furthermore, in the cross-sectional view, the width of the upper end (e.g., the first end) of each via of the first via layer 231 and the second via layer 232 may be narrower than the width of the lower end (e.g., the first end) of each via of the plurality of stacked via layers 131. In addition, the average spacing between the vias of each of the first via layer 231 and the second via layer 232 may be smaller than the average spacing between the vias of each of the plurality of stacked via layers 131. For example, the first wiring layer 221, the second wiring layer 222, and the third wiring layer 223 may be formed to have a relatively finer and higher density than the plurality of stacked wiring layers 121, and therefore, the first via layer 231 and the second via layer 232 connected to the first wiring layer 221, the second wiring layer 222, and the third wiring layer 223 may be formed to have a relatively finer and higher density than the plurality of stacked via layers 131 connected to the plurality of stacked wiring layers 121.

[0064] In addition, the first wiring layer 221 and the second wiring layer 222 and the first via layer 231 may be in direct contact with the glass layer 211. For example, the first wiring layer 221 and the second wiring layer 222 and the first via layer 231 may be directly formed on the glass layer 211, and therefore, a separate insulating material or resin material may not be provided between each of the first wiring layer 221 and the second wiring layer 222 and the glass layer 211 and between the first via layer 231 and the glass layer 211. Since the first wiring layer 221 and the first via layer 231 are formed integrally with each other, their boundaries may not be easily recognized at the connection portion, but since the second wiring layer 222 and the first via layer 231 are each formed by a separate plating process, their boundaries may be easily recognized at their connection portion.

[0065] Hereinafter, components of a printed circuit board 300A according to an embodiment will be described in more detail with reference to the accompanying drawings.

[0066] Each of the plurality of insulating layers 111 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material including an inorganic filler, an organic filler and / or glass fiber (for example, a glass fabric such as glass cloth) and these resins. For example, the insulating material may be a non-photosensitive insulating material (such as Ajinomoto built-up film (ABF) or prepreg (PPG)), but the present disclosure is not limited thereto, and other polymer materials may be used. In addition, the insulating material may be a photosensitive insulating material (such as a photosensitive dielectric (PID)). The plurality of insulating layers 111 may include substantially the same insulating material, or may include insulating materials different from each other.

[0067] Each of the plurality of built-up wiring layers 121 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The metal may include copper (Cu), but the present disclosure is not limited thereto. Depending on the design, each of the plurality of built-up wiring layers 121 may perform various functions. For example, the plurality of built-up wiring layers 121 may include a signal pattern, a power pattern, and a ground pattern. Each of these patterns may have various forms (such as traces, planes, and pads). The plurality of built-up wiring layers 121 may each include an electroless plating layer (or chemical copper plating layer) and an electrolytic plating layer (or electrolytic copper plating layer). Alternatively, the plurality of built-up wiring layers 121 may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper plating layer). Alternatively, the plurality of built-up wiring layers 121 may include a metal foil (or copper foil), an electroless plating layer (or chemical copper plating layer), and an electrolytic plating layer (or electrolytic copper plating layer). A sputtered layer may be included instead of an electroless layer (or chemical copper layer), and both may be included if desired.

[0068] Each of the plurality of stacked via layers 131 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The metal may include copper (Cu), but the present disclosure is not limited thereto. Each of the plurality of stacked via layers 131 may include a filled via that fills the via hole, or may include a conformal via disposed along the wall surface of the via hole. The plurality of stacked via layers 131 may perform various functions according to the design. For example, the plurality of stacked via layers 131 may include a ground via, a power via, and a signal via. In a cross-sectional view, the plurality of stacked via layers 131 may have a tapered shape in the same direction, for example, a tapered shape in which the width of the lower end is wider than the width of the upper end. Each of the plurality of stacked via layers 131 may include an electroless plating layer (or a chemical copper plating layer) and an electrolytic plating layer (or an electrolytic copper plating layer). A sputtered layer may be included instead of an electroless layer (or chemical copper layer), and both may be included if desired.

[0069] The glass layer 211 may include glass that is an amorphous solid. The glass may include, for example, pure silicon dioxide (approximately 100% SiO 2 ), soda-lime glass, borosilicate glass, and aluminosilicate glass. However, the present disclosure is not limited thereto, and alternative glass materials (such as fluorine glass, phosphate glass, chalcogenide glass, etc.) may also be used as materials. Other additives may also be included to form glass with specific physical properties. These additives may include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also one or more of magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides thereof with other elements.

[0070] The glass layer 211 may be a layer different from an organic insulating material (e.g., copper clad laminate (CCL), prepreg (PPG), etc.) including glass fiber (e.g., glass fabric such as glass cloth). For example, the glass layer 211 may include flat glass. The glass layer 211 may be a core layer. For example, the glass layer may be a glass core.

[0071] The insulating layer 212 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material including an inorganic filler, an organic filler and / or glass fiber (for example, a glass fabric such as glass cloth) and these resins. For example, the insulating material may be a non-photosensitive insulating material (such as Ajinomoto built-up film (ABF) or a prepreg (PPG)), but the present disclosure is not limited thereto, and other polymer materials may be used. In addition, the insulating material may be a photosensitive insulating material (such as a photosensitive dielectric (PID). The insulating layer 212 may include the same insulating material as the insulating material of the plurality of insulating layers 111, or may include an insulating material different from the insulating material of the plurality of insulating layers 111.

[0072] Each of the first wiring layer 221, the second wiring layer 222, and the third wiring layer 223 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or their alloys. The metal may include copper (Cu), but the present disclosure is not limited thereto. Each of the first wiring layer 221, the second wiring layer 222, and the third wiring layer 223 may perform various functions according to the design. For example, the first wiring layer 221, the second wiring layer 222, and the third wiring layer 223 may include a signal pattern, a power pattern, and a ground pattern. Each of these patterns may have various shapes (such as traces, planes, and pads). Each of the plurality of built-up wiring layers 121 may include an electroless plating layer (or a chemical copper plating layer) and an electrolytic plating layer (or an electrolytic copper plating layer). Alternatively, each of the plurality of built-up wiring layers 121 may include a metal foil (or a copper foil) and an electrolytic plating layer (or an electrolytic copper plating layer). Alternatively, each of the plurality of built-up wiring layers 121 may include a metal foil (or a copper foil), an electroless plating layer (or an electroless copper plating layer), and an electrolytic plating layer (or an electrolytic copper plating layer). A sputtering layer may be included instead of the electroless plating layer (or the electroless copper plating layer), and both of them may be included if necessary.

[0073] Each of the first via layer 231 and the second via layer 232 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The metal may include copper (Cu), but the present disclosure is not limited thereto. Each of the first via layer 231 and the second via layer 232 may include a filled via that fills the via hole, or may include a conformal via disposed along the wall surface of the via hole. The first via layer 231 and the second via layer 232 may perform various functions according to the design. For example, the first via layer 231 and the second via layer 232 may include a ground via, a power via, and a signal via. In a cross-sectional view, the first via layer 231 and the second via layer 232 may have a tapered shape in the same direction, for example, a tapered shape in which the width of the upper end is wider than the width of the lower end. Each of the first and second via layers 231 and 232 may include an electroless plating layer (or chemical copper plating layer) and an electrolytic plating layer (or electrolytic copper plating layer). A sputtering layer may be included instead of the electroless plating layer (or chemical copper plating layer), and both of them may be included if necessary.

[0074] 7A to 7J is a schematic diagram showing the manufacturing Figure 6 A process cross-sectional view of an example of the second substrate unit in FIG.

[0075] Reference Fig. 7A, prepare a first detachable carrier 410. The first detachable carrier 410 may have a multilayer structure including, for example, a core layer, copper foils stacked on both surfaces of the core layer, a bonding layer stacked on the copper foil, and a metal layer stacked on the bonding layer. Next, the glass layer 211 is stacked on the first detachable carrier 410.

[0076] Reference Figure 7B , a via hole v is processed in the glass layer 211 using a drill. In this case, the metal layer in the first detachable carrier 410 may be used as a stopper.

[0077] Reference Figure 7C , forming a seed layer m1. The seed layer m1 may cover the wall surface of the via hole v, the surface of the glass layer 211, and the exposed portion of the first detachable carrier 410. The seed layer m1 may be formed by electroless plating (eg, chemical copper plating). Alternatively, the seed layer m1 may be formed by sputtering.

[0078] Reference Fig.7D After the dry film 420 is formed, the dry film 420 is patterned by a photolithography process.

[0079] Reference Fig. 7E , forming the plating layer m2. The plating layer m2 may be formed by electrolytic plating (eg, electrolytic copper plating).

[0080] Reference Figure 7F , removing the dry film 420. The dry film 420 may be removed using a stripping solution.

[0081] Reference Figure 7G The seed layer m1 formed in the region other than the region where the plating layer m2 is formed is removed by etching. The first wiring layer 221 and the first via layer 231 may be formed in the glass layer 211 through a series of processes.

[0082] Reference Figure 7H , an insulating layer 212 is formed on the glass layer 211, and a via hole processing process, a seed layer forming process, and a plating layer forming process are repeated to form a third wiring layer 223 and a second via hole layer 232. The insulating layer 212 may be formed by stacking an insulating film in an uncured film state and curing it, or by applying a material for forming the insulating layer 212 and curing it. The via hole may be formed by laser processing.

[0083] Reference Fig.7I , the stacked body is separated from the first detachable carrier 410. In this case, the copper foil may be separated from the core layer, and the copper foil, adhesive layer, metal layer, etc. remaining on the stacked body after the core layer is separated may be removed by an appropriate method.

[0084] Reference Figure 7J, a second wiring layer 222 is formed on the lower surface of the glass layer 211. The second wiring layer 222 may be formed in a plating process using a semi-additive process (SAP), a modified SAP (MSAP), a via sealing (TT) process, etc. Then, a surface treatment may be performed as needed.

[0085] The second substrate unit 200A can be formed by a series of processes. In addition, in the process diagram, for the convenience of explanation, the shape of the pattern is more simply represented. In this way, in the process using the first detachable carrier 410, the first wiring layer 221, the second wiring layer 222 and the third wiring layer 223 and the first via layer 231 and the second via layer 232 can be directly formed on the glass layer 211 and the insulating layer 212, respectively, so as to have the above-mentioned technical effects.

[0086] FIG. 8A to FIG. 8F is a schematic diagram showing the manufacturing Figure 6 A process cross-sectional view of an example of a printed circuit board.

[0087] Reference Fig. 8A , the second substrate unit 200A is stacked on both sides of the second detachable carrier 430. In this case, if necessary, an insulating material 440 may be provided between the second detachable carrier 430 and the second substrate unit 200A. The insulating material 440 may include the same material as the plurality of stacked insulating layers 111 described above.

[0088] Reference Figure 8B , buildup insulating layer 111 is formed on second substrate unit 200A. Buildup insulating layer 111 may be formed by stacking insulating films in an uncured film state and curing them, or by applying a material for forming buildup insulating layer 111 and curing it.

[0089] Reference Figure 8C , a buildup wiring layer 121 and a buildup via layer 131 are formed on the buildup insulating layer 111. For example, after forming a via hole in the buildup insulating layer 111 by laser processing, the buildup wiring layer 121 and the buildup via layer 131 may be formed in a plating process using a semi-additive process (SAP), a modified SAP (MSAP), a hole sealing (TT) process, or the like.

[0090] Reference Fig.8D ,repeat Figure 8B and Figure 8C A process, for example, a build-up process is performed to form a first substrate unit 100A including a plurality of build-up insulating layers 111 , a plurality of build-up wiring layers 121 , and a plurality of build-up via layers 131 .

[0091] Reference Fig. 8E, the stacked body of the first substrate unit 100A and the second substrate unit 200A is separated from the second detachable carrier 430. When the insulating material 440 is separated, the insulating material 440 may be removed in a stripping process or the like.

[0092] Reference Figure 8F , the printed circuit board 300A according to the above-described embodiment may be manufactured by performing surface processing, electrical inspection, sawing, and the like.

[0093] Fig. 9 It is schematically shown Figure 6 sectional view of a modified example of the printed circuit board in FIG.

[0094] Reference Fig. 9 , the printed circuit board 300B according to the variant embodiment may be configured so that the second substrate unit 200B may include a plurality of interconnection regions R1 for die-to-die connection. In addition, the printed circuit board 300B may also include a first semiconductor chip 251, a second semiconductor chip 252, and a third semiconductor chip 253, which are mounted on the second substrate unit 200B through a plurality of first connection members 261, a plurality of second connection members 262, and a plurality of third connection members 263, respectively, and are electrically connected to each other through a plurality of interconnection regions R1 of the second substrate unit 200B. In addition, the printed circuit board 300B may also include a solder resist layer 271 stacked below the first substrate unit 100B. In addition, the printed circuit board 300B may also include a plurality of electrically connected metal bumps 281 respectively disposed on a plurality of openings h of the solder resist layer 271. For example, the printed circuit board 300A according to the above-described embodiment may be applied to a package board in a printed circuit board 300B according to a modified embodiment, and the printed circuit board 300B according to the modified embodiment may have a semiconductor package type structure.

[0095] The first semiconductor chip 251, the second semiconductor chip 252, and the third semiconductor chip 253 may each include an integrated circuit (IC) die, in which hundreds to millions of components are integrated into one chip. In this case, the integrated circuit may be, for example, a logic chip (such as a central processing unit (e.g., CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an application processor (AP), an analog-to-digital converter, an application-specific integrated circuit (ASIC)), etc., but the present disclosure is not limited thereto, and the integrated circuit may be a memory chip, such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM, flash memory), a high bandwidth memory (HBM), etc., or the integrated circuit may be other types, such as a power management integrated circuit (PMIC). For example, the first semiconductor chip 251 may include a logic chip (such as a GPU), and the second semiconductor chip 252 and the third semiconductor chip 253 may include a memory chip (such as an HBM, etc.).

[0096] Each of the first semiconductor chip 251, the second semiconductor chip 252 and the third semiconductor chip 253 can be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. can be used as the basic material for forming each body. Various circuits can be formed in the body. Connecting pads can be formed on each body, and the connecting pads may include conductive materials such as aluminum (Al) or copper (Cu). Each of the first semiconductor chip 251, the second semiconductor chip 252 and the third semiconductor chip 253 can be a bare die, in which case a metal bump can be arranged on the connecting pad. Each of the first semiconductor chip 251, the second semiconductor chip 252 and the third semiconductor chip 253 can be a packaged die, in which case a redistribution layer can be additionally formed on the connecting pad, and a metal bump can be arranged on the redistribution layer.

[0097] The first semiconductor chip 251, the second semiconductor chip 252 and the third semiconductor chip 253 can be mounted on the second substrate unit 200B by a plurality of first connection members 261, a plurality of second connection members 262 and a plurality of third connection members 263, respectively. Each of the plurality of first connection members 261, a plurality of second connection members 262 and a plurality of third connection members 263 can be formed using a low melting point metal (e.g., a solder such as tin (Sn)-aluminum (Al)-copper (Cu)), but this is only an example, and its material is not particularly limited thereto. Each of the plurality of first connection members 261, a plurality of second connection members 262 and a plurality of third connection members 263 can be a solder ball or the like. Each of the plurality of first connection members 261, a plurality of second connection members 262 and a plurality of third connection members 263 can be formed using a plurality of layers or a single layer. When the plurality of first connection members 261, the plurality of second connection members 262, and the plurality of third connection members 263 are formed using a plurality of layers, they may include copper pillars and solder, and when the plurality of first connection members 261, the plurality of second connection members 262, and the plurality of third connection members 263 are formed using a single layer, they may include tin-silver solder or copper, but the present disclosure is not limited thereto.

[0098] The solder resist layer 271 can protect the internal components of the circuit board 300B. The material of the solder resist layer 271 is not particularly limited. For example, an insulating material can be used, and in this case, a solder resist can be used as an insulating material. However, the present disclosure is not limited thereto, and ABF, etc. can be used. The solder resist layer 271 may have a plurality of openings h, and the plurality of openings h expose at least a portion of each of the stacked wiring layers 121 disposed on the lowermost side of the plurality of stacked wiring layers 121. A surface treatment layer can be formed on the pattern exposed by the plurality of openings h, and if necessary, an under-bump metal can be further formed.

[0099] A plurality of electrically connected metal bumps 281 are configured to connect the printed circuit board 300B to a main board or another board of an electronic device. A plurality of electrically connected metal bumps 281 may be connected to at least a portion of the lowest stacked wiring layer of the first substrate unit 100B. If necessary, a plurality of electrically connected metal bumps 281 may be provided by a plurality of under-bump metals, respectively. A plurality of electrically connected metal bumps 281 may be formed using a conductive material, such as solder, etc., but this is merely an example, and its material is not particularly limited thereto. Each of a plurality of electrically connected metal bumps 281 may be a ball, a pin, etc. Each of a plurality of electrically connected metal bumps 281 may be formed using a plurality of layers or a single layer. When a plurality of electrically connected metal bumps 281 are formed using a plurality of layers, they may include copper pillars and solder, and when a plurality of electrically connected metal bumps 281 are formed using a single layer, they may include tin-silver solder or copper, but the present disclosure is not limited thereto.

[0100] Other contents (eg, description of the configurations of the first substrate unit 100B and the second substrate unit 200B of the printed circuit board 300B according to the modified embodiment) are substantially the same as those described in the printed circuit board 300A according to the above embodiment, and therefore, redundant descriptions thereof will be omitted.

[0101] Fig.10 is a cross-sectional view schematically showing another example of a printed circuit board.

[0102] Reference Fig.10 According to another embodiment, a printed circuit board 300C may include a first substrate unit 100C and a second substrate unit 200C embedded in the first substrate unit 100C. The second substrate unit 200C may include only the interconnection region R1 in the second substrate unit 200A of the printed circuit board according to the above-described embodiment, and may have, for example, a shape of a bridge for die-to-die interconnection. The second substrate unit 200C may be configured so that its upper portion (e.g., the first outermost portion) may be exposed from the stacking insulation layer 111 disposed on the uppermost side among the plurality of stacking insulation layers 111 of the first substrate unit 100C, and the lower portion (e.g., the second outermost portion) and the side portion of the second substrate unit 200C may be embedded in the plurality of stacking insulation layers 111 to be covered by the plurality of stacking insulation layers 111 of the first substrate unit 100C. The first substrate unit 100A may surround the side portion and the lower portion of the second substrate unit 200C. For example, the first substrate unit 100C may include a wiring region R2 for die-to-substrate connection.

[0103] Other contents (for example, the description of the configuration of the first substrate unit 100C and the second substrate unit 200C of the printed circuit board 300C according to another embodiment) are substantially the same as those described in the printed circuit board 300A according to the above embodiment and the printed circuit board 300B according to the above variant embodiment, and therefore, redundant descriptions will be omitted.

[0104] FIG. 11A to FIG. 11G is a schematic diagram showing the manufacturing Fig.10 A process cross-sectional view of an example of a printed circuit board.

[0105] Reference Fig.11A , prepare a second detachable carrier 430.

[0106] Reference Fig. 11B , an insulating material 440 is formed on both sides of the second detachable carrier 430. If necessary, a barrier layer 441 (eg, a nickel (Ni) layer) may be formed on the insulating material 440.

[0107] Reference Fig. 11C , attaching the second substrate unit 200C to the barrier layer 441. 7A to 7JThe above-mentioned process is used to manufacture the second substrate unit 200C, and a sawing process may be added to manufacture the second substrate unit 200C in a bridge shape.

[0108] Reference Fig.11D , a buildup wiring layer 121 is formed on the barrier layer 441. For example, a buildup insulating layer 111 is formed on the barrier layer 441, and a buildup wiring layer 121 and a buildup via layer 131 are further formed on the buildup insulating layer 111. The buildup wiring layer 121 may be formed in a plating process using a semi-additive process (SAP), a modified SAP (MSAP), a hole sealing (TT) process, or the like. The buildup insulating layer 111 may be formed by stacking an insulating film in an uncured film state and curing it, or by coating a material for forming the buildup insulating layer 111 and curing it. The buildup wiring layer 121 and the buildup via layer 131 further formed on the buildup insulating layer 111 may be formed by forming a via hole in the buildup insulating layer 111 by laser processing, and then performing a plating process using a semi-additive process (SAP), an MSAP (modified SAP), a hole sealing (TT) process, or the like.

[0109] Reference Fig.11E ,repeat Fig.11D A process, for example, a build-up process is performed to form a first substrate unit 100C including a plurality of build-up insulating layers 111 , a plurality of build-up wiring layers 121 , and a plurality of build-up via layers 131 .

[0110] Reference Fig.11F , the stack of the first substrate unit 100C and the second substrate unit 200C is separated from the second detachable carrier 430. When the insulating material 440 and the barrier layer 441 are separated, the insulating material 440 may be removed in a stripping process, and the barrier layer 441 may be removed by an etching process.

[0111] Reference Fig.11G The printed circuit board 300C according to the above-described another embodiment may be manufactured by performing surface processing, electrical inspection, sawing, and the like.

[0112] Fig.12 It is schematically shown Fig.10 sectional view of a modified example of the printed circuit board in FIG.

[0113] Reference Fig.12, the printed circuit board 300D according to the variant embodiment may be configured so that a plurality of second substrate units 200D may be respectively embedded in a plurality of stacked insulating layers 111 of the first substrate unit 100D. In addition, the printed circuit board 300D may further include a first semiconductor chip 251, a second semiconductor chip 252, and a third semiconductor chip 253, which are respectively mounted on the second substrate unit 200D through a plurality of first connection members 261, a plurality of second connection members 262, and a plurality of third connection members 263, and are electrically connected to each other through the second substrate unit 200D. In addition, the printed circuit board 300D may further include a solder resist layer 271 stacked on the lower side of the first substrate unit 100D. In addition, the printed circuit board 300D may further include a plurality of electrically connected metal bumps 281 respectively disposed on a plurality of openings h of the solder resist layer 271. For example, the printed circuit board 300C according to the above-described other embodiment may be applied as a package board in the printed circuit board 300D according to the modified embodiment, and the printed circuit board 300D according to the modified embodiment may have a semiconductor package type structure.

[0114] Other contents (for example, the description of the configuration of the first substrate unit 100D and the second substrate unit 200D of the printed circuit board 300D according to the variant embodiment) are substantially the same as those described in the printed circuit board 300A according to the above embodiment, the printed circuit board 300B according to the above variant embodiment, and the printed circuit board 300C according to the above another example, and therefore, redundant descriptions thereof are omitted.

[0115] Fig.13 is a cross-sectional view schematically showing another example of a printed circuit board.

[0116] Reference Fig.13 , the printed circuit board 300E according to another example may be configured such that the second substrate unit 200E may further include a second insulating layer 213. For example, the second substrate unit 200E may include a glass layer 211, a first insulating layer 212 disposed above the glass layer 211, a second insulating layer 213 disposed below the glass layer 211, a first wiring layer 221 disposed between the glass layer 211 and the first insulating layer 212, a second wiring layer 222 disposed below the second insulating layer 213, a first via layer 231 penetrating both the glass layer 211 and the second insulating layer 213 and connecting the first wiring layer 221 and the second wiring layer 222, a third wiring layer 223 disposed above the first insulating layer 212, and a second via layer 232 penetrating the first insulating layer 212 and connecting the first wiring layer 221 and the third wiring layer 223.

[0117] In addition, the first via layer 231 may be deeper than the second via layer 232. For example, the first via layer 231 may penetrate both the glass layer 211 and the second insulating layer 213, but the second via layer 232 may penetrate only the first insulating layer 212, and thus, the depth of the via hole for forming the first via layer 231 may be deeper than the depth of the via hole for forming the second via layer 232. The first via layer 231 may be deeper than the second via layer 232.

[0118] In addition, the second insulating layer 213 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material including an inorganic filler, an organic filler and / or glass fiber (for example, a glass fabric such as glass cloth) and these resins. For example, the insulating material may be a non-photosensitive insulating material (such as Ajinomoto built-up film (ABF) or a prepreg (PPG)), but the present disclosure is not limited thereto, and other polymer materials may be used. In addition, the insulating material may be a photosensitive insulating material (such as a photosensitive dielectric (PID)). The second insulating layer 213 may include an insulating material that is the same as or different from the insulating material of the first insulating layer 212.

[0119] Other contents (for example, the description of the configuration of the first substrate unit 100E and the second substrate unit 200E of the printed circuit board 300E according to another embodiment) are substantially the same as those described in the printed circuit board 300A according to the above embodiment, the printed circuit board 300B according to the above variant embodiment, the printed circuit board 300C according to the above another example, and the printed circuit board 300D according to the above variant embodiment, and therefore, redundant descriptions thereof are omitted.

[0120] FIG. 14A to FIG. 14J is a schematic diagram showing the manufacturing Fig.13 A process cross-sectional view of an example of the second substrate unit in FIG.

[0121] Reference Fig.14A , prepare a first detachable carrier 410. The first detachable carrier 410 may, for example, have a multilayer structure including a core layer and copper foils stacked on both surfaces of the core layer. Next, the glass layer 211 is stacked on the first detachable carrier 410 using the second insulating layer 213 as an adhesive layer.

[0122] Reference Fig. 14B , a via hole v is processed in the glass layer 211 and the second insulating layer 213 using a drill. In this case, a copper foil may be used as a stopper.

[0123] Reference Fig. 14C, forming a seed layer m1. The seed layer m1 may cover the wall surface of the via hole v, the surface of the glass layer 211, and the exposed portion of the first detachable carrier 410. The seed layer m1 may be formed by electroless plating (eg, chemical copper plating). Alternatively, the seed layer m1 may be formed by sputtering.

[0124] Reference Fig.14D After the dry film 420 is formed, the dry film 420 is patterned in a photolithography process.

[0125] Reference Fig.14E , forming the plating layer m2. The plating layer m2 may be formed by electrolytic plating (eg, electrolytic copper plating).

[0126] Reference Fig.14F , removing the dry film 420. The dry film 420 may be removed using a stripping solution.

[0127] Reference Figure 14G The seed layer m1 formed in the region other than the region where the plating layer m2 is formed is removed by etching. Through a series of processes, the first wiring layer 221 and the first via layer 231 may be formed in the glass layer 211 and the second insulating layer 213 .

[0128] Reference Fig.14H , a first insulating layer 212 is formed on the glass layer 211, and a via hole processing process, a seed layer forming process, and a plating layer forming process are repeated to form a third wiring layer 223 and a second via layer 232. The first insulating layer 212 may be formed by stacking an insulating film in an uncured film state and curing it, or by coating and curing a material for forming the insulating layer 212. The via hole may be formed by laser processing.

[0129] Reference Fig.14I , the stacked body is separated from the first detachable carrier 410. In this case, the copper foil may be separated from the core layer, and the copper foil remaining on the stacked body after the core layer is separated may be removed by an appropriate method (eg, etching).

[0130] Reference Fig.14J , a second wiring layer 222 is formed on the lower surface of the second insulating layer 213. The second wiring layer 222 may be formed in a plating process using a semi-additive process (SAP), a modified SAP (MSAP), a via sealing (TT) process, etc. Then, a surface treatment may be performed as needed.

[0131] The second substrate unit 200E can be formed by a series of processes. In addition, in the process diagram, for the convenience of explanation, the shape of the pattern is more simply represented. In this way, in the process using the first detachable carrier 410, the first wiring layer 221, the second wiring layer 222 and the third wiring layer 223 and the first via layer 231 and the second via layer 232 can be directly formed on the glass layer 211 and the first insulating layer 212 and the second insulating layer 213, thereby having the above-mentioned technical effects.

[0132] FIG. 15A to FIG. 15F is a schematic diagram showing the manufacturing Fig.13 A process cross-section diagram of an example of a printed circuit board.

[0133] Reference Fig.15A , the second substrate unit 200E is stacked on both sides of the second detachable carrier 430. In this case, if necessary, the insulating material 440 may be provided between the second detachable carrier 430 and the second substrate unit 200E. The insulating material 440 may include the same material as the plurality of stacked insulating layers 111 described above.

[0134] Reference Fig. 15B , a buildup insulating layer 111 is formed on the second substrate unit 200E. The buildup insulating layer 111 may be formed by stacking an insulating film in an uncured film state and curing it, or by applying a material for forming the buildup insulating layer 111 and curing it.

[0135] Reference Fig. 15C , a buildup wiring layer 121 and a buildup via layer 131 are formed on the buildup insulating layer 111. For example, after forming a via hole in the buildup insulating layer 111 by laser processing, the buildup wiring layer 121 and the buildup via layer 131 may be formed in a plating process using a semi-additive process (SAP), a modified SAP (MSAP), a hole sealing (TT) process, or the like.

[0136] Reference Fig.15D ,repeat Fig. 15B and Fig. 15C A process, for example, a build-up process is performed to form a first substrate unit 100E including a plurality of build-up insulating layers 111 , a plurality of build-up wiring layers 121 , and a plurality of build-up via layers 131 .

[0137] Reference Fig.15E , the stacked body of the first substrate unit 100E and the second substrate unit 200E is separated from the second detachable carrier 430. When the insulating material 440 is separated, the insulating material 440 may be removed in a stripping process or the like.

[0138] Reference Fig.15FThe printed circuit board 300E according to the above-described another embodiment may be manufactured by performing surface processing, electrical inspection, sawing, and the like.

[0139] Fig.16 It is schematically shown Fig.13 sectional view of a modified example of the printed circuit board in FIG.

[0140] Reference Fig.16 , the printed circuit board 300F according to the variant embodiment may be configured so that the second substrate unit 200F may include a plurality of interconnection regions R1 for die-to-die connection. The printed circuit board 300F may also include a first semiconductor chip 251, a second semiconductor chip 252, and a third semiconductor chip 253, which are mounted on the second substrate unit 200F through a plurality of first connection members 261, a plurality of second connection members 262, and a plurality of third connection members 263, respectively, and are electrically connected to each other through a plurality of interconnection regions R1 of the second substrate unit 200F. In addition, the printed circuit board 300F may also include a solder resist layer 271 stacked under the first substrate unit 100F. In addition, the printed circuit board 300F may also include a plurality of electrically connected metal bumps 281 respectively disposed on a plurality of openings h of the solder resist layer 271. For example, the printed circuit board 300E according to the above-described other embodiment may be applied as a package board in the printed circuit board 300F according to the modified embodiment, and the printed circuit board 300F according to the modified embodiment may have a semiconductor package type structure.

[0141] Other contents (for example, the description of the configuration of the first substrate unit 100F and the second substrate unit 200F of the printed circuit board 300F according to the variant embodiment) are substantially the same as those described in the printed circuit board 300A according to the above embodiment, the printed circuit board 300B according to the above variant embodiment, the printed circuit board 300C according to the above another example, the printed circuit board 300D according to the above variant embodiment, and the circuit board 300E according to the above another embodiment, and therefore, redundant descriptions thereof will be omitted.

[0142] Fig.17 is a cross-sectional view schematically showing another example of a printed circuit board.

[0143] Reference Fig.17, the printed circuit board 300G according to another embodiment may be configured such that the second substrate unit 200G may further include a second insulating layer 213. For example, the second substrate unit 200G may include a glass layer 211, a first insulating layer 212 disposed above the glass layer 211, a second insulating layer 213 disposed below the glass layer 211, a first wiring layer 221 disposed between the glass layer 211 and the first insulating layer 212, a second wiring layer 222 disposed below the second insulating layer 213, a first via layer 231 penetrating both the glass layer 211 and the second insulating layer 213 and connecting the first wiring layer 221 and the second wiring layer 222, a third wiring layer 223 disposed above the first insulating layer 212, and a second via layer 232 penetrating the first insulating layer 212 and connecting the first wiring layer 221 and the third wiring layer 223.

[0144] Other contents (for example, the description of the configuration of the first substrate unit 100G and the second substrate unit 200G of the printed circuit board 300G according to another embodiment) are substantially the same as those described in the printed circuit board 300A according to the above embodiment, the printed circuit board 300B according to the above variant embodiment, the printed circuit board 300C according to the above another example, the printed circuit board 300D according to the above variant embodiment, the printed circuit board 300E according to the above another embodiment, and the printed circuit board 300F according to the above variant embodiment, and therefore, overlapping descriptions thereof are omitted.

[0145] FIG. 18A to FIG. 18G is a schematic diagram showing the manufacturing Fig.17 A process cross-section diagram of an example of a printed circuit board.

[0146] Reference Fig.18A , prepare a second detachable carrier 430.

[0147] Reference Fig.18B , an insulating material 440 is formed on both sides of the second detachable carrier 430. If necessary, a barrier layer 441, such as a nickel (Ni) layer, may be formed on the insulating material 440.

[0148] Reference Fig.18C , the second substrate unit 200G is attached to the barrier layer 441. FIG. 14A to FIG. 14J The second substrate unit 200G is manufactured by the above-mentioned process. A sawing process may be added to manufacture the second substrate unit 200G in a bridge shape.

[0149] Reference Fig.18D, a buildup wiring layer 121 is formed on the barrier layer 441. For example, a buildup insulating layer 111 is formed on the barrier layer 441, and a buildup wiring layer 121 and a buildup via layer 131 are further formed on the buildup insulating layer 111. The buildup wiring layer 121 may be formed in a plating process using a semi-additive process (SAP), a modified SAP (MSAP), a hole sealing (TT) process, or the like. The buildup insulating layer 111 may be formed by stacking an insulating film in an uncured film state and curing it, or by coating a material for forming the buildup insulating layer 111 and curing it. The buildup wiring layer 121 and the buildup via layer 131 further formed on the buildup insulating layer 111 may be formed by forming a via hole in the buildup insulating layer 111 via laser processing and then performing a plating process using a semi-additive process (SAP), a modified SAP (MSAP), a hole sealing (TT) process, or the like.

[0150] Reference Fig.18E ,repeat Fig.18D A process, for example, a build-up process is performed to form a first substrate unit 100G including a plurality of build-up insulating layers 111 , a plurality of build-up wiring layers 121 , and a plurality of build-up via layers 131 .

[0151] Reference Fig.18F , the stacked body of the first substrate unit 100G and the second substrate unit 200G is separated from the second detachable carrier 430. When the insulating material 440 and the barrier layer 441 are separated, the insulating material 440 may be removed in a stripping process, and the barrier layer 441 may be removed in an etching process.

[0152] Reference Figure 18G , surface processing, electrical inspection, sawing, etc. may be performed to manufacture the printed circuit board 300G according to the above-mentioned another embodiment.

[0153] Fig.19 It is schematically shown Fig.17 sectional view of a modified example of the printed circuit board in FIG.

[0154] Reference Fig.19, the printed circuit board 300H according to the variant embodiment may be configured so that a plurality of second substrate units 200H may be respectively embedded in a plurality of stacked insulating layers 111 of the first substrate unit 100H. The printed circuit board 300H may also include a first semiconductor chip 251, a second semiconductor chip 252, and a third semiconductor chip 253, which are mounted on the second substrate unit 200H through a plurality of first connection members 261, a plurality of second connection members 262, and a plurality of third connection members 263, respectively, and are electrically connected to each other through the second substrate unit 200H. In addition, the printed circuit board 300H may also include a solder resist layer 271 stacked under the first substrate unit 100H. In addition, the printed circuit board 300H may also include a plurality of electrically connected metal bumps 281 respectively disposed on a plurality of openings h of the solder resist layer 271. For example, the printed circuit board 300G according to the above-described other embodiment may be applied as a package board in the printed circuit board 300H according to the modified embodiment, and the printed circuit board 300H according to the modified embodiment may have a semiconductor package type structure.

[0155] Other contents (for example, the description of the configuration of the first substrate unit 100H and the second substrate unit 200H of the printed circuit board 300H according to the variant embodiment) are substantially the same as those described in the printed circuit board 300A according to the above embodiment, the printed circuit board 300B according to the above variant embodiment, the printed circuit board 300C according to the above another example, the printed circuit board 300D according to the above variant embodiment, the printed circuit board 300E according to the above another embodiment, the printed circuit board 300F according to the above variant embodiment, and the printed circuit board 300G according to the above another embodiment, and therefore, redundant descriptions thereof are omitted.

[0156] In the present disclosure, the thickness, width, length, pitch, spacing and depth can be measured respectively with a scanning microscope or an optical microscope based on a cross section obtained by polishing or cutting a printed circuit board. The cut section can be a vertical section or a horizontal section, and each value can be measured based on the desired cut section. If the value is not constant, the value can be determined as the average value of the values ​​measured at any of the five points. The width of the upper and / or lower ends of the via can be measured on a cross section cut along the central axis of the via in the thickness direction of the board. The depth of the via can be measured as the distance from the upper end to the lower end of the via on a cross section cut along the central axis of the via in the thickness direction of the board. Even if not described in the present disclosure, other methods and / or tools understood by a person of ordinary skill in the art can also be used.

[0157] In the present disclosure, the expression "covering" may include the case of covering at least a part as well as the case of covering the entire part, and may include not only the case of direct covering but also the case of indirect covering. In addition, the expression "filling" may include not only the case of complete filling but also the case of partial filling, for example, may include the case of the presence of some holes or gaps.

[0158] In the present disclosure, "substantially" may be determined by including process errors or positional deviations occurring in the manufacturing process and errors during measurement. For example, the expression "substantially vertical" may include not only a completely vertical situation but also a nearly vertical situation. Furthermore, substantially coplanar may include not only a situation where components exist on exactly the same plane but also a situation where components exist on approximately the same plane.

[0159] In the present disclosure, the same insulating material may have a meaning including the case of the same type of insulating material as well as completely identical insulating materials. Therefore, the components of the insulating materials are substantially the same as each other, but their specific component ratios may be slightly different from each other.

[0160] In the present disclosure, the meaning of a cross-sectional view or a cross section may refer to the cross-sectional shape of an object when the object is cut vertically, or the cross-sectional shape of an object when the object is viewed from the side. In addition, the meaning of a plan view may refer to the plane shape of an object when the object is cut horizontally, or the plane shape of an object when the object is viewed from the top or bottom.

[0161] In the present disclosure, the lower side, the lower part, and the lower surface are used to refer to the downward direction relative to the cross section of the drawings, and the upper side, the upper part, and the upper surface are used to refer to the opposite direction. However, for the convenience of explanation, the directions are defined here, and the scope of the rights of the claims is not particularly limited by the description of such directions, and the concepts of the upper part and the lower part can be changed at any time.

[0162] In the present disclosure, the meaning of connection includes not only direct connection but also indirect connection through an adhesive layer or the like. In addition, the meaning of electrical connection includes concepts of physical connection and non-connection. In addition, expressions such as first and second are used to distinguish one component from another component and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the rights, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component.

[0163] The expression "the example embodiments used in the present disclosure" does not mean the same embodiment, and is provided for explaining different unique features. However, the example embodiments presented above do not exclude being implemented in combination with features of other example embodiments. For example, even if the contents described in a specific example embodiment are not described in other example embodiments, they can be understood as explanations related to other example embodiments unless there is an explanation contrary to or contradictory to the contents in other example embodiments.

[0164] The terms used in the present disclosure are only used to describe example embodiments and are not intended to limit the present disclosure. In this case, unless clearly indicated differently in the context, a singular expression includes a plural expression.

Claims

1. A printed circuit board, comprising: A first substrate unit including a plurality of buildup insulating layers and a plurality of buildup wiring layers respectively disposed on or in the plurality of buildup insulating layers, each of the plurality of buildup wiring layers including a circuit; and a second substrate unit including a glass layer, a first wiring layer and a second wiring layer respectively provided on a first surface and a second surface of the glass layer, an insulating layer provided on the glass layer, and a third wiring layer provided on the insulating layer, each of the first wiring layer, the second wiring layer and the third wiring layer including a circuit, wherein the second substrate unit is stacked on the first substrate unit or embedded in the first substrate unit, wherein the first surface of the glass layer is opposite to the second surface of the glass layer, and wherein an average pitch of the circuits in each of the first wiring layer, the second wiring layer, and the third wiring layer is smaller than an average pitch of the circuits in each of the plurality of build-up wiring layers.

2. The printed circuit board according to claim 1, wherein: An average spacing between adjacent layers among the first wiring layer, the second wiring layer, and the third wiring layer is smaller than an average spacing between adjacent layers among the plurality of buildup wiring layers.

3. The printed circuit board according to claim 2, wherein: The thickness of each of the glass layer and the insulating layer is thinner than the thickness of each of the plurality of buildup insulating layers.

4. The printed circuit board according to claim 1, wherein: The first substrate unit further includes a plurality of stacked via layers, at least one of the plurality of stacked via layers penetrates at least one of the plurality of stacked insulating layers, The second substrate unit further includes a first via layer penetrating the glass layer and connecting the first wiring layer and the second wiring layer, and a second via layer penetrating the insulating layer and connecting the first wiring layer and the third wiring layer. In a cross-sectional view of the printed circuit board, each of the first via layer and the second via layer tapers in a direction opposite to a taper direction of the plurality of stacked via layers, and Each of the plurality of stacked via layers, the first via layer, and the second via layer includes a plurality of vias.

5. The printed circuit board according to claim 4, wherein: At least one via among the multiple vias in the first via layer, the second via layer, and each of the multiple stacked via layers has a first end and a second end opposite to the first end, and in a cross-sectional view of the printed circuit board, the width of the first end is wider than the width of the second end, and the width of the first end of the at least one via in each of the first via layer and the second via layer is narrower than the width of the first end of the at least one via in each of the multiple stacked via layers.

6. The printed circuit board according to claim 4, wherein: An average spacing between adjacent vias in the plurality of vias in each of the first and second via layers is smaller than an average spacing between adjacent vias in the plurality of vias in each of the plurality of build-up wiring layers.

7. The printed circuit board according to claim 4, wherein: The first wiring layer, the second wiring layer, and the first via layer are in direct contact with the glass layer.

8. The printed circuit board according to claim 1, wherein: The glass layer includes flat glass.

9. The printed circuit board according to claim 8, wherein: The insulating layer and each of the plurality of build-up insulating layers include an Ajinomoto build-up film, a prepreg, or a photosensitive medium.

10. The printed circuit board according to claim 1, further comprising: A first semiconductor chip and a second semiconductor chip are provided on the second substrate unit and are interconnected with each other through the first wiring layer, the second wiring layer, and the third wiring layer.

11. The printed circuit board according to claim 1, wherein: The second substrate unit is stacked on an outermost buildup insulating layer among the plurality of buildup insulating layers to completely cover the outermost buildup insulating layer.

12. The printed circuit board according to claim 1, wherein: The second substrate unit is embedded in the first substrate unit, and a first outermost portion of the second substrate unit is exposed from an outermost surface of an outermost stacked insulation layer among the multiple stacked insulation layers, and a side portion and a second outermost portion of the second substrate unit are embedded in the multiple stacked insulation layers to be covered by the multiple stacked insulation layers, wherein the first outermost portion and the second outermost portion are opposite to each other.

13. The printed circuit board according to claim 12, wherein: The printed circuit board includes a plurality of the second substrate units embedded in the plurality of build-up insulating layers.

14. A printed circuit board, comprising: A first substrate unit includes a plurality of buildup insulating layers and a plurality of buildup wiring layers respectively disposed on or in the plurality of buildup insulating layers; as well as a second substrate unit including a glass layer, a first wiring layer and a second wiring layer respectively disposed on a first surface and a second surface of the glass layer, an insulating layer disposed on the first surface of the glass layer, and a third wiring layer disposed on a surface of the insulating layer, wherein the first surface of the glass layer is opposite to the second surface of the glass layer, wherein the second substrate unit is stacked on the first substrate unit or embedded in the first substrate unit, and Wherein, the total thickness of the plurality of stacked insulating layers is thicker than the thickness of the insulating layer.

15. The printed circuit board according to claim 14, wherein: The plurality of buildup insulating layers have more layers than the insulating layer.

16. The printed circuit board according to claim 14, wherein: Each of the plurality of build-up wiring layers includes a circuit, and each of the first wiring layer, the second wiring layer, and the third wiring layer includes a circuit having a higher density than that of the circuit in each of the plurality of build-up wiring layers.

17. The printed circuit board according to claim 14, wherein: The second substrate unit is stacked on the first substrate unit.

18. The printed circuit board according to claim 14, wherein: The second substrate unit is embedded in the first substrate unit.

19. A printed circuit board comprising: Glass layer; A first insulating layer, disposed on a first surface of the glass layer; a second insulating layer, disposed on a second surface of the glass layer, wherein the second surface of the glass layer is opposite to the first surface of the glass layer; a first wiring layer, disposed between the glass layer and the first insulating layer; A second wiring layer is provided on the second insulating layer; and The first via layer penetrates both the glass layer and the second insulating layer and connects the first wiring layer and the second wiring layer.

20. The printed circuit board according to claim 19, further comprising: A third wiring layer is provided on the first insulating layer; as well as a second via layer penetrating the first insulating layer and connecting the first wiring layer and the third wiring layer, Wherein, the first via layer is deeper than the second via layer.

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