Terminal structure of fast recovery diode device and manufacturing method thereof

Abstract

The invention discloses a terminal structure of a fast recovery diode device and a manufacturing method of the terminal structure, and particularly relates to the technical field of power semiconductor devices.The terminal structure comprises an N-type substrate and an N-epitaxial layer formed on an N + substrate layer, a plurality of stepped deep grooves which are formed through etching and are wide in upper portion and narrow in lower portion are formed in a field limiting ring of an N-epitaxial layer terminal area, the deep trench is formed by one-time photoetching, a P type is injected into the bottom of the deep trench to form a terminal ring, and a dielectric layer is filled in the deep trench, or an oxide layer grows in the deep trench and the dielectric layer is filled on the oxide layer. A deep groove structure is arranged in the terminal area, more peak electric fields are introduced to relieve the electric field concentration effect at the edge of a terminal ring P / N junction, the P / N reverse breakdown characteristic is improved, therefore, reverse blocking voltage is improved, reverse leakage current is improved, meanwhile, the deep groove adopted in the terminal area can reduce a bulk electric field and a surface electric field, terminal withstand voltage of a device is improved, and the performance of the device is improved. The application scenarios of the device are increased, and the reliability of the device is enhanced.

Description

Technical Field

[0001] The invention relates to the technical field of fast recovery diode devices, and in particular to a terminal structure of a fast recovery diode device and a manufacturing method thereof. Background Art

[0002] Power Fast Recovery Diode (FRD) is a semiconductor device with a short reverse recovery time. It can quickly shut down when the current direction is reversed, reducing power loss and electromagnetic interference in the circuit. With the development of science and technology, power fast recovery diode devices have been widely used in many fields. Power FRD devices play a key role in energy conversion and power electronic equipment, and have become indispensable devices in life and industry.

[0003] In the design of semiconductor power FRD devices, the active area often determines the main characteristics of the device, such as forward resistance, withstand voltage, switching speed, etc., but the active area has always been limited by the design of the terminal area, such as area. The existing design of the terminal area of ​​power devices is usually based on structures such as field limiting rings (FLR) and junction terminal extensions (JTE). Fig. 20 The figure shows the device structure of the current general fast recovery diode terminal FLR. The basic structure from bottom to top is: substrate / epitaxial / main junction + terminal region / oxide layer / metal layer; Fig.21 The figure shows the device structure of the current common fast recovery diode terminal JTE. The basic structure from bottom to top is: substrate / epitaxial / main junction+terminal region.

[0004] Among them, field limiting rings are more commonly used but occupy more area, which will reduce the area of ​​the active area and affect the forward resistance of the device. Although the junction termination extension (JTE) has a smaller area, its manufacturing process is complex, the manufacturing cost is high, and the leakage current of the device is large. Summary of the invention

[0005] The purpose of the present invention is to provide a terminal structure of a fast recovery diode device and a manufacturing method thereof. The present invention sets a deep trench structure in the terminal area, introduces more peak electric fields to alleviate the electric field concentration effect at the edge of the terminal ring P / N junction, improves the P / N reverse breakdown characteristics, thereby increasing the reverse blocking voltage and improving the reverse leakage current. At the same time, the deep trench used in the terminal area can reduce the body electric field and the surface electric field, improve the terminal withstand voltage of the device, increase the application scenarios of the device and enhance the reliability of the device.

[0006] In order to achieve the above object, the present invention provides the following technical solutions: a terminal structure of a fast recovery diode device, comprising an N-type substrate, wherein the N-type substrate comprises an N+ substrate layer and an N- epitaxial layer formed on the N+ substrate layer; A plurality of deep trenches with a stepped shape and a width at the top and a narrowness at the bottom are formed by etching in the field limiting ring of the terminal region of the N-epitaxial layer, and the deep trenches are formed by photolithography at one time; The first terminal structure is to inject P-type into the bottom of the deep trench to form a terminal ring and fill the deep trench with a dielectric layer; The second terminal structure is to grow an oxide layer in the deep trench and fill a dielectric layer on the oxide layer.

[0007] Preferably, the deep groove includes a first layer of grooves, a second layer of grooves and a third layer of grooves, the width of the second layer of grooves is smaller than the width of the first layer of grooves, and the width of the third layer of grooves is smaller than the width of the second layer of grooves, so that the deep groove is wide at the top and narrow at the bottom.

[0008] Preferably, the N-epitaxial layer is also provided with a P-type implanted main junction anode region and a deep N-well implanted termination ring, the back N+ substrate layer forms the cathode of the main junction, and a passivation layer is deposited on the top layer.

[0009] Preferably, the conductivity types of the N-epitaxial layer and the termination ring are both N-type, and the conductivity types of the main junction anode region and the field limiting ring are both P-type; the conductivity type of the main junction anode region is opposite to the conductivity type of the N-epitaxial layer, and is used to form an active region; the conductivity type of the field limiting ring is opposite to the conductivity type of the N-epitaxial layer, and is used to form a terminal region; the P-type field limiting ring forms a P / N junction with the N-epitaxial layer.

[0010] Preferably, the P-type concentration injected into the main junction anode region is less than the P-type concentration injected into the terminal ring.

[0011] The specific steps of the manufacturing method of the first terminal structure are as follows: S1. A silicon oxide layer is grown on the surface of a selected N-type substrate silicon wafer, and a terminal region is defined by photolithography and etching, and the silicon oxide layer in the terminal region is etched; S2. Then, the substrate under the silicon oxide layer in the terminal region is etched, and the first layer of groove morphology perpendicular to the substrate surface is etched using anisotropic etching; S3. By depositing a silicon oxide layer and etching back, a silicon oxide sidewall is formed at the edge of the first layer trench sidewall for isolation in subsequent etching; S4. Continue etching the substrate to form a second layer of trench morphology. The width of the second layer of trench is smaller than the width of the first layer of trench due to the obstruction of the silicon oxide sidewall of the first layer of trench; S5. Continue to deposit the silicon oxide layer and etch back, and continue to form silicon oxide sidewalls at the edges of the first trench and the second trench for isolation in subsequent etching; S6. Continue etching the substrate to form a third-layer trench morphology. Due to the obstruction of the silicon oxide sidewalls of the first and second trenches, the width of the third-layer trench is smaller than the width of the second-layer trench. The first, second and third-layer trenches form a deep trench with a stepped shape that is wide at the top and narrow at the bottom. S7. remove the silicon oxide layer, and by photolithography, inject P-type into the deep trench to form a terminal ring, and inject P-type into the main junction to form a main junction anode region, wherein the concentration of P-type injected into the main junction anode region is less than the concentration of P-type injected into the terminal ring; S8. By photolithography, a deep N well is defined on the N-epitaxial layer to form a termination ring for the deep N well injection; S9. High temperature advancement after injection; S10. Depositing a dielectric layer and densifying the dielectric layer, and then defining the active area of ​​the device by photolithography; S11. Depositing a passivation layer of silicon nitride and polyimide, and photolithographically etching the passivation layer to complete the production of the top structure; S12. Thinning the back side of the silicon wafer to a specific thickness, injecting N-type impurities into the back side, forming a field stop layer by low temperature annealing or laser annealing, and ensuring that the surface impurity concentration is high enough to form an ohmic contact; S13. Deposit the back metal by sputtering or evaporation, and finally perform minority carrier lifetime control process to improve the reverse recovery characteristics of the device.

[0012] The specific steps of the manufacturing method of the second terminal structure are as follows: S1. A silicon oxide layer is grown on the surface of a selected N-type substrate silicon wafer, and a terminal region is defined by photolithography and etching, and the silicon oxide layer in the terminal region is etched; S2. Then, the substrate under the silicon oxide layer in the terminal region is etched, and the first layer of groove morphology perpendicular to the substrate surface is etched using anisotropic etching; S3. By depositing a silicon oxide layer and etching back, a silicon oxide sidewall is formed at the edge of the first layer trench sidewall for isolation in subsequent etching; S4. Continue etching the substrate to form a second layer of trench morphology. The width of the second layer of trench is smaller than the width of the first layer of trench due to the obstruction of the silicon oxide sidewall of the first layer of trench; S5. Continue to deposit the silicon oxide layer and etch back, and continue to form silicon oxide sidewalls at the edges of the first trench and the second trench for isolation in subsequent etching; S6. Continue etching the substrate to form a third-layer trench morphology. Due to the obstruction of the silicon oxide sidewalls of the first-layer trench and the second-layer trench, the width of the third-layer trench will be smaller than the width of the second-layer trench. The first-layer trench, the second-layer trench and the third-layer trench form a stepped deep trench that is wide at the top and narrow at the bottom. The number of steps, depth and width of the deep trench can be controlled by adjusting process parameters according to the performance requirements of the device; S7. Remove the silicon oxide layer, and define a deep N-well on the N-epitaxial layer by photolithography to form a termination ring for the deep N-well injection; S8. Deposit an oxide layer in the deep trench and perform photolithography on the oxide layer. The thickness of the oxide layer must be able to withstand the voltage applied by the back cathode, so the thickness and quality of the oxide layer must be strictly controlled during growth; S9. After the oxide layer is grown, the anode region is defined by photolithography and etching of the oxide layer and a P-type is injected to form a main junction anode region; S10. High temperature advancement after injection; S11. Filling a dielectric layer on the oxide layer in the deep trench as a suspended field plate, and filling the entire inner surface of the deep trench with polysilicon dielectric; S12. Depositing a passivation layer of silicon nitride and polyimide, and photolithographically etching the passivation layer to complete the production of the top structure; S13. Thinning the back side of the silicon wafer to a specific thickness, injecting N-type impurities into the back side, forming a field stop layer by low temperature annealing or laser annealing, and ensuring that the surface impurity concentration is high enough to form an ohmic contact; S14. Deposit the back metal by sputtering or evaporation, and finally perform minority carrier lifetime control process to improve the reverse recovery characteristics of the device.

[0013] In the above technical solution, the technical effects and advantages provided by the present invention are: The terminal structure of the fast recovery diode of the present invention is different from the traditional planar ring terminal structure and the trench Schottky barrier diode. The present invention sets a stepped deep trench structure in the terminal area, injects a P-type Pring at the bottom of the deep trench to form a P / N junction with the N-type epitaxial layer, and can also grow an oxide layer in the deep trench, and fill a dielectric layer to replace the P+ injection of the Pring; through the innovation of the device structure, compared with the traditional terminal structure, adding a deep trench in the terminal area can introduce more peak electric fields to alleviate the electric field concentration effect at the edge of the terminal ring P / N junction, improve the P / N reverse breakdown characteristics, thereby improving the reverse blocking voltage and improving the reverse leakage current. At the same time, the deep trench used in the terminal area can reduce the body electric field and the surface electric field, improve the terminal withstand voltage of the device, increase the application scenarios of the device and enhance the reliability of the device; The device structure of the present invention is simple, and by proposing a deep trench terminal field limiting ring structure, the reverse bias performance is improved under the same chip area (increasing the reverse breakdown voltage and reducing the reverse leakage current, etc.); The deep groove of the present invention only needs one photolithography and then the oxide layer self-aligned etching process to be processed and formed, so that the process cost and time cost of the device can be greatly reduced, and the number of groove layers can be flexibly adjusted according to the voltage resistance requirements by only controlling the size of the groove opening and the etching depth. The manufacturing process of the present invention is fully compatible with the existing general power device FRD process, the process is simple, and the process controllability is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a terminal structure diagram of the first fast recovery diode device of the present invention; Figure 2 It is a terminal structure diagram of the second fast recovery diode device of the present invention; Figure 3 The manufacturing process of the first and second terminal structures of the present invention Figure 1 ; Figure 4 The manufacturing process of the first and second terminal structures of the present invention Figure 2 ; Figure 5 The manufacturing process of the first and second terminal structures of the present invention Figure 3 ; Figure 6 The manufacturing process of the first and second terminal structures of the present invention Figure 4 ; Figure 7 The manufacturing process of the first and second terminal structures of the present invention Figure 5 ; Figure 8 The manufacturing process of the first and second terminal structures of the present invention Figure 6 ; Fig. 9 The manufacturing process of the first terminal structure of the present invention is Figure 7 ; Fig.10 The manufacturing process of the first terminal structure of the present invention is Figure 8 ; Fig.11 The manufacturing process of the first terminal structure of the present invention is Figure 9 ; Fig.12 The manufacturing process of the first terminal structure of the present invention is Figure 10 ; Fig.13 The manufacturing process of the first terminal structure of the present invention is Figure 10 one; Fig.14 The manufacturing process of the first terminal structure of the present invention is Figure 10 two; Fig.15The manufacturing process of the second terminal structure of the present invention is Figure 7 ; Fig.16 The manufacturing process of the second terminal structure of the present invention is Figure 8 ; Fig.17 The manufacturing process of the second terminal structure of the present invention is Figure 9 ; Fig.18 The manufacturing process of the second terminal structure of the present invention is Figure 10 ; Fig.19 The manufacturing process of the second terminal structure of the present invention is Figure 10 one; Fig. 20 The device structure diagram of the current general fast recovery diode terminal FLR; Fig.21 This is a device structure diagram of the current common fast recovery diode terminal JTE.

[0015] Description of reference numerals: 10. N-type substrate; 11. N+ substrate layer; 12. N- epitaxial layer; 20. Main junction anode region; 30. Termination ring; 40. Passivation layer; 50, deep groove; 51, first layer groove; 52, second layer groove; 53, third layer groove; 60. terminal ring; 70. dielectric layer; 80. oxide layer. DETAILED DESCRIPTION

[0016] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0017] Embodiment 1 like Figure 1 The terminal structure of a fast recovery diode device shown includes an N-type substrate 10, wherein the N-type substrate 10 includes an N+ substrate layer 11 and an N- epitaxial layer 12 formed on the N+ substrate layer 11, and the conductivity type of the N- epitaxial layer 12 is N-type; The N-epitaxial layer 12 is provided with a P-type implanted main junction anode region 20, a P-type implanted field limiting ring and a deep N-well implanted termination ring 30 in sequence, the main junction anode region 20 and the field limiting ring are both P-type in conductivity, and the P-type concentration implanted in the main junction anode region 20 is less than the P-type concentration implanted in the termination ring 60; The conductivity type of the main junction anode region 20 is opposite to that of the N-epitaxial layer 12 and is used to form an active region. The conductivity type of the field limiting ring is opposite to that of the N-epitaxial layer 12 and is used to form a terminal region. The P-type field limiting ring forms a P / N junction with the N-epitaxial layer 12. The conductivity type of the termination ring 30 is N-type. The back N+ substrate layer 11 forms the cathode of the main junction, and a passivation layer 40 is deposited on the top layer of the device; A plurality of deep grooves 50 formed by etching are arranged in the field limiting ring of the terminal region of the N-epitaxial layer 12, and the deep grooves 50 are formed by one-time photolithography, and the deep grooves 50 include a first layer of grooves 51, a second layer of grooves 52 and a third layer of grooves 53, the width of the second layer of grooves 52 is smaller than the width of the first layer of grooves 51, and the width of the third layer of grooves 53 is smaller than the width of the second layer of grooves 52, so that the deep grooves 50 form a stepped shape with a wide top and a narrow bottom; A P-type is implanted at the bottom of the deep trench 50 to form a terminal ring 60 and a dielectric layer 70 is filled in the deep trench 50 .

[0018] The manufacturing method of the terminal structure of the fast recovery diode device in the first embodiment is: the active area and the terminal area are defined by photolithography on the surface of the epitaxial silicon substrate, a plurality of deep trenches 50 in a stepped shape are formed by etching in the terminal area, P+ is injected into the deep trenches 50 to form a terminal ring 60 and a dielectric layer 70 is filled, and the specific steps are as follows: S1. A silicon oxide layer with a thickness of about 1 μm is grown on the surface of the selected N-type substrate 10 silicon wafer, and a terminal region is defined by photolithography and etching. The silicon oxide layer in the terminal region is etched, such as Figure 3 As shown; S2. Then, the substrate under the silicon oxide layer in the terminal region is etched, and the first layer of grooves 51 perpendicular to the substrate surface are etched using anisotropic etching, such as Figure 4 As shown; S3. By depositing a silicon oxide layer and etching back, a silicon oxide sidewall is formed at the edge of the sidewall of the first layer trench 51 for isolation in subsequent etching, such as Figure 5 As shown; S4. Continue etching the substrate to form a second layer of grooves 52, such as Figure 6 As shown, the width of the second layer trench 52 is smaller than the width of the first layer trench 51 due to the obstruction of the silicon oxide sidewall of the first layer trench 51; S5. Continue to deposit the silicon oxide layer and etch back, and continue to form silicon oxide sidewalls at the edges of the first layer trench 51 and the second layer trench 52 for isolation in subsequent etching, such as Figure 7 As shown; S6. Continue etching the substrate to form a third layer of grooves 53, such as Figure 8As shown, the width of the third layer trench 53 is smaller than the width of the second layer trench 52 due to the obstruction of the silicon oxide sidewalls of the first layer trench 51 and the second layer trench 52, and the first layer trench 51, the second layer trench 52 and the third layer trench 53 form a stepped deep trench 50 which is wide at the top and narrow at the bottom; The present invention is not limited to the three-layer groove structure listed in the first embodiment. Continuing deposition and etching can form a multi-layer groove morphology. The depth and width of the deep groove can be specifically determined according to parameters such as doping concentration and withstand voltage requirements. Generally speaking, the deeper the deep groove and the larger the width of the deep groove, the better the withstand voltage effect. S7. Remove the silicon oxide layer, and implant P-type into the deep trench 50 to form a terminal ring 60 by photolithography. Fig. 9 , Fig.12 As shown, a P-type is injected into the main junction to form a main junction anode region 20, as shown in FIG. Fig.10 , Fig.12 As shown, the P-type concentration injected into the main junction anode region 20 is less than the P-type concentration injected into the terminal ring 60; S8. By photolithography, a deep N well is defined on the N-epitaxial layer 12 to form a termination ring 30 for deep N well implantation, such as Fig.11 , Fig.12 As shown; S9. High temperature advancement after injection; S10. Deposit a dielectric layer 70 and densify the dielectric layer 70, and then define the active area of ​​the device by photolithography, such as Fig.13 As shown, the dielectric layer 70 can effectively prevent the humidity and impurities in the external environment from affecting the reverse leakage current of the high-voltage device, and play a role in withstanding voltage and reducing leakage; S11. Deposit a passivation layer 40 of silicon nitride and polyimide, and etch the passivation layer 40 by photolithography to complete the production of the top structure, such as Fig.14 As shown; S12. Thinning the back side of the silicon wafer to a specific thickness, injecting N-type impurities into the back side, forming a field stop layer by low temperature annealing or laser annealing, and ensuring that the surface impurity concentration is high enough to form an ohmic contact. When a substrate with a deep back diffusion layer is selected, the back side impurity injection and annealing process may not be performed; S13. Deposit the back metal by sputtering or evaporation, and finally perform minority carrier lifetime control process to improve the reverse recovery characteristics of the device.

[0019] This embodiment proposes a terminal design scheme of a stepped deep trench 50 on the basis of a traditional planar ring terminal structure. Different from the current trench Schottky barrier diode in which a trench is set in the active area, the present invention sets a stepped deep trench 50 structure in the terminal area, and the deep trench 50 is formed by one-time photolithography, which saves process costs. P-type Pring is injected into the bottom of the deep trench 50 to form a P / N junction with the N-type epitaxial layer. The electric field distribution is adjusted through the deep trench 50 to alleviate the electric field concentration at the edge of the field limiting ring, thereby improving the reverse breakdown characteristics of the device. Compared with a shallower junction, the deep trench 50 can reduce both the body electric field and the surface electric field, thereby improving the terminal withstand voltage of the device, and the deep trench 50 is filled with a dielectric layer 70 to prevent breakdown.

[0020] Embodiment 2 like Figure 2 The terminal structure of a fast recovery diode device shown includes an N-type substrate 10, wherein the N-type substrate 10 includes an N+ substrate layer 11 and an N- epitaxial layer 12 formed on the N+ substrate layer 11, and the conductivity type of the N- epitaxial layer 12 is N-type; The N-epitaxial layer 12 is provided with a P-type implanted main junction anode region 20, a P-type implanted field limiting ring and a deep N-well implanted termination ring 30 in sequence, the main junction anode region 20 and the field limiting ring are both P-type in conductivity, and the P-type concentration implanted in the main junction anode region 20 is less than the P-type concentration implanted in the termination ring 60; The conductivity type of the main junction anode region 20 is opposite to that of the N-epitaxial layer 12 and is used to form an active region. The conductivity type of the field limiting ring is opposite to that of the N-epitaxial layer 12 and is used to form a terminal region. The P-type field limiting ring forms a P / N junction with the N-epitaxial layer 12. The conductivity type of the termination ring 30 is N-type. The back N+ substrate layer 11 forms the cathode of the main junction, and a passivation layer 40 is deposited on the top layer of the device; A plurality of deep grooves 50 formed by etching are arranged in the field limiting ring of the terminal region of the N-epitaxial layer 12, and the deep grooves 50 are formed by one-time photolithography, and the deep grooves 50 include a first layer of grooves 51, a second layer of grooves 52 and a third layer of grooves 53, the width of the second layer of grooves 52 is smaller than the width of the first layer of grooves 51, and the width of the third layer of grooves 53 is smaller than the width of the second layer of grooves 52, so that the deep grooves 50 form a stepped shape with a wide top and a narrow bottom; An oxide layer 80 is grown in the deep trench 50 and a dielectric layer 70 is filled on the oxide layer 80 . The dielectric layer 70 is filled with P-doped polysilicon.

[0021] The manufacturing method of the terminal structure of the fast recovery diode device in the second embodiment is mainly different from the manufacturing method in the first embodiment in that the terminal ring 60 of the device is formed by filling the deep trench 50 with a P-type dielectric layer 70 instead of the P-type implantation in the deep trench 50. The specific steps are as follows: S1. A silicon oxide layer with a thickness of about 1 μm is grown on the surface of the selected N-type substrate 10 silicon wafer, and a terminal region is defined by photolithography and etching. The silicon oxide layer in the terminal region is etched, such as Figure 3 As shown; S2. Then, the substrate under the silicon oxide layer in the terminal region is etched, and the first layer of grooves 51 perpendicular to the substrate surface are etched using anisotropic etching, such as Figure 4 As shown; S3. By depositing a silicon oxide layer and etching back, a silicon oxide sidewall is formed at the edge of the sidewall of the first layer trench 51 for isolation in subsequent etching, such as Figure 5 As shown; S4. Continue etching the substrate to form a second layer of grooves 52, such as Figure 6 As shown, the width of the second layer trench 52 is smaller than the width of the first layer trench 51 due to the obstruction of the silicon oxide sidewall of the first layer trench 51; S5. Continue to deposit the silicon oxide layer and etch back, and continue to form silicon oxide sidewalls at the edges of the first layer trench 51 and the second layer trench 52 for isolation in subsequent etching, such as Figure 7 As shown; S6. Continue etching the substrate to form a third layer of grooves 53, such as Figure 8 As shown, the width of the third layer trench 53 is smaller than the width of the second layer trench 52 due to the obstruction of the silicon oxide sidewalls of the first layer trench 51 and the second layer trench 52, and the first layer trench 51, the second layer trench 52 and the third layer trench 53 form a stepped deep trench 50 which is wide at the top and narrow at the bottom; S7. Remove the silicon oxide layer, and define a deep N well on the N-epitaxial layer 12 by photolithography to form a termination ring 30 for deep N well implantation, such as Fig.15 As shown; S8. Depositing an oxide layer 80 in the deep trench 50 and depositing a photolithography on the oxide layer 80, such as Fig.16 As shown, the thickness of the oxide layer 80 must be able to withstand the voltage applied by the back cathode, so the thickness and quality of the oxide layer 80 must be strictly controlled during growth; S9. After the oxide layer 80 is grown, the anode region is defined by photolithography and etching of the oxide layer 80 and a P-type is injected to form the main junction anode region 20, such as Fig.17 As shown; S10. High temperature advancement after injection; S11. Fill the dielectric layer 70 (P-doped polysilicon) on the oxide layer 80 in the deep trench 50 as a suspended field plate, and fill the entire inner surface of the deep trench 50 with polysilicon, such as Fig.18As shown, when depositing polysilicon, polysilicon can be first deposited on the deep trench 50 and the entire surface near the deep trench 50 until the entire surface is filled, and then the surface polysilicon covered by unnecessary polysilicon is etched away, so that only the polysilicon in the deep trench 50 is left, and a small section is recessed on the surface. The function of the suspended field plate is to expand the electric lines of the P / N junction, thereby improving the voltage resistance; S12. Deposit a passivation layer 40 of silicon nitride and polyimide, and photolithographically etch the passivation layer 40 to complete the production of the top structure, such as Fig.19 As shown; S13. Thinning the back side of the silicon wafer to a specific thickness, injecting N-type impurities into the back side, forming a field stop layer by low temperature annealing or laser annealing, and ensuring that the surface impurity concentration is high enough to form an ohmic contact. When a substrate with a deep back diffusion layer is selected, the back side impurity injection and annealing process may not be performed; S14. Deposit the back metal by sputtering or evaporation, and finally perform minority carrier lifetime control process to improve the reverse recovery characteristics of the device.

[0022] Different from the first embodiment, in the second embodiment, an oxide layer 80 is grown in the deep trench 50 and a dielectric layer 70 is filled on the oxide layer 80 to replace the P+ injection of Pring. Filling the dielectric layer 70 can also adjust the terminal electric field of the device to improve performance.

[0023] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A terminal structure of a fast recovery diode device, comprising an N-type substrate (10), characterized in that: The N-type substrate (10) comprises an N+ substrate layer (11) and an N- epitaxial layer (12) formed on the N+ substrate layer (11); A plurality of deep grooves (50) having a stepped shape and being wider at the top and narrower at the bottom are formed by etching in the field limiting ring of the terminal region of the N-epitaxial layer (12), and the deep grooves (50) are formed by photolithography in one step; A P-type is implanted at the bottom of the deep trench (50) to form a terminal ring (60) and a dielectric layer (70) is filled in the deep trench (50), or an oxide layer (80) is grown in the deep trench (50) and a dielectric layer (70) is filled on the oxide layer (80).

2. The terminal structure of a fast recovery diode device according to claim 1, characterized in that: The deep groove (50) comprises a first layer groove (51), a second layer groove (52) and a third layer groove (53), the width of the second layer groove (52) is smaller than the width of the first layer groove (51), and the width of the third layer groove (53) is smaller than the width of the second layer groove (52).

3. The terminal structure of a fast recovery diode device according to claim 1, characterized in that: The N-epitaxial layer (12) is also provided with a P-type injected main junction anode region (20) and a deep N-well injected termination ring (30), the back N+ substrate layer (11) forms a cathode of the main junction, and a passivation layer (40) is deposited on the top layer.

4. The terminal structure of a fast recovery diode device according to claim 3, characterized in that: The conductivity types of the N-epitaxial layer (12) and the termination ring (30) are both N-type, and the conductivity types of the main junction anode region (20) and the field limiting ring are both P-type; The conductivity type of the main junction anode region (20) is opposite to the conductivity type of the N-epitaxial layer (12), and is used to form an active region; The conductivity type of the field limiting ring is opposite to the conductivity type of the N-epitaxial layer (12), and is used to form a terminal region; The P-type field limiting ring and the N-type N-epitaxial layer (12) form a P / N junction.

5. The terminal structure of a fast recovery diode device according to claim 3, characterized in that: The P-type concentration injected into the main junction anode region (20) is lower than the P-type concentration injected into the terminal ring (60).

6. The terminal structure of the fast recovery diode device according to any one of claims 1 to 5, characterized in that: The specific steps of the manufacturing method of the first terminal structure are as follows: S1. growing a silicon oxide layer on the surface of a selected N-type substrate (10) silicon wafer, and defining a terminal region by photolithography and etching, wherein the silicon oxide layer in the terminal region is etched; S2. Then, the substrate under the silicon oxide layer in the terminal region is etched, and a first layer of grooves (51) perpendicular to the substrate surface is etched using anisotropic etching; S3. By depositing a silicon oxide layer and etching back, a silicon oxide sidewall is formed at the edge of the sidewall of the first layer trench (51) for isolation in subsequent etching; S4. Continue etching the substrate to form a second-layer trench (52) morphology. Due to the obstruction of the silicon oxide sidewall of the first-layer trench (51), the width of the second-layer trench (52) is smaller than the width of the first-layer trench (51); S5. Continue to deposit the silicon oxide layer and etch back, and continue to form silicon oxide sidewalls at the edges of the first layer trench (51) and the second layer trench (52) for isolation in subsequent etching; S6. Continue etching the substrate to form a third-layer groove (53) morphology. Due to the obstruction of the silicon oxide sidewalls of the first-layer groove (51) and the second-layer groove (52), the width of the third-layer groove (53) will be smaller than the width of the second-layer groove (52). The first-layer groove (51), the second-layer groove (52) and the third-layer groove (53) form a stepped deep groove (50) that is wide at the top and narrow at the bottom. S7. removing the silicon oxide layer, and injecting P-type into the deep trench (50) through photolithography to form a terminal ring (60), and injecting P-type into the main junction to form a main junction anode region (20), wherein the concentration of P-type injected into the main junction anode region (20) is less than the concentration of P-type injected into the terminal ring (60); S8. By photolithography, a deep N-well is defined on the N-epitaxial layer (12) to form a termination ring (30) for deep N-well implantation; S9. High temperature advancement after injection; S10. depositing a dielectric layer (70) and densifying the dielectric layer (70), and then defining an active region of the device by photolithography; S11. Depositing a passivation layer (40) of silicon nitride and polyimide, and photolithographically etching the passivation layer (40) to complete the production of the top structure; S12. Thinning the back side of the silicon wafer, injecting N-type impurities into the back side, forming a field stop layer by low temperature annealing or laser annealing, and ensuring that the surface impurity concentration is high enough to form an ohmic contact; S13. Deposit the back metal by sputtering or evaporation, and finally perform minority carrier lifetime control process to improve the reverse recovery characteristics of the device.

7. The terminal structure of the fast recovery diode device according to any one of claims 1 to 5, characterized in that: The specific steps of the manufacturing method of the second terminal structure are as follows: S1. growing a silicon oxide layer on the surface of a selected N-type substrate (10) silicon wafer, and defining a terminal region by photolithography and etching, wherein the silicon oxide layer in the terminal region is etched; S2. Then, the substrate under the silicon oxide layer in the terminal region is etched, and a first layer of grooves (51) perpendicular to the substrate surface is etched using anisotropic etching; S3. By depositing a silicon oxide layer and etching back, a silicon oxide sidewall is formed at the edge of the sidewall of the first layer trench (51) for isolation in subsequent etching; S4. Continue etching the substrate to form a second-layer trench (52) morphology. Due to the obstruction of the silicon oxide sidewall of the first-layer trench (51), the width of the second-layer trench (52) is smaller than the width of the first-layer trench (51); S5. Continue to deposit the silicon oxide layer and etch back, and continue to form silicon oxide sidewalls at the edges of the first layer trench (51) and the second layer trench (52) for isolation in subsequent etching; S6. Continue etching the substrate to form a third-layer groove (53) morphology. Due to the obstruction of the silicon oxide sidewalls of the first-layer groove (51) and the second-layer groove (52), the width of the third-layer groove (53) will be smaller than the width of the second-layer groove (52). The first-layer groove (51), the second-layer groove (52) and the third-layer groove (53) form a stepped deep groove (50) that is wide at the top and narrow at the bottom. S7. removing the silicon oxide layer, defining a deep N-well on the N-epitaxial layer (12) by photolithography, and forming a termination ring (30) for deep N-well implantation; S8. Depositing an oxide layer (80) in the deep trench (50) and performing photolithography on the oxide layer (80); S9. After the oxide layer (80) is grown, the anode region is defined by photolithography and etching of the oxide layer (80) and a P-type is implanted to form a main junction anode region (20); S10. High temperature advancement after injection; S11. Filling a dielectric layer (70) on the oxide layer (80) in the deep trench (50) as a suspended field plate, and filling the entire inner surface of the deep trench (50) with polysilicon dielectric; S12. Depositing a passivation layer (40) of silicon nitride and polyimide, and photolithographically etching the passivation layer (40) to complete the production of the top structure; S13. Thinning the back side of the silicon wafer to a specific thickness, injecting N-type impurities into the back side, forming a field stop layer by low temperature annealing or laser annealing, and ensuring that the surface impurity concentration is high enough to form an ohmic contact; S14. Deposit the back metal by sputtering or evaporation, and finally perform minority carrier lifetime control process to improve the reverse recovery characteristics of the device.

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