Groove type power device and manufacturing method thereof

Abstract

The invention provides a trench type power device and a manufacturing method thereof. The manufacturing method comprises the steps of forming a doped region which extends inwards from a first main surface of a semiconductor layer to reach a first extension depth; and forming a plurality of gate trenches extending inwardly from the first main surface of the semiconductor layer, the gate trenches having a second extension depth smaller than the first extension depth, and removing a top surface of the doped region and a section below the top surface to the second extension depth while forming some of the gate trenches to form a charge compensation region. According to the invention, some gate trenches are formed, and meanwhile, the section, reaching the second extension depth from the top surface, of the pre-formed doped region is removed, so that the charge compensation region is introduced to the bottom of at least one gate trench, the electric field distribution of the drift region is modulated by using the charge coupling effect, and a triangular electric field of the drift region is converted into a trapezoidal electric field; therefore, the compromise relationship between the conduction loss and the voltage resistance is optimized in the process of thinning the drift region.

Description

Technical Field

[0001] The invention belongs to the field of semiconductors, and in particular relates to a trench type power device and a manufacturing method thereof. Background Art

[0002] Power semiconductor devices are mainly power metal oxide semiconductor field effect transistors (often abbreviated as MOSFET), insulated gate bipolar transistors (IGBT) and power integrated circuits (power IC, often abbreviated as PIC). In the application of power and high-voltage devices, transistors are required to have sufficiently low conduction losses and greater current driving capabilities. Among them, MOSFET and IGBT are widely used in power electronics due to their faster switching speed and lower driving loss.

[0003] Taking trench MOSFET power devices as an example, they are often used as switching elements in power electronic circuits. on,sp ) and breakdown voltage (BV) are one of its important parameter indicators. Obtaining higher breakdown voltage and lower on-resistance can improve the competitiveness of the product.

[0004] In order to improve the breakdown resistance, the thickness of the drift region, the doping concentration or similar methods are usually increased, which will increase the on-resistance of the device, that is, increase the conduction loss. How to improve the withstand voltage performance of the device without affecting the conduction loss, or improve the compromise between the conduction loss and withstand voltage performance of the device has always been a research hotspot for researchers from various countries.

[0005] Therefore, it is necessary to provide an improved structure of a trench power device and a manufacturing method thereof.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a trench power device and a method for manufacturing the same, so as to solve the problem that the thickness of the drift region of the trench power device in the prior art is reduced while sacrificing the withstand voltage performance of the device.

[0008] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a trench power device, comprising the following steps:

[0009] Providing a substrate, the substrate comprising a semiconductor layer, the semiconductor layer having a doped region extending inward from a first main surface thereof to a first extension depth, the semiconductor layer having a conductivity type opposite to that of the doped region;

[0010] forming a plurality of gate trenches extending inward from the first main surface of the semiconductor layer, the gate trenches having a second extension depth less than the first extension depth, and removing a section of the doped region from its top surface by the second extension depth while forming some of the gate trenches to form a charge compensation region;

[0011] forming a trench gate structure in the gate trench;

[0012] forming a body region on the first main surface of the semiconductor layer, wherein the body region has a conductivity type opposite to that of the semiconductor layer, and forming a source region in the body region;

[0013] An interlayer dielectric layer and a front metal layer are formed on the first main surface of the semiconductor layer, and the front metal layer is separated into a source lead-out terminal and a gate lead-out terminal.

[0014] Optionally, the step of forming the doped region includes:

[0015] Etching from the first main surface of the semiconductor layer inwardly to form at least one deep trench having a first extension depth;

[0016] The deep trench is filled with a single crystal semiconductor material and doped in situ.

[0017] Optionally, the step of forming the charge compensation region includes: the step of forming the charge compensation region includes: defining a gate etching mask on the substrate, the gate etching mask defining a window exposing the doped region; performing anisotropic etching based on the gate etching mask to form a plurality of gate trenches extending inward from the first main surface of the semiconductor layer, and at the same time forming the doped region retained below the gate trench into a charge compensation region, wherein the number of the gate trenches is greater than or equal to the number of the deep trenches.

[0018] Optionally, a single crystal semiconductor material is grown on the inner surface of the deep trench by an epitaxial process, and in-situ doping is performed to form the doped region, wherein the material of the doped region includes one of single crystal silicon, silicon germanium, silicon carbide, gallium arsenide, and indium phosphide.

[0019] Optionally, the single crystal semiconductor material is grown on the inner surface of the deep trench by a chemical vapor deposition process.

[0020] Optionally, the base includes a substrate, and the second main surface of the semiconductor layer is adjacent to the substrate opposite to the first main surface. The step of forming a back structure based on the substrate includes: thinning the back side of the substrate away from the semiconductor layer; and forming a back metal layer on the back side of the substrate after thinning.

[0021] The present invention also provides a trench power device, comprising:

[0022] A semiconductor layer, wherein a drift region and a plurality of gate trenches extending inwardly from a first main surface of the semiconductor layer are provided, a charge compensation region extending back to the gate trench is provided at the bottom of at least one of the plurality of gate trenches, and the drift region has a conductivity type opposite to that of the charge compensation region:

[0023] A trench gate structure is disposed in the gate trench;

[0024] A body region and a source region, wherein the body region and the source region are stacked on the drift region;

[0025] A front metal layer is arranged on the first main surface of the semiconductor layer and is separated from the semiconductor layer by an interlayer dielectric layer. The front metal layer is separated into a source lead terminal and a gate lead terminal.

[0026] Optionally, the number of the gate trenches in the semiconductor layer is greater than or equal to the number of the charge compensation regions.

[0027] Optionally, a height difference between an end surface of the charge compensation region extending away from the gate trench and an opening of the gate trench is 1 μm to 60 μm.

[0028] Optionally, the trench power device includes a vertical double diffused metal oxide semiconductor field effect transistor, or an insulated gate bipolar transistor.

[0029] As described above, the trench power device and the manufacturing method thereof provided by the present invention have the following beneficial technical effects:

[0030] The manufacturing method of the trench-type power device of the present invention removes the section of the pre-formed doping region that is at a second extension depth from the top surface thereof while forming some gate trenches, thereby introducing a charge compensation region at the bottom of at least one gate trench, and utilizing the charge coupling effect to modulate the electric field distribution of the drift region, so that the triangular electric field of the drift region is transformed into a trapezoidal electric field, thereby improving the voltage resistance of the device; in addition, the manufacturing method of the present invention is also applicable to power MOSFET and IGBT devices, has broad application prospects, has simple process steps and will not significantly increase manufacturing costs.

[0031] By applying the manufacturing method of the present invention, a charge compensation region is introduced at the bottom of some gate trenches. Under the reverse withstand voltage state, the charge compensation region and the adjacent drift region are mutually depleted, so that the triangular electric field of the drift region is transformed into a trapezoidal electric field. In this way, the compromise relationship between conduction loss and withstand voltage performance is optimized in the process of thinning the drift region, and the electric field concentration effect at the bottom of the gate trench can be alleviated, thereby avoiding premature breakdown of the device caused by reliability problems of the gate dielectric, and ensuring the long-term reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Shown is a process flow chart of a method for manufacturing a trench power device in an embodiment of the present invention.

[0033] Figure 2 9 is a schematic diagram showing the structure of each step of the method for manufacturing a trench power device according to an embodiment of the present invention; wherein, Figure 9a and Figure 9b It is a schematic diagram of the structure obtained after step S7 in the method for manufacturing a trench power device.

[0034] Component number description

[0035] 20 Semiconductor layer

[0036] 202 Deep Groove

[0037] 204 Doping Area

[0038] 206 Charge compensation area

[0039] 210 Gate Trench

[0040] 212 Gate Oxide

[0041] 214 Polysilicon Gate

[0042] 220 Body Area

[0043] 230 Source Area

[0044] 310 Contact hole

[0045] 320 Interlayer dielectric layer

[0046] 30 Front metal layer

[0047] 50 Back metal layer

[0048] 240 Field cutoff layer

[0049] 410 First collector area

[0050] 420 Second collector area

[0051] Steps S1 to S7 DETAILED DESCRIPTION

[0052] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed according to actual needs, and the component layout type may also be more complex.

[0054] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0055] The present invention provides a trench type power device and a manufacturing method thereof. The first conductivity type may be N type, the second conductivity type may be P type, and the trench type power device structure is an N type device.

[0056] Afterwards, combined Figure 1 , a method for manufacturing a trench field effect transistor is specifically described, and the manufacturing method comprises the following steps:

[0057] First, step S1 is performed to provide a substrate, wherein the substrate includes a semiconductor layer.

[0058] Specifically, the base includes a semiconductor substrate itself or a substrate on which a semiconductor layer is formed. In this embodiment, the semiconductor layer has a first conductivity type, that is, N-type.

[0059] In one implementation, the base includes a substrate and a semiconductor layer located on the substrate, and the semiconductor layer is preferably grown on the substrate by epitaxial growth, wherein the material of the semiconductor layer 20 includes one of silicon, silicon germanium, silicon carbide, gallium arsenide, and indium phosphide.

[0060] In another implementation, the base is a semiconductor substrate, and a portion of the semiconductor substrate between the first main surface and the second main surface is used as a drift region.

[0061] Then, step S2 is performed to form a doped region extending inward from the first main surface of the semiconductor layer to a first extension depth, wherein the semiconductor layer has a conductivity type opposite to that of the doped region.

[0062] Specifically, the step of forming the doped region 204 includes: etching the semiconductor layer 20 to form one or more deep trenches 202 extending inward from the first main surface of the semiconductor layer to a first extension depth; and filling the deep trenches 202 with a single crystal semiconductor material.

[0063] like Figure 2 As shown, in some examples, etching is performed based on a groove pattern mask to form the deep groove 202, wherein the groove pattern mask can be a patterned hard mask layer, in which an etching window corresponding to the deep groove is formed, and the first extension depth of the deep groove extending into the interior of the semiconductor layer can be several microns to tens of microns, typically between 1μm and 60μm, more typically between 10μm and 60μm. In a specific example, the shape of the deep groove 202 includes a U-shaped groove, and the semiconductor layer 20 can be etched by a deep reactive ion etching (DRIE) method to form the U-shaped groove, avoiding the appearance of sharp corners, and the deep reactive ion etching method can obtain a deep groove sidewall with low surface roughness. The distribution, size and morphology of the deep groove 202 can be determined according to actual conditions, and no excessive restrictions are made here.

[0064] Furthermore, in step S2, the doping region 204 is formed by, for example, ion implantation or in-situ doping. Figure 3 As shown, the step of forming the doped region 204 includes: growing a single crystal semiconductor material on the inner surface of the deep trench by an epitaxial process, and performing in-situ doping at the same time, wherein the material of the doped region includes, for example, silicon, silicon germanium, silicon carbide, gallium arsenide, indium phosphide, or similar single crystal semiconductor materials doped with P type. Preferably, the doped region 204 can be grown on the inner surface of the deep trench by a chemical vapor deposition process, and this process has good step coverage, thereby being able to obtain a high-quality epitaxial layer at an efficient deposition rate. In some cases, the doped region may contain the same material as the semiconductor layer, so as to facilitate subsequent synchronous etching of the doped region and the semiconductor layer. In this embodiment, the conductivity type of the doped region is P type, and a P type doping precursor, such as diborane (B2H6), boron trifluoride (BF3) and / or other P type doping precursors, can be used to form the P type doped region by a chemical vapor deposition process, thereby.

[0065] The step of forming the doped region 202 further includes: removing the remaining photoresist layer and the hard mask layer.

[0066] Then, execute step S3, such as Figure 4 As shown, a plurality of gate trenches extending inward from the first main surface of the semiconductor layer are formed, and the gate trenches have a second extension depth that is smaller than the first extension depth.

[0067] Specifically, in step S3, while forming some gate trenches, the top surface of the doped region and the section below it reaching the second extension depth are removed, and the charge compensation region 206 retained below the gate trenches is Figure 3 In the semiconductor layer 20 shown, the number of the gate trenches 210 is greater than the number of the charge compensation regions.

[0068] like Figure 4 As shown, the steps of forming the gate trench 210 are: defining a gate etch mask on the substrate by lithography; and anisotropically etching the semiconductor layer from the first main surface of the semiconductor layer based on the gate etch mask, wherein the gate etch mask can be a patterned hard mask layer.

[0069] In some examples, at step S3, the step of forming the charge compensation region 206 includes: etching based on a graphic mask to form a plurality of gate trenches 210 extending inward from the first main surface of the N-type drift region; while forming some gate trenches, removing the top surface of the doped region and the section below it to the second extension depth; wherein, an etching window exposing the doped region is defined in the gate etching mask, and the top surface of the doped region is within the projection of the etching window on the first main surface of the semiconductor layer, and accordingly, the resulting gate trench has a lateral size slightly larger than that of the charge compensation region. Figure 3 As shown, the end surface of the gate trench extending into the semiconductor layer is higher than the end surface of the doped region extending into the semiconductor layer, and by removing a portion of the doped region and retaining a section whose distance from the top surface exceeds the second extension depth, some end surfaces of some gate trenches are terminated in the doped region, and the retained doped region is formed as a charge compensation region 206. By introducing the charge compensation region below the gate trench, the drift regions adjacent to the charge compensation region are mutually depleted under the reverse withstand voltage state, thereby modulating the electric field distribution of the drift region.

[0070] Compared with the method of forming a buried region (usually, with a thickness of less than 2 μm) at the bottom of the gate trench by an ion implantation process, the above technical solution forms a doped region based on the epitaxial material filling the deep trench, and then partially removes the doped region to obtain a charge compensation region. The resulting charge compensation region extends into a deeper position in the drift region, which can not only alleviate the electric field concentration effect at the bottom of the gate trench and ensure the long-term reliability of the device, but also optimize the electric field distribution in the drift region.

[0071] Then, execute step S4, such as Figures 4 to 5 As shown, a trench gate structure is formed in the gate trench.

[0072] Specifically, in step S4, the step of forming the trench gate structure includes: sequentially forming a gate oxide layer 212 and a polysilicon gate 214 in the gate trench 210. In this embodiment, the gate oxide layer 212 is conformally deposited on the inner surface of the gate trench by thermal oxidation or chemical vapor deposition.

[0073] As an example, the steps of forming the polysilicon gate 214 include: depositing polysilicon material using a chemical vapor deposition (CVD) process so that the polysilicon material fills the gate trench 210; planarizing the substrate to remove the polysilicon material covering the N-type epitaxial layer 20, thereby forming the polysilicon gate 214, wherein the planarization method includes: a chemical mechanical polishing (CMP) process.

[0074] Then, step S5 is performed to form a body region on the first main surface of the semiconductor layer, wherein the body region has a conductivity type opposite to that of the semiconductor layer, and a source region is formed in the body region.

[0075] like Figure 6 As shown, a second conductive type dopant is used to form a body region 220 on the first main surface of the semiconductor layer by thermal diffusion or ion implantation; and a first conductive type ion implantation is performed on the first main surface of the semiconductor layer to form a source region 230.

[0076] In this embodiment, the conductivity type of the body region 220 is P type, and the conductivity type of the source region 230 is N type. Boron ions are used as dopants to perform ion implantation as described in step S5 through general injection to form a P type body region. Arsenic ions are used as dopants to perform ion implantation as described in step S6 based on an implantation mask to form an N+ type source region.

[0077] Then, step S6 is performed to form an interlayer dielectric layer and a front metal layer on the first main surface of the semiconductor layer, and the front metal layer is separated into a source terminal and a gate terminal.

[0078] Specifically, step S6 includes: covering the semiconductor layer 20 to form an interlayer dielectric layer 320, and forming a contact hole 310 through the interlayer dielectric layer 320; filling and covering the contact hole 310 to form a front metal layer 30, and the front metal layer is separated into a source lead terminal and a gate lead terminal.

[0079] As an example, Figure 7 As shown, the step of forming the contact hole 310 includes: etching based on the contact hole pattern mask to penetrate the interlayer dielectric layer 320 to form a gate contact hole exposing the polysilicon gate 214, and a source contact hole penetrating the source region and extending into the body region.

[0080] See also Figure 8 Step S6 further includes: filling the contact hole 310, covering the interlayer dielectric layer 320, and forming a front metal layer 30; and separating the front metal layer into a source terminal and a gate terminal by, for example, a photolithography process and an etching process.

[0081] Furthermore, after the step of forming the source contact hole 310, ion implantation is performed through the source contact hole 310 to form a body contact region 221; and then, an ohmic contact is formed between the front metal layer and the body contact region.

[0082] Then, step S7 is performed to form a backside structure on a side of the substrate away from the semiconductor layer.

[0083] The step of forming the back structure includes: forming a back metal layer on a side of the substrate away from the semiconductor layer.

[0084] like Figure 9a As shown, in one implementation, when the trench power device is formed as a vertical double diffused field effect transistor with a trench gate, the base includes a substrate heavily doped with a first conductivity type, and a second main surface of the semiconductor layer arranged opposite to the first main surface is adjacent to the substrate, and the step of forming a back structure based on the substrate includes: thinning the side of the substrate away from the semiconductor layer, that is, a back thinning process of the substrate; and forming a back metal layer on the back side of the substrate after thinning.

[0085] In another implementation, when the trench power field effect transistor is an insulated gate bipolar field effect transistor, after the second main surface of the semiconductor layer away from the first main surface is thinned, that is, the back side of the semiconductor layer is thinned to form a back side structure, which includes the following steps: Figure 9b As shown, a field stop layer 240 is formed on the second main surface of the semiconductor layer; a collector region is formed on the second main surface of the semiconductor layer, such as a first collector region 410 and a second collector region 420 as shown in the figure.

[0086] For example, the back metal layer 22 includes a titanium layer, a nickel layer and a silver layer deposited in sequence, thereby completing the manufacturing of a trench power device, such as Figure 9b The back metal layer is shown, which serves as the metal collector.

[0087] Furthermore, after the step of thinning the substrate layer, an ohmic contact is made on the back side of the thinned substrate or the semiconductor layer.

[0088] The present invention further provides a trench type power device, which is preferably manufactured using the trench type power device manufacturing method described above.

[0089] The trench power device includes a semiconductor layer 20, a body region 220, a source region 230 and a trench gate structure. The semiconductor layer 20 is provided with a drift region and a plurality of gate trenches 210 extending inward from the first main surface of the semiconductor layer. The bottom of at least one gate trench is provided with a charge compensation region 206 extending back to the gate trench. The drift region has a conductivity type opposite to that of the charge compensation region: a trench gate structure is provided in the gate trench 210; the body region 220 and the source region 230 are stacked on the drift region. Due to the introduction of the charge compensation region, under the condition of the same thinning thickness of the drift region, the voltage resistance of the device is improved without significantly changing the conduction voltage drop; in other words, under the condition of providing the same breakdown voltage BV, the drift region is allowed to have a significantly thinned thickness and / or a significantly increased doping concentration, thereby improving the on-resistance R ON , thereby optimizing the trade-off between the device's conduction loss and reverse withstand voltage.

[0090] like Figure 9a to Figure 9b As shown, an interlayer dielectric layer 320 and a front metal layer 30 are sequentially arranged on the first main surface of the semiconductor layer, the front metal layer is separated from the semiconductor layer by the interlayer dielectric layer 310, a contact hole 310 is formed through the interlayer dielectric layer, and the front metal layer 30 is separated into a source lead terminal and a gate lead terminal.

[0091] like Figure 9a and Figure 9b As shown, a charge compensation region 206 is provided in the drift layer 20, and the charge compensation region 206 is arranged to extend from the bottom of at least one gate trench back to the gate trench 210, and the charge compensation region 206 has a conductivity type opposite to that of the drift layer. By utilizing the charge coupling effect, the charge compensation region 206 and the adjacent drift region are mutually depleted, and the electric field spike in the original drift layer is alleviated under the reverse withstand voltage state, and the breakdown voltage BV is effectively improved. In some examples, the height difference between the end surface of the charge compensation region 206 extending back to the gate trench and the opening of the gate trench is several microns to tens of microns, typically between 1μm and 60μm, and more typically between 10μm and 60μm. For example, when the gate trench has an extension depth of 4μm to 5μm, the extension depth of the charge compensation region 206 extending back to the gate trench can be between one and several times the extension depth of the gate trench.

[0092] Under the condition of ensuring the performance of the device, the number and distribution of the doping regions can be appropriately determined according to the thickness of the gate oxide layer of the device, and the doping concentration and thickness of the drift region. In some examples, the voltage resistance of the device is further improved by increasing the number of the charge compensation regions, for example, the number of the gate trenches is greater than the number of the charge compensation regions and less than twice the number of the charge compensation regions.

[0093] As an example, the trench power device may be a vertical double diffused metal oxide semiconductor (MOS) field effect transistor, or an insulated gate bipolar transistor (IGBT). Figure 9b As shown, when the power transistor is selected as an insulated gate bipolar transistor, a field stop layer 240 and a collector region are stacked in sequence on the second main surface of the semiconductor layer, and a back metal layer 50 is provided on the second main surface of the semiconductor layer, and the back metal layer is used as a metal collector.

[0094] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a trench power device, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a semiconductor layer, the semiconductor layer having a doped region extending inward from a first main surface thereof to a first extension depth, the semiconductor layer having a conductivity type opposite to that of the doped region; forming a plurality of gate trenches extending inward from the first main surface of the semiconductor layer, the gate trenches having a second extension depth less than the first extension depth, and removing the top surface of the doped region and a section thereof below the top surface up to the second extension depth while forming some of the gate trenches to form a charge compensation region; forming a trench gate structure in the gate trench; forming a body region on the first main surface of the semiconductor layer, wherein the body region has a conductivity type opposite to that of the semiconductor layer, and forming a source region in the body region; An interlayer dielectric layer and a front metal layer are formed on the first main surface of the semiconductor layer, and the front metal layer is separated into a source lead-out terminal and a gate lead-out terminal.

2. The method according to claim 1, characterized in that: The step of forming the doped region comprises: Etching inwardly from the first main surface of the semiconductor layer to form at least one deep trench having a first extension depth; The deep trench is filled with a single crystalline semiconductor material.

3. The method according to claim 2, characterized in that: The step of forming the charge compensation region comprises: defining a gate etching mask on the substrate, wherein the gate etching mask defines a window for exposing the doped region; performing anisotropic etching based on the gate etching mask to form a plurality of gate trenches extending inward from the first main surface of the semiconductor layer, and at the same time forming the doped region retained below the gate trenches into a charge compensation region, wherein the number of the gate trenches is greater than or equal to the number of the deep trenches.

4. The method according to claim 2, characterized in that: A single crystal semiconductor material is grown on the inner surface of the deep trench through an epitaxial process, and in-situ doping is performed to form the doped region, wherein the material of the doped region includes one of single crystal silicon, silicon germanium, silicon carbide, gallium arsenide, and indium phosphide.

5. The trench power device according to claim 4, characterized in that: The single crystal semiconductor material is grown on the inner surface of the deep trench by a chemical vapor deposition process.

6. The method according to claim 1, characterized in that: The base includes a substrate, a second main surface of the semiconductor layer disposed opposite to the first main surface is adjacent to the substrate, and a step of forming a backside structure based on the substrate includes: The back side of the substrate away from the semiconductor layer is thinned; and a back side metal layer is formed on the back side of the substrate after thinning.

7. A trench power device, characterized in that: include: A semiconductor layer, wherein a drift region and a plurality of gate trenches extending inwardly from a first main surface of the semiconductor layer are provided, a charge compensation region extending back to the gate trench is provided at the bottom of at least one of the plurality of gate trenches, and the drift region has a conductivity type opposite to that of the charge compensation region: A trench gate structure is disposed in the gate trench; A body region and a source region, wherein the body region and the source region are stacked on the drift region; A front metal layer is arranged on the first main surface of the semiconductor layer and is separated from the semiconductor layer by an interlayer dielectric layer. The front metal layer is separated into a source lead terminal and a gate lead terminal.

8. The trench power device according to claim 7, characterized in that: The number of the gate trenches in the semiconductor layer is greater than or equal to the number of the charge compensation regions.

9. The trench power device according to claim 7, characterized in that: A height difference between an end surface of the charge compensation region extending away from the gate trench and an opening of the gate trench is 1 μm to 60 μm.

10. The trench power device according to claim 7, characterized in that: The trench power device includes a vertical double diffused metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

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