LDMOS device and preparation method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. According to the preparation method, the covering layer with the gradually-changed thickness is used as the mask layer of the ion implantation process, so that the gradually-changed region with the gradually-changed dosage can be formed in the drift region through the one-time ion implantation process, and the closer the part, close to the well region, in the gradually-changed region is, the higher the dosage of ions of the second conduction type is; the part, close to the well region, in the drift region is more easily and completely depleted, the depletion degree in the drift region is increased, the depletion layer width on the surface of the device is greatly improved, a depletion line can be far away from a channel region of the device, the risk that the device is broken down is reduced, meanwhile, high-concentration carriers can be prevented from being collected near a channel, and the device reliability is improved. And the hot carrier injection effect of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an LDMOS device and a preparation method thereof. Background Art

[0002] LDMOS devices are a type of MOS devices that are formed using a double-diffused process and have a channel consisting of a double concentration difference. Compared with traditional CMOS devices, LDMOS devices have a longer low-doped drift region to bear the source-drain voltage, which is also the reason why LDMOS devices have a high withstand voltage. Due to the advantages of LDMOS devices such as high voltage resistance and good compatibility with CMOS devices, they are widely used in the BCD process to prepare power management chips.

[0003] Therefore, high withstand voltage is a major purpose of LDMOS device design. To improve the withstand voltage of LDMOS devices, currently commonly used methods include:

[0004] (1) By reducing the ion concentration of the drift region as a whole, the depletion layer width of the well region and the drift region under pressure can be increased. However, this method cannot effectively improve the surface depletion layer width near the channel of the device, and the surface withstand voltage is still insufficient;

[0005] (2) By increasing the length of the drift region, the breakdown voltage of the device is increased. However, the increase in the length of the drift region will lead to an increase in the chip area and an increase in the on-resistance of the device, making it difficult to simultaneously meet the requirements of low on-resistance and high breakdown voltage of the device.

[0006] (3) By using a field plate structure to balance the surface electric field and increase the breakdown voltage, this method cannot completely deplete the surface of the drift region, and the device's voltage resistance performance still needs to be improved. Summary of the invention

[0007] The object of the present invention is to provide a method for preparing an LDMOS device, so that the prepared LDMOS device has a larger surface depletion layer width and the depletion line is far away from the channel region of the device, thereby reducing the risk of device breakdown.

[0008] To this end, the present invention provides a method for preparing an LDMOS device, comprising: providing a substrate, in which a drift region of a first conductivity type and a well region of a second conductivity type are formed; forming a capping layer on the substrate, the capping layer covering at least a portion of the top surface of the drift region, wherein the capping layer includes a first portion close to the well region and having a gradient thickness, the thickness of the first portion gradually decreases along a direction close to the well region; and performing an ion implantation process of the second conductivity type to at least allow ions of the second conductivity type to pass through the first portion and be implanted into the drift region to form a gradient region, the dose of the second conductivity type ions in the gradient region gradually increasing along a direction close to the well region.

[0009] Optionally, the method for preparing the covering layer includes: coating a photoresist material on the substrate; performing a photolithography process to form a patterned photoresist layer, wherein the photoresist layer covers a portion of the drift region, and the photoresist layer is close to the edge of the well region and is spaced from the well region; and performing a baking process, wherein the edge of the photoresist layer collapses during the baking process and extends toward the well region to form an inclined portion with a gradually decreasing thickness, so as to constitute the covering layer having the first portion.

[0010] Optionally, the amount of ions of the first conductivity type in the gradient region is greater than the amount of ions of the second conductivity type, so that the gradient region appears as a doped region of the first conductivity type.

[0011] Optionally, the depth of the second conductive type ions in the gradient region gradually increases along a direction approaching the well region; and / or the concentration of the second conductive type ions in the gradient region gradually increases along a direction approaching the well region.

[0012] Optionally, the thickness of the first portion decreases continuously along a direction approaching the well region; or, the thickness of the first portion decreases gradually along a direction approaching the well region.

[0013] Optionally, the capping layer further includes a second portion with a constant thickness relative to the first portion, the second portion connecting a side of the first portion away from the well region and covering a predetermined region in the drift region for forming a drain region.

[0014] Optionally, the covering layer further exposes the well region; or, the covering layer further includes a third portion having a constant thickness relative to the first portion, and the third portion covers the well region.

[0015] Optionally, the cover layer is disposed close to an edge of the well region and spaced apart from the well region, so that a portion of the drift region close to the well region is exposed.

[0016] Optionally, the preparation method also includes: forming a gate structure on the substrate, the gate structure partially covering the well region and extending to cover the adjacent drift region; forming a source region and a drain region, the source region is formed in the well region, the drain region is formed in the drift region, and the gradient region is located between the drain region and the well region.

[0017] The present invention also provides an LDMOS device, comprising: a substrate, in which a drift region of a first conductivity type and a well region of a second conductivity type are formed; a gradient region of the first conductivity type is formed in the drift region, the gradient region also has ions of the second conductivity type, and the dose of the ions of the second conductivity type gradually increases along the direction approaching the well region.

[0018] Optionally, the depth of the second conductive type ions in the gradient region gradually increases along a direction approaching the well region; and / or the concentration of the second conductive type ions in the gradient region gradually increases along a direction approaching the well region.

[0019] Optionally, the LDMOS device also includes: a gate structure, which partially covers the well region and extends to cover the adjacent drift region; a source region and a drain region, the source region is formed in the well region, the drain region is formed in the drift region, and the gradient region is located between the drain region and the well region.

[0020] In the preparation method of the LDMOS device provided by the present invention, a cover layer with a gradual thickness is used as a mask layer of the ion implantation process, so that the second conductive type ions with a gradually changing ion dose can be implanted in the drift region through a single ion implantation process to form a gradually changing dose gradient region, and the portion of the gradient region closer to the well region has a higher ion dose of the second conductive type, which is equivalent to the portion of the gradient region closer to the well region presenting a lower concentration of first conductive type doping as a whole (for example, the portion of the gradient region closer to the well region has a higher dose of P-type ions, which correspondingly makes it present a lower concentration of N-type doping as a whole). Therefore, when the device is reversely withstand voltage, the portion of the drift region close to the well region can be more easily completely depleted, and the depletion layer generated by the drift region and the well region can be extended to a wider distance, which greatly increases the width of the depletion layer on the surface of the device, so that the depletion line can be away from the channel region of the device, reducing the risk of device breakdown. In addition, since the width of the depletion layer is enlarged, the depletion line is far away from the channel region, which can also prevent high-concentration carriers from gathering near the channel, which is beneficial to improving the hot carrier injection (HCI) problem of the device.

[0021] Furthermore, when preparing a cover layer with a gradual thickness change, for example, a photoresist material can be used to preferentially form a photoresist layer that covers part of the drift region, and the edge of the photoresist layer is spaced a predetermined distance from the well region. Afterwards, a baking process can be used to cause the edge of the photoresist layer to collapse and extend toward the well region to autonomously form a portion with a gradual thickness change, which is conducive to simplifying the process and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the structure of an existing LDMOS device.

[0023] Figure 2 It is a schematic flow chart of a method for manufacturing an LDMOS device in one embodiment of the present invention.

[0024] Figure 3-Figure 8 FIG. 1 is a schematic diagram of the structure of the LDMOS device in the first embodiment of the present invention during its preparation process.

[0025] Fig. 9 FIG. 1 is a schematic diagram of a partial depletion line of an LDMOS device during reverse withstand voltage in an embodiment of the present invention.

[0026] Fig.10 It is a schematic diagram of the structure of a cover layer formed during the preparation process of the LDMOS device in the second embodiment of the present invention.

[0027] Fig.11 It is a schematic diagram of the structure of a cover layer formed during the preparation process of the LDMOS device in the third embodiment of the present invention.

[0028] The reference numerals are as follows:

[0029] 10 / 100-substrate;

[0030] 110 - base;

[0031] 120-epitaxial layer;

[0032] 10N / 100N-drift zone;

[0033] 10P / 100P-well area;

[0034] 110N-gradient area;

[0035] 200-covering layer;

[0036] 210-Part I;

[0037] 220-Part II;

[0038] 200a-photoresist material;

[0039] 200b-patterned photoresist layer;

[0040] 20G / 200G-gate structure;

[0041] 20S / 200S-source region;

[0042] 20D / 200D-drain area;

[0043] 310-field dielectric layer;

[0044] 320-field plate structure;

[0045] L1 / L2 - depletion lines. DETAILED DESCRIPTION

[0046] As described in the background technology, it is difficult for existing LDMOS devices to simultaneously meet the requirements of low on-resistance and high breakdown voltage, especially the low depletion degree on the surface of the drift region makes the depletion line close to the channel, so that electric field concentration is likely to occur near the channel, increasing the risk of device breakdown.

[0047] For example Figure 1 A LDMOS device shown in FIG. 1 shows a schematic diagram of the structure of a surface depletion line, such as Figure 1 As shown, the LDMOS device generally includes: a drift region 10N and a well region 10P formed in the substrate; a source region 20S formed in the well region 10P and a drain region 20D formed in the drift region 10N; and a gate structure 20G formed on the top surface of the substrate and located between the source region 20S and the drain region 20D. The gate structure 20G partially covers the well region 10P and the drift region 10N at the junction of the well region 10P and the drift region 10N. The portion of the well region 10P covered by the gate structure 20G constitutes the channel region of the device, which is used to form a conductive channel in an inversion state when the device is turned on. Continue to refer to Figure 1 As shown, when the device is in reverse withstand voltage, the depletion layer generated by the well region 10P and the drift region 10N expands from the junction, but since the depletion degree on the surface of the drift region is low and the width of the depletion layer is small, the depletion line L1 is close to the channel region of the device.

[0048] To this end, the present invention provides a method for preparing an LDMOS device, wherein the LDMOS device formed thereby can achieve an enhanced depletion degree on the surface of the drift region, so that the depletion line is away from the vicinity of the channel, thereby reducing the risk of device breakdown. Figure 2 The flowchart of the method for preparing the LDMOS device in one embodiment of the present invention is shown. The method for preparing the LDMOS device includes the following steps.

[0049] Step S100 , providing a substrate, wherein a drift region of a first conductivity type and a well region of a second conductivity type are formed in the substrate.

[0050] Step S200, forming a cover layer on the substrate, the cover layer at least covering a portion of the top surface of the drift region, wherein the cover layer includes a first portion close to the well region and having a gradually changing thickness, and the thickness of the first portion gradually decreases along a direction close to the well region.

[0051] Step S300, performing a second conductivity type ion implantation process to at least allow the second conductivity type ions to pass through the first portion and be implanted into the drift region to form a gradient region, wherein the dose of the second conductivity type ions in the gradient region gradually increases in a direction approaching the well region.

[0052] That is, in the preparation method of the LDMOS device provided by the present invention, the ion implantation process of the second conductivity type is performed under the shielding of the cover layer with a gradual thickness, so that the ion dose implanted on the top surface of the drift region can be distributed in an opposite trend, so as to form a gradual zone with a gradual ion dose on the top surface of the drift region, so that when the device is reversely withstand voltage, the part of the drift region close to the well region can be more easily completely depleted, greatly increasing the width of the depletion layer on the surface of the device, so that the depletion line can be far away from the channel region of the device, reducing the risk of device breakdown. At the same time, it is also conducive to improving the hot carrier injection effect of the device.

[0053] The LDMOS device and the method for preparing the same proposed by the present invention are further described in detail below in conjunction with specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawing, an element described as being "above" another element will now be below the element.

[0054] <Example 1>

[0055] Combination Figure 3-Figure 8 The structural schematic diagram of the LDMOS device in the first embodiment of the present invention during its preparation process is shown to illustrate the preparation method of the LDMOS device in this embodiment.

[0056] In step S100, refer to Figure 3 As shown, a substrate 100 is provided, in which a drift region 100N of a first conductivity type and a well region 100P of a second conductivity type are formed.

[0057] In one example, the substrate 100 may include a second doping type base 110 and a first conductive type epitaxial layer 120 formed on the base 110, and a second conductive type well region 100P is formed in the epitaxial layer 120. At this time, the portion of the device area where the well region 100P is not formed may constitute a first conductive type drift region 100N, and the drift region 100N and the well region 100P have a laterally adjacent interface.

[0058] In another example, the substrate 100 can be a substrate of any conductivity type, and then the first conductivity type ion implantation process and the second conductivity type ion implantation process are performed on the substrate 100 respectively to form a laterally adjacent first conductivity type drift region 100N and a second conductivity type well region 100P.

[0059] The first doping type and the second doping type are opposite doping types, for example, if the first doping type is N-type, the second doping type is P-type; or, if the first doping type is P-type, the second doping type is N-type. In this embodiment, the first doping type is N-type and the second doping type is P-type for explanation.

[0060] In step S200, refer to Figure 3-Figure 5 As shown, a cap layer 200 is formed on the substrate 100, the cap layer 200 at least covers a portion of the top surface of the drift region 100N, and the cap layer 200 includes a first portion close to the well region 100P and having a gradually changing thickness, and the thickness of the first portion gradually decreases along the direction close to the well region 100P. The thickness of the first portion of the cap layer 200, for example, decreases continuously, or may also decrease in a gradient.

[0061] Specifically, in a predetermined area in the drift region 100N away from the well region 100P, a drain region will be formed by an ion implantation process in a subsequent step, and the cap layer 200 at least covers the predetermined area (corresponding to the drain region) in the drift region 100N and extends in the direction of the well region 100P to cover between the well region 100P and the predetermined area. In one example, the first part of the cap layer 200 is the part covering between the well region 100P and the predetermined area (corresponding to the drain region), that is, the part of the cap layer 200 covering between the well region 100P and the predetermined area constitutes the first part; in another example, the first part of the cap layer 200 covers the part between the well region 100P and the predetermined area, and further extends to cover the predetermined area, that is, the thickness of the cap layer 200 gradually decreases from the predetermined area to the direction of the well region 100P.

[0062] In this embodiment, the first part of the cover layer 200 covers the predetermined area and further extends to cover the boundary of the well region 100P. Figure 5As shown, the thickness of the cap layer 200 gradually decreases from the predetermined area to the well region 100P, and the thickness of the first portion of the cap layer 200 continuously decreases to have an inclined surface. It should be recognized that in other examples, the thickness of the first portion of the cap layer 200 can also decrease gradually to have a stepped surface.

[0063] Combine the following Figure 3-Figure 5 , a method for preparing the covering layer 200 is illustrated by way of example, which specifically includes the following steps.

[0064] First reference Figure 3 As shown, a photoresist material 200 a is coated on the top surface of the substrate 100 .

[0065] Next reference Figure 4 As shown, a photolithography process is performed to form a patterned photoresist layer 200b. Specifically, an exposure process is performed to define the pattern of the photoresist layer in the photoresist material 200a, and then the unnecessary photoresist material is removed by a development process to form a patterned photoresist layer 200b. The patterned photoresist layer 200b may have a relatively flat edge, and the patterned photoresist layer 200b covers a portion of the drift region 100N, so that the patterned photoresist layer 200b is close to the edge of the well region 100P and is spaced from the well region 100P.

[0066] Next reference Figure 5 As shown, the photoresist material is baked to reduce the viscosity and enhance the fluidity, so that the edge of the photoresist layer 200b collapses during the baking process, and then flows and extends toward the well region 100P to form an inclined portion with a gradually decreasing thickness. At the same time, as the baking proceeds, the photoresist layer can be further solidified. The photoresist layer thus formed can constitute the desired cover layer 200, and the inclined portion in the photoresist layer constitutes the first portion with a gradual thickness change.

[0067] It should be noted that in Figure 3-Figure 5 In the example of , by adjusting the baking parameters, the edge of the photoresist layer flows and extends toward the well region 100P, thereby forming an inclined portion with a gradually decreasing thickness. However, in other examples, the thickness of the cover layer 200 can also be adjusted in combination with the etching process to obtain the first portion with a gradual thickness change.

[0068] In step S300, refer to Figure 6 As shown, a second conductivity type ion implantation process is performed to allow at least the second conductivity type ions to pass through the first portion of the cap layer 200 and be implanted into the drift region 100N, and the ion dose implanted below the first portion gradually increases in a direction approaching the well region 100P.

[0069] Specifically, since the thickness of the portion of the cover layer 200 that is closer to the well region 100P is smaller, ions can be injected into the drift region 100N in a larger dose under the same power and energy; and the thickness of the cover layer 200 that is farther away from the well region 100P is larger, it is more difficult for ions to be injected into the drift region 100N under the same power and energy. In this way, an ion dose with a trend opposite to that of the thickness change of the cover layer 200 can be injected into the drift region 100N.

[0070] Exemplarily, through the ion implantation process in this step, a gradient region 110N with a gradient ion dose can be formed in the top surface area of ​​the drift region 100N. For example, the depth of the second conductive type ions implanted into the drift region 100N gradually increases along the direction close to the well region 100P, that is, the depth of the gradient region 110N gradually increases along the direction close to the well region 100P; and / or, the concentration of the second conductive type ions implanted into the drift region 100N gradually increases along the direction close to the well region 100P, that is, the concentration of the second conductive type ions in the gradient region 110N gradually increases along the direction close to the well region 100P.

[0071] Furthermore, the ion implantation dose of the ion implantation process in this step is small, so that the area in the drift region 100N where the ions of the second conductivity type are implanted still presents the first conductivity type, that is, the amount of ions of the first conductivity type in the gradient region 110N is greater than the amount of ions of the second conductivity type, so that the gradient region 110N as a whole still presents the first conductivity type. For example, the top surface of the N-type drift region 100N is implanted with P-type ions, the dose of the P-type ions gradually decreases in the direction away from the well region 100P, and the gradient region 110N implanted with P-type ions still presents the N-type as a whole.

[0072] Continue to refer Figure 6 As shown, the cover layer 200 in this embodiment does not cover the well region 100P, so during the ion implantation process, ions of the second conductivity type can also be implanted into the well region 100P. It should be recognized that in other examples, the cover layer can further cover the well region 100P to block the ions in this step from being implanted into the well region 100P. For example, the cover layer also includes a third portion with a constant thickness relative to the first portion, and the third portion covers the top surface of the well region 100P, wherein the third portion can be made of a material different from that of the first portion, for example, the third portion can be a silicon oxide layer, a silicon nitride layer, etc., and the first portion can be made of a photoresist material and a baking process can be used to allow the first portion to autonomously form a thickness gradient effect.

[0073] Afterwards, the process further includes forming a source region, a drain region and a gate structure on the substrate 100 , for details, please refer to step S400 .

[0074] In step S400, refer to Figure 7 As shown, a source region 200S, a drain region 200D and a gate structure 200G are formed.

[0075] The source region 200S is formed in the well region 100P, the drain region 200D is formed in a predetermined region of the drift region 100N, and the gradient region 110N is located between the drain region 200D and the well region 100P. In addition, the gate structure 200G is located between the source region 200S and the drain region 200D, and the gate structure 20G partially covers the well region 100P and the drift region 100N at the junction of the well region 100P and the drift region 100N. The portion of the well region 100P covered by the gate structure 200G constitutes the channel region of the device, which is used to form a conductive channel in an inversion state when the device is turned on.

[0076] In a further solution, a field plate structure may be formed on the substrate 100. For details, please refer to Figure 8 As shown, the present invention further includes: forming a field dielectric layer 310 on the substrate 100, the field dielectric layer 310 partially covering the gate structure 200G and extending toward the drain region 200D to cover the top surface of the substrate; and forming a field plate structure 320 on the field dielectric layer 310. By providing the field plate structure 320, the breakdown voltage of the device can be further improved.

[0077] The LDMOS device formed by the preparation method described above can effectively improve the width of the surface depletion layer of the device and improve the withstand voltage performance of the device. Fig. 9 As shown, the gradient region 110N in the top surface of the drift region 100N is closer to the channel region of the device, and the ion dose of the second conductivity type in the gradient region 110N closer to the channel region is higher. It can be considered that the gradient region 110N closer to the channel region is generally of the first conductivity type and has a lower ion concentration. Therefore, when the device is reversely withstand voltage, the presence of the gradient region 110N makes it easier for the portion of the drift region 100N close to the channel region to be completely depleted, and the depletion layer generated by the drift region 100N and the well region 100P can be extended to a wider distance, for example, it can be extended to the edge of the gradient region 110N away from the well region 100P, greatly increasing the width of the depletion layer on the surface of the device, and making the depletion line L2 away from the channel region of the device, reducing the risk of device breakdown. In addition, due to the expansion of the width of the depletion layer, the depletion line L2 is away from the channel region, avoiding the problem of hot carrier injection (HCI) caused by the high concentration of carriers gathering near the channel.

[0078] <Example 2>

[0079] The difference from the first embodiment is that the cover layer in this embodiment further includes a second portion with a constant thickness relative to the first portion, the second portion connects to a side of the first portion away from the well region and covers a predetermined area in the drift region for forming a drain region.

[0080] Specific reference Fig.10 As shown, the capping layer 200 in this embodiment includes a first portion 210 with a gradually changing thickness and a second portion 220 with a constant thickness. The first portion 210 is close to the well region 100P and its thickness gradually decreases along the direction close to the well region 210; the second portion 220 is connected to the side of the first portion 210 away from the well region 100P, and the second portion 220 can specifically cover a predetermined area in the drift region 100N for forming a drain region.

[0081] Furthermore, the thickness of the second portion 220 is equal to the maximum thickness of the first portion 210. Fig.10 As shown, the thickness of the first portion 210 gradually increases in the direction close to the second portion 220, and reaches the maximum thickness at the position connected to the second portion 220, so that the maximum thickness of the first portion 210 is consistent with the thickness of the second portion 220. Exemplarily, the second portion 220 can also effectively block the ions of the second conductivity type in the ion implantation process of step S300, so that the ions of the second conductivity type are difficult to be implanted into the drift region below the second portion 220.

[0082] Specific combination Fig.10 As shown, in the second conductive type ion implantation process in step S300, for example, the second conductive type ions can only pass through the first part 210, thereby forming a gradient region 110N below the first part 210, while no second conductive type ions are implanted in the drift region below the second part 220.

[0083] <Example 3>

[0084] Different from the first embodiment, there is a gap between the cover layer and the well region in this embodiment, that is, the top surface between the cover layer and the well region is exposed.

[0085] Specific reference Fig.11 As shown, the edge of the cap layer 200 in this embodiment does not reach the boundary of the well region 100P, so that the portion of the drift region 110 close to the well region 100PD is exposed. Based on this, when performing the second conductivity type ion implantation process in step S300, the ion dose implanted into the exposed drift region 100N can be higher than the ion dose implanted under the cap layer 200.

[0086] The present disclosure also provides an LDMOS device, which is formed in the direction as described above. Fig. 9 As shown, the LDMOS device includes a substrate 100 in which a drift region 100N of a first conductivity type and a well region 100P of a second conductivity type are formed.

[0087] Furthermore, a first conductive type gradient region 110N is formed in the drift region 100N, and the gradient region 110N also has ions of the second conductive type, and the dose of the second conductive type ions in the gradient region 110N gradually increases along the direction close to the well region 100P. It can be considered that the gradient region 110N has ions of the first conductive type and ions of the second conductive type, and the amount of ions of the first conductive type is greater than the amount of ions of the second conductive type, so that the gradient region 110N as a whole still presents the first conductive type.

[0088] For example, the LDMOS device has an N-type drift region 100N and a P-type well region 100P. An N-type gradient region 110N is formed in the N-type drift region 100N, and the overall N-type ion doping concentration of the N-type gradient region 110N is lower than the N-type ion doping concentration in the drift region 100N. Specifically, the N-type gradient region 110N contains both N-type ions and P-type ions, and the ion amount of the N-type ions in the N-type gradient region 110N is greater than the ion amount of the P-type ions. It can be considered that the N-type gradient region 110N described here is a region in which the dose of the P-type ions gradually decreases along the direction close to the well region 100P; it can also be considered that the N-type gradient region 110N is a region in which the overall N-type doping concentration gradually decreases along the direction close to the well region 100P.

[0089] In a specific example, the depth of the second conductive type ions in the gradient region 110N may gradually increase along the direction approaching the well region 100P; and / or the concentration of the second conductive type ions in the gradient region 110N may gradually increase along the direction approaching the well region 100P.

[0090] Continue to refer Fig. 9 As shown, the LDMOS device further includes: a gate structure 200G, a source region 200S and a drain region 200D. The gate structure 200G is formed on the substrate 100, and partially covers the well region 100P and extends to cover the adjacent drift region 100N. The source region 200S is formed in the well region 100P, the drain region 200D is formed in the drift region 100N, and the gradient region 110N is located between the drain region 200D and the well region 100P.

[0091] The LDMOS device formed based on the preparation method as described above, by setting the gradient region 110N in the top surface area of ​​the drift region 100N, can not only achieve the effect of increasing the depletion layer width, greatly improving the breakdown voltage of the device, but also effectively improve the hot carrier injection effect of the device, further improving the device performance.

[0092] It should be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

[0093] It must be noted that as used herein and in the appended claims, the singular forms "a," "an," and "an" include plural references unless the context clearly indicates otherwise. For example, reference to "a step" or "a device" means reference to one or more steps or devices and may include secondary steps as well as secondary devices. All conjunctions used should be interpreted in the broadest sense. Also, the word "or" should be interpreted as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise.

Claims

1. A method for preparing an LDMOS device, characterized in that: include: Providing a substrate, in which a drift region of a first conductivity type and a well region of a second conductivity type are formed; forming a cover layer on the substrate, the cover layer at least covering a portion of the top surface of the drift region, wherein the cover layer comprises a first portion close to the well region and having a gradually changing thickness, and the thickness of the first portion gradually decreases along a direction close to the well region; as well as, An ion implantation process of the second conductivity type is performed to at least allow ions of the second conductivity type to pass through the first portion and be implanted into the drift region to form a gradient region, wherein the dose of the ions of the second conductivity type in the gradient region gradually increases in a direction approaching the well region.

2. The method for preparing an LDMOS device according to claim 1, wherein: The method for preparing the covering layer comprises: coating a photoresist material on the substrate; Performing a photolithography process to form a patterned photoresist layer, wherein the photoresist layer covers a portion of the drift region and is spaced from the well region near an edge of the well region; and, A baking process is performed, and the edge of the photoresist layer collapses during the baking process and extends toward the well region to form an inclined portion with a gradually decreasing thickness, so as to form the cover layer having the first portion.

3. The method for preparing an LDMOS device according to claim 1, wherein: The amount of ions of the first conductivity type in the gradient region is greater than the amount of ions of the second conductivity type, so that the gradient region appears as a doped region of the first conductivity type.

4. The method for preparing an LDMOS device according to claim 1, wherein: The depth of the second conductive type ions in the gradient region gradually increases along a direction approaching the well region; and / or the concentration of the second conductive type ions in the gradient region gradually increases along a direction approaching the well region.

5. The method for preparing an LDMOS device according to claim 1, wherein: The thickness of the first portion decreases continuously along a direction approaching the well region; or the thickness of the first portion decreases gradually along a direction approaching the well region.

6. The method for preparing an LDMOS device according to claim 1, wherein: The capping layer further includes a second portion with a constant thickness relative to the first portion, the second portion connecting a side of the first portion away from the well region and covering a predetermined region in the drift region for forming a drain region.

7. The method for preparing an LDMOS device according to claim 1, wherein: The covering layer further exposes the well region; or, the covering layer further includes a third portion having a constant thickness relative to the first portion, and the third portion covers the well region.

8. The method for preparing an LDMOS device according to claim 1, wherein: The cover layer is disposed close to the edge of the well region and spaced apart from the well region, so that a portion of the drift region close to the well region is exposed.

9. The method for preparing an LDMOS device according to claim 1, wherein: The preparation method further comprises: forming a gate structure on the substrate, the gate structure partially covering the well region and extending to cover an adjacent drift region; and, A source region and a drain region are formed, wherein the source region is formed in the well region, the drain region is formed in the drift region, and the gradient region is located between the drain region and the well region.

10. An LDMOS device, characterized in that: include: A substrate having a drift region of a first conductivity type and a well region of a second conductivity type formed therein; A gradient region of the first conductivity type is formed in the drift region. The gradient region also contains ions of the second conductivity type, and the dosage of the ions of the second conductivity type gradually increases along a direction approaching the well region.

11. The LDMOS device according to claim 10, characterized in that: The depth of the second conductive type ions in the gradient region gradually increases along a direction approaching the well region; and / or the concentration of the second conductive type ions in the gradient region gradually increases along a direction approaching the well region.

12. The LDMOS device according to claim 10, wherein: Also includes: a gate structure, the gate structure partially covering the well region and extending to cover an adjacent drift region; A source region and a drain region, wherein the source region is formed in the well region, the drain region is formed in the drift region, and the gradient region is located between the drain region and the well region.

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