Power semiconductor device and preparation method thereof
By introducing the septum layer in the crystal of high electron migration rate of nitride, improved its critical electric field and energy gap, solved the problem of the peak electric field when the device was compressed when the grid was pressed, and achieved higher breakdown voltage and reliable reliability and reliable reliability. sex.
Patent Information
- Application Number
- CN202411275377.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-12
- Publication Date
- 2025-01-28
AI Technical Summary
The existing gallium nitride high electron mobility transistors are prone to form a spike electric field when the gate is forwardly compressed, resulting in a low gate breakdown voltage of the device and insufficient reliability.
Set the partition layer above the P -type cover layer. The critical electric field and the band gap of the partition layer are greater than the P -type cover layer. Once or multi -lapse of the light hood is performed to ensure the boundary between the partition and the grid metal layer. Location.
The grid breakdown and reliability of the device is improved, the leakage current is reduced, and the performance of the device at high temperature reverse bias.
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Figure CN119384001A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a power semiconductor device, in particular to a power semiconductor device and a preparation method thereof. Background Art
[0002] Gallium nitride high electron mobility transistor is a common power device and is widely used in high-frequency applications such as RF and microwave. Compared with silicon materials, it has a larger band gap, higher electron mobility, saturation electron velocity and breakdown electric field.
[0003] Figure 1 The figure shows an existing GaN high electron mobility transistor structure. In order to reduce the chance of the enhancement mode device being turned on by mistake, the threshold voltage needs to reach a sufficiently high value. In order to achieve a higher threshold voltage, the P-type cap layer 104 generally requires a higher doping concentration to enhance the ability to deplete the two-dimensional electron gas located below it. However, when the gate is positively pressurized, the P-type cap layer 104 with a higher doping concentration forms a shallower depletion region on its surface, and the electric field formed is also higher; in addition, due to the edge effect of the electric field, a peak electric field will be formed at the corner position 110 on the surface of the P-type cap layer 104 below the gate metal layer 106. When the above-mentioned peak electric field reaches the critical electric field of the P-type cap layer 104, the gate of the device will be broken down. Summary of the invention
[0004] In order to overcome the above-mentioned problems, the present invention provides a power semiconductor device, the device includes a substrate layer located at the bottom, a buffer layer located above the substrate layer, a channel layer located above the buffer layer, a barrier layer located above the channel layer, a P-type cap layer located above the barrier layer, a gate metal layer located above the P-type cap layer and the separation layer, a source metal layer located on one side of the gate metal layer and a drain metal layer on the other side, the channel layer and the barrier layer form a heterojunction and form a two-dimensional electron gas on the surface of the channel layer below the heterojunction, the P-type cap layer depletes the two-dimensional electron gas on the surface of the channel layer below it when the device is turned off to form an enhanced device, the P-type cap layer forms a Schottky contact with the gate metal layer above it, and separation layers are provided at the edge positions on both sides above the P-type cap layer, the critical electric field of the separation layer is greater than the critical electric field of the P-type cap layer below it, and the energy band gap of the separation layer is greater than the energy band gap of the P-type cap layer.
[0005] Furthermore, the material constituting the separation layer is one or more of gallium oxide, gallium oxynitride or aluminum nitride.
[0006] Furthermore, the boundaries of the separation layer and the gate metal layer on both sides are the same, and the boundaries are within the P-type cap layer.
[0007] Furthermore, the gate metal layer and the separation layer are formed by photolithography at one time using the same photomask, and the P-type cap layer is formed by photolithography using an independent photomask.
[0008] Furthermore, the boundaries of the separation layer and the P-type cap layer on both sides are the same, and the boundary of the gate metal layer is within the separation layer.
[0009] Furthermore, the separation layer and the P-type cap layer are formed by photolithography at one time using the same photomask, and the gate metal layer is formed by photolithography using an independent photomask.
[0010] Furthermore, the width of the separation layer on the side close to the drain metal layer is greater than the width of the separation layer on the side close to the source metal layer.
[0011] The present invention also provides a method for preparing a power semiconductor device, the method comprising the following steps: In the first step, a buffer layer is formed on the substrate layer, a channel layer is formed on the buffer layer, and then a barrier layer is formed on the channel layer; The second step is to form a preliminary P-type cap layer on the barrier layer, and then form a preliminary separation layer on the preliminary P-type cap layer; The third step is to etch the surface of the preliminary separation layer to form a patterned second-step separation layer; Step 4, forming a preliminary gate metal layer on the surface of the second-step separation layer; Step 5, etching the preliminary gate metal layer, the second-step separation layer and the preliminary P-type cap layer to form a patterned gate metal layer, a patterned separation layer and a patterned P-type cap layer respectively; In the sixth step, a source metal layer is formed on the left side of the gate metal layer and a drain metal layer is formed on the right side of the gate metal layer.
[0012] The present invention provides a separation layer at both side edge positions above the P-type cap layer below the gate metal layer. The separation layer is composed of a material or a combination thereof whose energy band gap is greater than the energy band gap of the P-type cap layer, and the critical electric field of the separation layer is greater than the critical electric field of the P-type cap layer. When the gate is positively pressurized, a peak electric field is formed at the corner position of the surface of the separation layer below the gate metal layer. Since the critical electric field of the separation layer is greater than the critical electric field of the P-type cap layer, the gate breakdown voltage and reliability of the device are improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 It is a cross-sectional schematic diagram of an existing high electron mobility transistor structure.
[0014] Figure 2 FIG. 4 is a cross-sectional schematic diagram of a device structure according to an embodiment of the present invention.
[0015] Figure 3 FIG. 4 is a cross-sectional schematic diagram of a device structure according to another embodiment of the present invention.
[0016] Figure 4 FIG. 4 is a cross-sectional schematic diagram of a device structure according to another embodiment of the present invention.
[0017] Figure 5 FIG. 4 is a cross-sectional schematic diagram of a device structure according to another embodiment of the present invention.
[0018] Figure 6-Figure 11 The present invention is an embodiment of a method for manufacturing a device structure. DETAILED DESCRIPTION
[0019] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that the corresponding position words such as "upper", "lower", "left", "right", "front", "back", "vertical", and "horizontal" described in this document correspond to the relative positions of the reference diagrams, and are not limited to fixed directions in specific implementations. The devices in the accompanying drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and trenches in the accompanying drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.
[0020] Example 1 Reference Figure 2 2a is a cross-sectional schematic diagram of the device structure of the first embodiment of the present invention, and the structure includes: a substrate layer 200 at the bottom; a buffer layer 201 above the substrate layer 200; a channel layer 202 above the buffer layer 201; a barrier layer 203 above the channel layer 202; a P-type cap layer 104 above the barrier layer 203; a separation layer 205 at both side edge positions above the P-type cap layer 104; a gate metal layer 106 above the P-type cap layer 104 and the separation layer 205; and a source metal layer 207 on the left of the gate metal layer 106 and a drain metal layer 208 on the right.
[0021] In the above structure, the channel layer 202 and the barrier layer 203 form a heterojunction, and a two-dimensional electron gas (2DEG) is formed on the surface of the channel layer 202 located below the heterojunction, forming a current channel between the source metal layer 207 and the drain metal layer 208 when the device is turned on.
[0022] In the above structure, the P-type cap layer 104 depletes the two-dimensional electron gas on the surface of the channel layer 202 located thereunder when the device is turned off, thereby forming an enhancement-mode device.
[0023] In the above structure, the P-type cap layer 104 forms a Schottky contact with the gate metal layer 106 located thereon, so as to reduce the gate current when the gate is subjected to a positive pressure.
[0024] In the above structure, the doping material of the P-type cap layer 104 includes magnesium (Mg) or other suitable P-type doping elements.
[0025] In the above structure, the critical electric field of the spacer layer 205 is greater than the critical electric field of the P-type cap layer 104 located therebelow. When the gate is positively pressed, a peak electric field is formed at the corner positions 210 on both sides of the surface of the spacer layer 205 below the gate metal layer 106. Since the critical electric field of the spacer layer 205 is greater than the critical electric field of the P-type cap layer 104, the gate breakdown voltage of the device will be increased.
[0026] In the above structure, the spacer layer 205 may include materials having a larger energy band gap than the P-type cap layer 104 , such as gallium oxide (GaO), gallium oxynitride (GaON), aluminum nitride (AlN), or a combination thereof.
[0027] Example 2 A variation of the device embodiment of the present invention is as follows Figure 3 As shown, and Figure 2 The embodiment is different in that the gate metal layer 106 and the spacer layer 205 have the same width and are smaller than the width of the P-type cap layer 104. The gate metal layer 106 and the spacer layer 205 are formed by one photolithography using the same mask, while the P-type cap layer 104 is formed by photolithography using an independent mask.
[0028] In the above structure, the sidewall of the P-type cap layer 104 is formed by etching, and there are many defects on the surface of the wall. Since the width of the gate metal layer 106 and the separation layer 205 is smaller than the width of the P-type cap layer 104, the peak electric field at the corners on both sides of the surface of the separation layer 205 below the gate metal layer 106 is far away from the defects of the sidewall of the P-type cap layer 104. Therefore, the gate leakage current of the device is small and the gate breakdown voltage is high.
[0029] Example 3 A variation of the device embodiment of the present invention is as follows Figure 4 As shown, and Figure 3 The difference between the embodiments is that the width of the spacer layer 205 and the P-type cap layer 104 is the same and larger than the width of the gate metal layer 106. The spacer layer 205 and the P-type cap layer 104 are formed by one photolithography using the same mask, while the gate metal layer 106 is formed by photolithography using an independent mask.
[0030] Figure 3 In the embodiment, the P-type cap layer 104 serves as an etching stop layer for the separation layer 205 . After the separation layer 205 is etched, defects are formed on the surface of the P-type cap layer 104 . Figure 4In the embodiment, the spacer layer 205 becomes an etching stop layer for the gate metal layer 106. After the etching of the gate metal layer 106 is completed, defects will be formed on the surface of the spacer layer 205. Since the etching selectivity between the spacer layer 205 and the gate metal layer 106 is better than the etching selectivity between the P-type cap layer 104 and the spacer layer 205, fewer defects will be formed on the surface of the spacer layer 205 after the etching of the gate metal layer 106 is completed. Figure 3 Comparison of Examples Figure 4 The gate leakage current of the embodiment is smaller and the gate breakdown voltage is higher.
[0031] Example 4 A variation of the device embodiment of the present invention is as follows Figure 5 As shown, and Figure 4 The difference between the embodiments is that the widths of the left and right parts of the spacer layer 205 are different. Generally, the width d1 of the right part of the spacer layer 205 close to the drain metal layer 208 is larger than the width d2 of the left part of the spacer layer 205 close to the source metal layer 207. When the gate is positively pressed, the distance between the peak electric field on the surface of the spacer layer 205 under the gate metal layer 106 and the defect on the side wall of the P-type cap layer 104 is larger, which reduces the drain-gate leakage current and improves the reliability performance of the device under high temperature reverse bias (HTRB).
[0032] Those skilled in the art should know that the structural features mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more device structures of the embodiments of the present invention.
[0033] Example 5 According to the structural features of the above-mentioned embodiments of the present invention, combined with the existing GaN high electron mobility transistor manufacturing process, a variety of methods for forming the device embodiments of the present invention can be obtained. An exemplary method for forming the device embodiment of the present invention is as follows: Figure 6-Figure 11 Shown: In the first step, a buffer layer 201 is formed on the substrate layer 200, a channel layer 202 is formed on the buffer layer 201, and a barrier layer 203 is formed on the channel layer 202. Figure 6 shown.
[0034] The material of the substrate layer 200 is usually silicon (Si), and may also be other suitable materials such as gallium nitride (GaN), silicon carbide (SiC), and sapphire.
[0035] The buffer layer 201 may include one material or a combination of multiple materials such as aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium nitride (GaN), etc. The one material or the combination of multiple materials may include doping elements such as carbon (C) and iron (Fe), which is beneficial to reduce leakage current.
[0036] The material of the channel layer 202 is usually gallium nitride (GaN), but may also be other materials, and the energy band gap of the channel layer 202 is smaller than the energy band gap of the material of the barrier layer 203 located thereon.
[0037] The material of the barrier layer 203 is usually aluminum gallium nitride (AlGaN), but may also be other materials, and the energy band gap of the barrier layer 203 is larger than the energy band gap of the material of the channel layer 202 located therebelow.
[0038] The above structure can be formed by chemical vapor deposition, physical vapor deposition, epitaxial growth and other processes.
[0039] In the second step, a preliminary P-type cap layer 194 is formed on the barrier layer 203, and a preliminary separation layer 295 is formed on the preliminary P-type cap layer 194. Figure 7 shown.
[0040] The material of the preliminary P-type cap layer 194 is usually doped gallium nitride (GaN), and may also be doped aluminum gallium nitride (AlGaN) or other materials. The doped material contains magnesium (Mg) or other suitable P-type doping elements.
[0041] The preliminary spacer layer 295 may include materials having an energy band gap greater than the energy band gap of the preliminary P-type cap layer 194 , such as gallium oxide (GaO), gallium oxynitride (GaON), aluminum nitride (AlN), or a combination thereof.
[0042] The above structure can be formed by chemical vapor deposition, physical vapor deposition, epitaxial growth and other processes.
[0043] In the third step, photolithography, dry etching, wet etching and other process steps are performed on the surface of the preliminary separation layer 295 to form a patterned two-step separation layer 285, such as Figure 8 shown.
[0044] In the fourth step, a preliminary gate metal layer 196 is formed on the surface of the second-step separation layer 285, such as Fig. 9 shown.
[0045] The preliminary gate metal layer 196 may be formed by evaporation, sputtering and other processes, and its constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds or other appropriate materials.
[0046] Typically, the preliminary gate metal layer 196 forms a Schottky contact with the preliminary P-type cap layer 194 thereunder.
[0047] In the fifth step, the preliminary gate metal layer 196, the second-step separation layer 285 and the preliminary P-type cap layer 194 are subjected to photolithography, dry etching, wet etching and other process steps to form a patterned gate metal layer 106, a patterned separation layer 205 and a patterned P-type cap layer 104, respectively. Fig.10 shown.
[0048] In the sixth step, a source metal layer 207 is formed on the left side of the gate metal layer 106 and a drain metal layer 208 is formed on the right side thereof. Fig.11 shown.
[0049] The source metal layer 207 and the drain metal layer 208 may be formed by evaporation, sputtering and other processes, and their constituent materials may include but are not limited to metals such as titanium (Ti), nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), gold (Au), their alloys, their compounds or other appropriate materials.
[0050] The method of forming the patterned source metal layer 207 and the drain metal layer 208 may include photolithography, dry etching, wet etching and other process steps.
[0051] Typically, the source metal layer 207 and the drain metal layer 208 form ohmic contacts with the channel layer 202 thereunder.
[0052] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.
Claims
1. A power semiconductor device, comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, a P-type cap layer above the barrier layer, a gate metal layer above the P-type cap layer and the separation layer, a source metal layer on one side of the gate metal layer and a drain metal layer on the other side, wherein the channel layer and the barrier layer form a heterojunction and a two-dimensional electron gas is formed on the surface of the channel layer below the heterojunction, characterized in that: When the device is turned off, the P-type cap layer depletes the two-dimensional electron gas on the surface of the channel layer below it to form an enhanced device. The P-type cap layer forms a Schottky contact with the gate metal layer above it. Separation layers are provided at the edge positions on both sides above the P-type cap layer. The critical electric field of the separation layer is greater than the critical electric field of the P-type cap layer below it, and the energy band gap of the separation layer is greater than the energy band gap of the P-type cap layer.
2. The power semiconductor device according to claim 1, characterized in that: The material constituting the separation layer is one or more of gallium oxide, gallium oxynitride or aluminum nitride.
3. The power semiconductor device according to claim 1, characterized in that: The boundaries of the separation layer and the gate metal layer on both sides are the same, and the boundaries are within the P-type cap layer.
4. The power semiconductor device according to claim 3, characterized in that: The gate metal layer and the separation layer are formed by photolithography at one time using the same photomask, and the P-type cap layer is formed by photolithography using an independent photomask.
5. The power semiconductor device according to claim 1, characterized in that: The boundaries of the separation layer and the P-type cap layer on both sides are the same, and the boundary of the gate metal layer is within the separation layer.
6. The power semiconductor device according to claim 5, characterized in that: The separation layer and the P-type cap layer are formed by photolithography at one time using the same photomask, and the gate metal layer is formed by photolithography using an independent photomask.
7. The power semiconductor device according to claim 5, characterized in that: The width of the separation layer on the side close to the drain metal layer is greater than the width of the separation layer on the side close to the source metal layer.
8. The method for preparing a power semiconductor device according to any one of claims 1 to 7, characterized in that: The preparation method comprises the following steps: In the first step, a buffer layer is formed on the substrate layer, a channel layer is formed on the buffer layer, and then a barrier layer is formed on the channel layer; The second step is to form a preliminary P-type cap layer on the barrier layer, and then form a preliminary separation layer on the preliminary P-type cap layer; The third step is to etch the surface of the preliminary separation layer to form a patterned second-step separation layer; Step 4, forming a preliminary gate metal layer on the surface of the second-step separation layer; Step 5, etching the preliminary gate metal layer, the second-step separation layer and the preliminary P-type cap layer to form a patterned gate metal layer, a patterned separation layer and a patterned P-type cap layer respectively; In the sixth step, a source metal layer is formed on one side of the gate metal layer and a drain metal layer is formed on the other side.