Power semiconductor device layout

Abstract

The invention discloses a power semiconductor device which comprises a plurality of cells, and each cell comprises a substrate layer, an epitaxial layer, a well region, a source region and a well contact region. The well region is distributed in the epitaxial layer, and the strip-shaped epitaxial platform region surrounds the upper surface of the epitaxial layer in a square ring shape. The source region is distributed in the well region, is in a square ring shape on the upper surface of the epitaxial layer and is distributed along the outer contour of the well region, and a certain distance is formed between the inner contour of the source region and the inner contour of the well region. The well contact region is distributed in the source region and located at at least one end of the epitaxial platform region in the first direction. Wherein the first direction is parallel to the upper surface of the epitaxial layer and is the length direction of the epitaxial platform region. According to the invention, the well contact regions are arranged at the two ends of a part of the strip-shaped cells in the length direction, so that the cell size of the device is reduced, and the on resistance of the device can be further reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a layout and structure of a power semiconductor device. Background Art

[0002] Figure 1 FIG. 1 shows a cross-sectional view of a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device 100. Figure 1 As shown, the MOSFET device 100 includes a semiconductor layer 111, and a gate structure 112 located on the semiconductor layer 111. The gate structure 112 includes a polysilicon gate 112a and an insulating layer 112b that wraps the polysilicon gate 112a. The semiconductor layer 111 includes a substrate layer 101, an epitaxial layer 102 located on the substrate layer 101, a well region 103 located in the epitaxial layer 102, and an adjacent source region 104 and a well contact region 105 located in the well region 103. At the same time, the lower surface of the semiconductor layer 111, that is, the surface of the substrate layer 101 of the device, is covered with a metal layer as a drain electrode 106, and the upper surface of the semiconductor layer 111, that is, the exposed surface of the source region 104, is covered with a metal layer as a source electrode 107. In the MOSFET device 100, as shown in FIG. Figure 1 As shown in FIG. 1 , the size of the cell on the cross section is L=Lohmic+2Lgs+2Loverlap+2Lch+Ljfet. Currently, the length of each part has reached the limit of the current process capability, and it is difficult to further reduce the cell size of the device, resulting in the device's on-resistance cannot be further reduced. Summary of the invention

[0003] The present application provides a power semiconductor device, which places well contact regions at both end regions of a strip-shaped cell, thereby reducing the cell size of the device, thereby further reducing the on-resistance of the device.

[0004] According to one embodiment of the present application, a power semiconductor device is provided, comprising a plurality of first cells, wherein each of the first cells comprises: a substrate layer; an epitaxial layer, having an epitaxial layer upper surface and an epitaxial layer lower surface, wherein the epitaxial layer lower surface is connected to the substrate layer; a well region, distributed in the epitaxial layer, and in the form of a square ring surrounding a strip-shaped epitaxial platform region on the epitaxial layer upper surface; a source region, distributed in the well region, and in the form of a square ring along the outer contour of the well region on the epitaxial layer upper surface, with a certain distance between the inner contour of the source region and the inner contour of the well region; and a well contact region, distributed in the source region, and located at least at one end of the epitaxial platform region in a first direction; wherein the first direction is parallel to the epitaxial layer upper surface, and is the length direction of the epitaxial platform region.

[0005] In one embodiment, each first cell of the aforementioned power semiconductor device includes two well contact regions, which are respectively distributed at two ends of the epitaxial platform region in the first direction.

[0006] In one embodiment, the distance between the two well contact regions of the power semiconductor device is greater than 1.2 μm.

[0007] In one embodiment, the power semiconductor device comprises at least two first cells, whose central axes coincide with each other in a second direction, and the second direction is parallel to the upper surface of the epitaxial layer and perpendicular to the first direction.

[0008] In one embodiment, the well contact regions of at least two first cells of the power semiconductor device located on the same side extend in the second direction and are connected into a whole.

[0009] In one embodiment, the power semiconductor device comprises at least two first cells arranged adjacent to each other in a second direction, wherein the central axes of the adjacent first cells in the second direction do not overlap, and the second direction is equal to the upper surface of the epitaxial layer and perpendicular to the first direction.

[0010] In one embodiment, the aforementioned power semiconductor device also includes a second cell, which shares a substrate layer and an epitaxial layer with the first cell, and the second cell includes on the upper surface of the epitaxial layer: an epitaxial platform region, which is distributed in the form of strips along the first direction; a well region, which is distributed in the form of strips on both sides of the epitaxial platform region along the first direction; and a source region, which is distributed in the form of strips in the well region along the first direction, and there is a gap between the side wall of the source region along the first direction and the side wall of the epitaxial platform region on the same side; wherein, in a second direction parallel to the upper surface of the epitaxial layer and perpendicular to the first direction, the first cell and the second cell are arranged at intervals, and adjacent source regions of adjacent first cells and second cells are connected.

[0011] In one embodiment, the aforementioned power semiconductor device also includes a second cell, which shares a substrate layer and an epitaxial layer with the first cell, and the second cell includes on the upper surface of the epitaxial layer: an epitaxial platform region, which is distributed in the form of strips along the first direction; a well region, which is distributed in the form of strips on both sides of the epitaxial platform region along the first direction; and a source region, which is distributed in the form of strips in the well region along the first direction, and there is a gap between the side wall of the source region along the first direction and the side wall of the epitaxial platform region on the same side; wherein, in a second direction parallel to the upper surface of the epitaxial layer and perpendicular to the first direction, a plurality of first cells are arranged between every two second cells, and adjacent source regions of adjacent first cells and second cells are connected, and adjacent source regions of adjacent first cells are connected.

[0012] In one embodiment, the well contact regions of the plurality of first cells between the two second cells of the power semiconductor device located on the same side extend in the second direction and are connected into a whole.

[0013] In one embodiment, the power semiconductor device further includes: a source electrode layer connected to the well contact region and a source region around the well contact region. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings:

[0015] Figure 1 A cross-sectional view of a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device 100 is shown;

[0016] Figure 2 is a schematic plan view of a partial region of a power semiconductor device 200 according to an embodiment of the present application;

[0017] Figure 3 According to an embodiment of the present application, Figure 2 A schematic diagram of a first cross section 300 of the power semiconductor device 200 along line AA′ in FIG.

[0018] Figure 4 According to an embodiment of the present application, Figure 2 A schematic diagram of a second cross section 400 of the power semiconductor device 200 along line BB';

[0019] Figure 5 is a schematic plan view of a partial region of a power semiconductor device 500 according to another embodiment of the present application;

[0020] Figure 6 According to an embodiment of the present application, Figure 5 A schematic diagram of a second cross section 600 of the power semiconductor device 500 along line BB';

[0021] Figure 7 is a schematic plan view of a partial region of a power semiconductor device 700 according to an embodiment of the present application;

[0022] Figure 8 According to an embodiment of the present application, Figure 7 A second cross section 800 of the power semiconductor device 700 along line BB';

[0023] Fig. 9is a schematic plan view of a partial region of a power semiconductor device 900 according to an embodiment of the present application;

[0024] Fig.10 According to an embodiment of the present application, Fig. 9 A second cross section 1000 of the power semiconductor device 900 along line BB′;

[0025] Fig.11 is a schematic plan view of a partial region of a power semiconductor device 1100 according to an embodiment of the present application;

[0026] Fig.12 According to an embodiment of the present application, Fig.11 A schematic diagram of a second cross section 1200 of the power semiconductor device 1100 along line BB' in FIG.

[0027] Fig.13 According to an embodiment of the present application, Fig.11 A schematic diagram of a third cross section 1300 of the power semiconductor device 1100 along line EE′ in FIG.

[0028] Fig.14 is a schematic plan view of a partial region of a power semiconductor device 1400 according to an embodiment of the present application;

[0029] Fig.15 According to an embodiment of the present application, Fig.14 A schematic diagram of a second cross section 1500 of the power semiconductor device 1400 along line BB′ in FIG.

[0030] Fig.16 According to an embodiment of the present application, Fig.14 A third cross section 1600 of the power semiconductor device 1400 along line CC′;

[0031] Fig.17 is a schematic plan view of a partial region of a power semiconductor device 1700 according to an embodiment of the present application;

[0032] Fig.18 According to an embodiment of the present application, Fig.17 A schematic diagram of a second cross section 1800 of the power semiconductor device 1700 along line BB' in FIG.

[0033] Fig.19 is a schematic plan view of a partial region of a power semiconductor device 1900 according to an embodiment of the present application;

[0034] Fig. 20 According to an embodiment of the present application, Fig.19 A schematic diagram of a second cross section 2000 of the power semiconductor device 1900 along line BB';

[0035] Fig.21 According to an embodiment of the present application, Fig.19 A schematic diagram of a third cross section 2100 of the power semiconductor device 1900 along line HH′ in FIG.

[0036] Fig. 22 FIG. 2 is a schematic plan view of a partial region of a power semiconductor device 2200 according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] The specific embodiments of the present application will be described in detail below. It should be noted that the embodiments described herein are only for illustration and are not intended to limit the present application. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present application. However, it is obvious to those of ordinary skill in the art that these specific details do not have to be adopted to implement the present application. In other examples, in order to avoid confusing the present application, known circuits, materials or methods are not specifically described.

[0038] Throughout the specification, references to "one embodiment", "an embodiment", "an example" or "an example" mean that a particular feature, structure or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present application. Therefore, the phrases "in one embodiment", "in an embodiment", "an example" or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, particular features, structures or characteristics may be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes and that the drawings are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" used herein includes any and all combinations of one or more related listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise specified, the same elements have been designated by corresponding reference numerals in different drawings.

[0039] The terms “having,” “comprising,” “including,” “including,” and the like are open ended, and these terms indicate the presence of stated structures, elements, or features, but do not exclude additional elements or features.

[0040] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" another layer or region.

[0041] If it is intended to describe a situation where it is directly on another layer or another area, this article will use the expression “directly on…” or “on… and adjacent to…”.

[0042] In this document, relative doping concentrations are described by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means that the doping concentration is lower than the doping concentration of an "n"-doped region, while the "n"-doped region has a higher doping concentration than the "n-"-doped region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doped regions may have the same or different absolute doping concentrations.

[0043] In an embodiment of the present application, each semiconductor layer or region has a first conductivity type or a second conductivity type. The first conductivity type refers to one of n-type or p-type, and the second conductivity type is the other one. That is to say, the semiconductor layer with the first conductivity type can be an n-type semiconductor layer or a p-type semiconductor layer. When the semiconductor layer with the first conductivity type is an n-type semiconductor layer, the semiconductor layer with the second conductivity type is a p-type semiconductor layer. The n-type semiconductor layer is formed by doping n-type impurities in the semiconductor layer. The n-type impurities can be pentavalent elements such as phosphorus, arsenic, and nitrogen. The p-type semiconductor layer is formed by doping p-type impurities in the semiconductor layer. The p-type impurities can be trivalent elements such as boron, indium, gallium, and aluminum.

[0044] Figure 2 FIG. 2 is a schematic plan view of a partial area of ​​a power semiconductor device 200 according to an embodiment of the present application. It should be understood that Figure 2 Only a partial planar structure of the power semiconductor device 200 on one horizontal plane 209 is shown, which does not represent the overall structure of the power semiconductor device 200. Figure 2 As shown, a single first cell 221 of the power semiconductor device 200 includes an epitaxial platform region 202, a well region 203, a source region 204, and a well contact region 205. The epitaxial platform region 202 is in a strip shape, and its longitudinal direction is distributed along a first direction (y direction as shown in the figure). The well region 203 is distributed in the epitaxial layer, and surrounds the epitaxial platform region 202 in a square ring shape on the upper surface 209 of the epitaxial layer. The source region 204 is distributed in the well region 203, and is distributed in a square ring shape on the upper surface 209 of the epitaxial layer along the outer contour of the well region. Figure 2 As shown, there is a distance d1 between the inner contour of the source region 204 and the inner contour of the well region 203, wherein the inner contour of the well region 203 is also the outer contour of the epitaxial platform region 202, i.e., the sidewall. The well contact region 205 is located in the epitaxial platform region in the first direction (e.g., Figure 2In the source regions at both ends of the first direction (y direction as shown), the well region 203 and the source region 204 are separated from the epitaxial platform region in the first direction. In some embodiments, in the first direction, the distance h1 between adjacent well contact regions 205 distributed along the same straight line is at least 1.2 μm.

[0045] like Figure 2 As shown, the power semiconductor device 200 includes a plurality of first cells 221. The plurality of first cells 221 are arranged in a first direction and a second direction (eg, Figure 2 The well regions 203 of the adjacent first cells 221 are connected to each other to form a whole. Figure 2 A mesh structure is formed on the upper surface 209 of the epitaxial layer, and the meshes of the mesh structure are the epitaxial platform region 202. The source region 204 is located in the well region 203, and the source regions 204 of adjacent first cells 221 are interconnected to form a whole, and a mesh structure conformal to the well region 203 is formed on the upper surface 209 of the epitaxial layer.

[0046] exist Figure 2 In the embodiment, the well contact region 205 is embedded in the source region 204 and distributed in the source region at both ends of the epitaxial platform region 202 in the first direction.

[0047] exist Figure 2 In the embodiment, the plurality of first cells 221 are arranged in rows and columns. In a row, the central axes of the plurality of first cells 221 coincide with each other. Figure 2 As shown in the CC' line, in a row, the central axes of the first cells 221 coincide with each other. Figure 2 That is, in Figure 2 In the embodiment, along the first direction, the plurality of first cells 221 are arranged in a straight line. Similarly, along the second direction, the plurality of first cells 221 are also arranged in a straight line.

[0048] Figure 2 Each sub-area shown in FIG. 2 is a structure of one horizontal surface of the power semiconductor device 200, namely, the upper surface 209 of the epitaxial layer. Figure 2 The area between the upper and lower dotted lines is the area of ​​the gate oxide layer or the gate electrode layer 212 covering the horizontal plane. In order to show the structure of each area on the horizontal plane, the device structure covering the horizontal plane is not drawn in the figure, but only the dotted lines are used to indicate the position of the gate oxide layer and the gate electrode layer. Therefore, the area between the two dotted lines in the figure represents the position of the gate oxide layer and the gate electrode layer, not the actual gate oxide layer and the gate electrode layer.

[0049] Figure 3 According to an embodiment of the present application, Figure 2 Schematic diagram of a first cross section 300 of a power semiconductor device 200 along line AA' in FIG. The first cross section 300 and the second direction, i.e. Figure 2 The x direction is parallel to the first direction, i.e. Figure 2 The y direction is vertical. Figure 3 As shown, the power semiconductor device 200 includes: a substrate layer 201, an epitaxial layer 219, a well region 203, a source region 204, a gate oxide layer 214, a gate electrode layer 212, a source electrode layer 207 and a drain electrode layer 206. The epitaxial layer 219 is located on the first surface of the substrate layer 201, and the drain electrode layer 206 covers the second surface of the substrate layer 201, and the first surface and the second surface are opposite and parallel. The epitaxial layer 219 has an epitaxial layer upper surface 209 and an epitaxial layer lower surface 210 that are opposite and parallel. Among them, the lower surface 210 of the epitaxial layer 219 covers the first surface of the substrate layer 201, and the upper surface 209 is covered by the gate oxide layer 214 on the first cross section 300. The epitaxial layer includes a plurality of well regions 203, extending from the epitaxial layer upper surface 209 to the inside of the epitaxial layer. The plurality of well regions 203 are isolated by the epitaxial platform region 202 and have approximately the same spacing. It should be understood that the epitaxial platform region 202 is a part of the epitaxial layer 219 and is located between the well regions 203. The source region 204 is located in each well region 203 and extends from the upper surface 209 of the epitaxial layer to the inside of the well region, wherein the bottom of the source region 204 does not reach the bottom of the well region 203, that is, the distance between the bottom of the well region 203 and the upper surface 209 of the epitaxial layer is greater than the distance between the bottom of the source region 204 and the upper surface 209 of the epitaxial layer. Both the well region 203 and the source region 204 are exposed to the upper surface 209 of the epitaxial layer. The gate oxide layer 214 covers the upper surface 209 of the epitaxial layer, isolating the gate electrode layer 212 thereon from the upper surface 209 of the epitaxial layer below. The gate electrode layer 212 is covered with an interlayer dielectric layer 213, and the source electrode layer 207 is located on the interlayer dielectric layer 213, and the gate electrode layer 212 and the source electrode layer 207 are isolated by the interlayer dielectric layer 213.

[0050] In one embodiment, the gate oxide layer 214 is silicon dioxide with a thickness between 5 and 200 nanometers. In other embodiments, the gate oxide layer 214 may also include other insulating materials such as silicon nitride and aluminum nitride. The interlayer dielectric layer 213 may be the same insulating material as the gate oxide layer 214, or may be other different insulating materials. The thickness of the interlayer dielectric layer 213 is much greater than the thickness of the gate oxide layer 214.

[0051] In one embodiment, the epitaxial layer 219 is of a single conductivity type and has a substantially uniform concentration. In some embodiments, the epitaxial layer 219 includes multiple semiconductor layers with different doping concentrations. For example, the epitaxial layer 219 may include a first semiconductor layer with a first doping concentration and a second semiconductor layer with a second doping concentration, wherein the first semiconductor layer is located in a region below the well region at a certain distance from the bottom of the well region, and the second semiconductor layer is located above the first semiconductor layer, and the first doping concentration is less than the second doping concentration. In other embodiments, the epitaxial layer 219 may also be composed of more semiconductor layers with different doping concentrations.

[0052] In one embodiment, the substrate layer 201, the epitaxial layer 219 and the source region 204 have a first doping type, and the well region 203 and the well contact region 205 have a second doping type. In one embodiment, the first doping type is n-type doping, and the second doping type is p-type doping. It should be understood that in other embodiments, the first doping type may be p-type doping, and the second doping type may be n-type doping. In one embodiment, the doping concentration of the well contact region 205 is greater than the doping concentration of the well region 203, and the doping concentration of the substrate layer 201 is greater than the doping concentration of the epitaxial layer 219.

[0053] exist Figure 3 In the embodiment, the epitaxial platform region 202 located between the well regions 203 and the portion close to the gate oxide layer 214 form a JFET region. Figure 3 As can be seen from the figure, in the first cross section 300, there is no well contact region 205, so the size of a single first cell of the power semiconductor device 200 is L= Ls+2Lch+Ljfet. Compared with the prior art, since the well contact region 205 is located in the source regions 204 at both ends in the longitudinal direction of the epitaxial platform region 202, but not in the second direction (such as Figure 2 In the x direction shown in FIG. 1 ), the first cross section 300 overlaps with the source region 204 in size, that is, the well contact region 205 is not included in the first cross section 300, and further, the ohmic contact region (the contact between the source electrode layer and the well contact region and the source region) is not included. Therefore, in the second direction, that is, in the direction perpendicular to the length of the source region, there is no need to have Figure 1 The ohmic contact region, the overlap region between the gate oxide layer and the source region, and the thickness of the sidewall of the interlayer dielectric layer are shown, that is, the dimensions Lohmic, Loverlap, and Lgs are omitted. Furthermore, since no ohmic contact is required, the width of the source region can also be greatly reduced, so that the size of the device can be greatly reduced, so that the semiconductor device 200 can have a smaller device area.

[0054] Figure 4 According to an embodiment of the present application, Figure 2 FIG. 4 is a schematic diagram of a second cross section 400 of the power semiconductor device 200 along line BB' in FIG. Figure 4As shown, the second cross section 400 includes: substrate layer 201, epitaxial layer 219, well region 203, well contact region 205, source electrode layer 207 and drain electrode layer 206. On the second cross section 400, the well regions 203 of the first cells 221 in the same row are connected as a whole, and their source regions 204 are also connected as a whole, and the well contact region 205 is located in the source region 204, extending from the upper surface 209 of the epitaxial layer to the inside of the well region. The source region 204 and the well contact region 205 are both exposed on the upper surface of the epitaxial layer. On the second cross section 400, the gate oxide layer 214 and the gate electrode layer 212 are not distributed. The source electrode layer 207 is connected to the well contact region 205 and the source region 204 exposed on the upper surface 209 of the epitaxial layer.

[0055] In the second cross section 400, the well contact region 205 is located on both sides of the source region 204, and its depth is greater than the depth of the source region 204, so it passes through the bottom of the source region 204 and reaches the bottom of the well region 203. In the second cross section 400, the source region 204 and the well contact region 205 are exposed to the upper surface 209 of the epitaxial layer. The source electrode layer 209 directly covers the upper surface 209 of the epitaxial layer in this cross section, and is connected to the source region 204 and the well contact region 205, connecting the potential of the source region 204 and the well contact region 205 to the source potential of the device.

[0056] Figure 5 FIG. 5 is a schematic plan view of a partial area of ​​a power semiconductor device 500 according to another embodiment of the present application. It should be understood that Figure 5 Only a partial planar structure of the power semiconductor device 500 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 500. Figure 5 As shown, a single first cell 521 of the power semiconductor device 500 includes an epitaxial platform region 202, a well region 203, a source region 204 and a well contact region 505. Figure 2 Compared with the embodiment, Figure 5 In the embodiment, at both ends of the first cells 521 in the longitudinal direction of the same row, the well contact region 505 of each first cell 521 extends in the second direction and is connected to form a whole. Figure 5 shown.

[0057] exist Figure 5 In the embodiment, the first cross section along the AA′ line has the same structure as the first cross section 300 of the power semiconductor device 200 , and therefore, for the sake of simplicity, it will not be described in detail herein.

[0058] Figure 6 According to an embodiment of the present application, Figure 5Schematic diagram of a second cross section 600 of the power semiconductor device 500 along line BB' in FIG. In this cross section, the well contact region 505 is connected as a whole, so there is no distribution of the well region 203 and the source region 204 in this cross section. Figure 5 and Figure 6 In the embodiment of FIG. 6 , the depth of the well contact region 505 is consistent with the depth of the well region 203, resulting in a distribution without the well region 203 in the cross section 600. It should be understood that in some embodiments, the depth of the well contact region 505 is less than the depth of the well region 203. In these embodiments, Figure 5 In the cross section along line BB' shown, the bottom of the well contact region is the well region.

[0059] Figure 7 FIG. 7 is a schematic plan view of a partial area of ​​a power semiconductor device 700 according to an embodiment of the present application. It should be understood that Figure 7 Only a partial planar structure of the power semiconductor device 700 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 700. Figure 2 The difference is, Figure 7 In the embodiment, the power semiconductor device 700 includes first cells 221 arranged in parallel. The well contact regions 205 are distributed at both ends of some of the first cells 221 in the longitudinal direction, rather than at both ends of all of the first cells 221 in the longitudinal direction. It should be understood that in some embodiments, the well contact regions can be distributed in any number in the longitudinal direction of all or some of the first cells as needed. For example, in some embodiments, the well contact regions can be distributed at only one end of the first cells in the longitudinal direction, rather than at both ends.

[0060] The first cross section of the power semiconductor device 700 along the line AA′ has the same structure as the first cross section 300 of the power semiconductor device 200 . Therefore, for the sake of simplicity, it will not be described in detail here.

[0061] Figure 8 According to an embodiment of the present application, Figure 7 FIG. 8 is a second cross section 800 of the power semiconductor device 700 along line BB'. Figure 7 As shown, the second cross section 800 includes: substrate layer 201, epitaxial layer 219, well region 203, source region 204, well contact region 205, source electrode layer 207 and drain electrode layer 206. In the second cross section 800, the well region 203 is distributed on the epitaxial layer 219, and the source region 204 and the well contact region 205 are distributed in the well region 203. The source electrode layer 207 is connected to the well contact region 205 and the source region 204 exposed on the upper surface 209 of the epitaxial layer.

[0062] exist Figure 8In the embodiment, the depth of the well contact region 205 is consistent with the depth of the source region 204, and both are smaller than the depth of the well region 203. Since the well contact region 205 is selectively distributed in the source regions at both ends of the longitudinal direction of part of the first cell 221, Figure 4 Compared with the embodiment, in the second cross section 800 , more source region 204 is exposed on the upper surface 209 of the epitaxial layer.

[0063] In some embodiments, based on the power semiconductor device 700 , the gate oxide layer 214 and the gate electrode layer 212 may also extend in the first direction to cover the source region except the well contact region 205 and a certain area around it.

[0064] Fig. 9 FIG. 9 is a schematic plan view of a partial area of ​​a power semiconductor device 900 according to an embodiment of the present application. It should be understood that Fig. 9 Only a partial planar structure of the power semiconductor device 900 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 900. Figure 2 The difference is that, in the upper surface of the epitaxial layer of the power semiconductor device 900, the gate oxide layer and the gate electrode layer 212 extend along the first direction toward the regions at both ends of the first cell, covering other regions except the well contact region 205 and its surrounding regions.

[0065] The first cross section of the power semiconductor device 900 along the AA′ line has the same structure as the first cross section 300 of the power semiconductor device 200 . Therefore, for the sake of simplicity, it will not be described in detail here.

[0066] Fig.10 According to an embodiment of the present application, Fig. 9 FIG. 1 is a second cross section 1000 of the power semiconductor device 900 along line BB'. Fig.10 As shown, the second cross section 1000 includes: substrate layer 201, epitaxial layer 219, well region 203, source region 204, well contact region 205, gate oxide layer 214, gate electrode layer 212, interlayer dielectric layer 213, source electrode layer 207 and drain electrode layer 206. Figure 8 Compared with the second cross section 800 shown in FIG. 1 , the upper surface 209 of the epitaxial layer outside the well contact region 205 and its surrounding area is covered with an interlayer dielectric layer 213, and the upper surface 209 of the epitaxial layer in the interlayer dielectric layer 213 is also covered with a gate structure, namely, a gate oxide layer 214 and a gate electrode layer 212. The gate structure generates a channel in a part of the well region below it, thereby further improving the current density of the device.

[0067] exist Fig.10In the embodiment, the depth of the well contact region 205 is consistent with the depth of the well region 203, and the depth of the source region 204 is less than the depth of the well region 203. Since the well contact region 205 is selectively distributed in the source regions at both ends of the longitudinal direction of part of the first cell 221, Figure 4 Compared with the embodiment, in the second cross section 1000 , more source regions 204 are exposed on the upper surface 209 of the epitaxial layer.

[0068] Fig.11 FIG. 1 is a schematic plan view of a partial area of ​​a power semiconductor device 1100 according to an embodiment of the present application. It should be understood that Fig.11 Only a partial planar structure of the power semiconductor device 1100 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 1100. Figure 2 , 5 , 7 and 9 are different in that Fig.11 In the power semiconductor device 1100, adjacent first cells are staggered in the second direction, such as Fig.11 As shown, the central axes FF' and GG' of the first cells 921-1 and 921-2 adjacent in the second direction do not overlap. The well contact regions 205 are distributed at both ends of each first cell 921 in the longitudinal direction. The gate oxide layer and the gate electrode layer cover other areas except the well contact region and its surrounding areas, such as Fig.11 Shown by dotted line.

[0069] The first cross section of the power semiconductor device 1100 along the AA′ line has the same structure as the first cross section 300 of the power semiconductor device 200 . Therefore, for the sake of simplicity, it will not be described in detail here.

[0070] Fig.12 According to an embodiment of the present application, Fig.11 FIG. 1 is a schematic diagram of a second cross section 1200 of the power semiconductor device 1100 along line BB' in FIG. Fig.12 As shown, the second cross section 1200 includes: substrate layer 201, epitaxial layer 219, well region 203, source region 204, well contact region 205, gate oxide layer 214, gate electrode layer 212, interlayer dielectric layer 213, source electrode layer 207 and drain electrode layer 206. In the second cross section 1200, the well region 203 is distributed on the epitaxial layer 219, and the source region 204 and the well contact region 205 are distributed in the well region 203. Fig.12In the embodiment, the depth of the well contact region 205 is consistent with the depth of the source region 204. In other embodiments, the depth of the well contact region 205 can be deeper or shallower than the depth of the source region 204. The source electrode layer 207 is connected to the well contact region 205 and the source region 204 region exposed to the upper surface 209 of the epitaxial layer. The gate oxide layer 214 and the gate electrode layer 212 cover other regions except the well contact region 205 and a certain area around it. The gate electrode layer 212 is isolated from the source electrode layer 207 by the interlayer dielectric layer 213.

[0071] Fig.13 According to an embodiment of the present application, Fig.11 FIG. 1 is a schematic diagram of a third cross section 1300 of the power semiconductor device 1100 along line EE′ in FIG. Fig.13 As shown, the third cross section 1300 includes: a substrate layer 201, an epitaxial layer 219, a well region 203, a source region 204, a gate oxide layer 214, a gate electrode layer 212, an interlayer dielectric layer 213, a source electrode layer 207, and a drain electrode layer 206. In the third cross section 1300, a well region 203 is distributed on the epitaxial layer 219. The source region 204 is distributed in the well region 203. The gate oxide layer 214 and the gate electrode layer 212 cover the upper surface 209 of the epitaxial layer. The gate electrode layer 212 is isolated from the source electrode layer 207 by the interlayer dielectric layer 213.

[0072] Fig.14 FIG. 1 is a schematic plan view of a partial area of ​​a power semiconductor device 1400 according to an embodiment of the present application. It should be understood that Fig.14 Only a partial planar structure of the power semiconductor device 1400 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 1400. Fig.14 As shown, the power semiconductor device 1400 includes a first cell 221 and a second cell 222. The power semiconductor device 1400 includes an epitaxial platform region 202, a well region 203, a source region 204 and a well contact region 205. In the first cell 221, the epitaxial platform region 202 is in a strip shape, and its longitudinal direction is distributed along the first direction (the y direction as shown in the figure). The well region 203 is distributed in the epitaxial layer, and surrounds the epitaxial platform region 202 in a square ring shape on the upper surface 209 of the epitaxial layer. The source region 204 is distributed in the well region 203, and is distributed along the outer contour of the well region in a square ring shape on the upper surface 209 of the epitaxial layer. In the second cell 222, the epitaxial platform region 202, the well region 203 and the source region 204 are in a strip shape, and their longitudinal direction is distributed in parallel along the first direction (the y direction as shown in the figure). Among them, the well region 203 is distributed on both sides of the epitaxial platform region 202, and the source region is distributed in the well region 203. The well contact regions 205 are distributed in the source region 204 at both ends of the first cell 221. There is a certain interval between adjacent well contact regions 205 distributed along the same straight line in the first direction. In some embodiments, the interval is at least 1.2 μm.

[0073] exist Fig.14 In the embodiment, the first cell 221 and the second cell 222 share the substrate layer and the epitaxial layer, and the layout distribution of the epitaxial platform region 202, the well region 203 and the source region 204 of the two cells is different. In the cells 221 and 222, the source region 204 is distributed in the well region 203, and a certain distance is maintained between the sidewall of the inner contour of the source region 204 and the sidewall of the epitaxial platform region 202. In the second direction, the cells 221 and the cells 222 are alternately distributed, and the adjacent source regions and well regions of the two are respectively connected to form a whole.

[0074] The first cross section of the power semiconductor device 1400 along line AA′ is as follows: Figure 3 As shown, no further description is given here.

[0075] Fig.15 According to an embodiment of the present application, Fig.14 FIG. 1 is a schematic diagram of a second cross section 1500 of the power semiconductor device 1400 along line BB′ in FIG. Fig.15 As shown, the second cross section 1500 includes: a substrate layer 201, an epitaxial layer 219, a well region 203, a well contact region 205, an interlayer dielectric layer 213, a source electrode layer 207, and a drain electrode layer 206. In the second cross section 1500, the well contact region 205 is located in each well region 203, extending from the upper surface 209 of the epitaxial layer to the inside of the well region. Both the well region 203 and the well contact region 205 are exposed on the upper surface of the epitaxial layer. In the second cross section 400, the gate oxide layer 214 and the gate electrode layer 212 are not distributed. The source electrode layer 207 extends downward through the window in the interlayer dielectric layer 213 and contacts the well contact region 205 and the part of the well region 203 exposed on the upper surface 209 of the epitaxial layer, as well as the part not in the second cross section 400. Fig.15 That is, in order to make the well contact region 205 contact with the source electrode layer 207, so as to connect the potential of the well region 203 to the source potential of the device (i.e., the potential connected to the source electrode layer), a plurality of windows are opened in the interlayer dielectric layer 213, and the source electrode layer 207 partially extends downward to fill the windows in the interlayer dielectric layer 213, or in some embodiments, the windows in the interlayer dielectric layer 213 may be filled with a conductive through-hole structure, so as to electrically connect the well contact region 205 and the source region 204 to the source electrode layer 207, and further to the source potential of the power semiconductor device 1400.

[0076] Fig.16 According to an embodiment of the present application, Fig.14 FIG. 16 is a third cross section 1600 of the power semiconductor device 1400 along line CC′. Fig.16As shown, the third cross section 1600 includes: substrate layer 201, epitaxial layer 219, well region 203, source region 204, gate oxide layer 214, gate electrode layer 212, interlayer dielectric layer 213, source electrode layer 207 and drain electrode layer 206. In the third cross section 1600, the well regions 203 are arranged in a second direction (perpendicular to the first direction) at intervals, and adjacent well regions 203 are isolated by epitaxial platform regions 202. The source region 204 is located in the well region 203. The gate oxide layer 214 and the gate electrode layer 212 cover the upper surface 209 of the epitaxial layer. The source electrode layer 207 is isolated from the gate electrode layer 212 by the interlayer dielectric layer 213.

[0077] Fig.17 FIG. 1 is a schematic plan view of a partial area of ​​a power semiconductor device 1700 according to an embodiment of the present application. It should be understood that Fig.17 Only a partial planar structure of the power semiconductor device 1700 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 1700. Fig.14 The difference is, Fig.17 In the embodiment of the present invention, the gate oxide layer 214 and the gate electrode layer 212 extend in the first direction of the device, covering other regions except the well contact region 205. That is to say, in the second cell 1722, the gate oxide layer 214 and the gate electrode layer 212 almost completely cover the well contact region 205. It should be understood that in order to ensure that the well contact region 205 and the source region 204 are both in contact with the source electrode layer 207, the edges of the gate oxide layer 214 and the gate electrode layer 212 maintain a certain distance from the edges of the well contact region 205, so that the source region around the well contact region 205 can be in contact with the source electrode layer 207.

[0078] Fig.18 According to an embodiment of the present application, Fig.17 FIG. 1 is a schematic diagram of a second cross section 1800 of the power semiconductor device 1700 along line BB' in FIG. Fig.18 As shown, the second cross section 1800 includes: a substrate layer 201, an epitaxial layer 219, a well region 203, a source region 204, a well contact region 205, a gate oxide layer 214, a gate electrode layer 212, an interlayer dielectric layer 213, a source electrode layer 207 and a drain electrode layer 206. Fig.15 In comparison, Fig.18 In the interlayer dielectric layer 213, the gate oxide layer 214 and the gate electrode layer 212 cover the epitaxial platform region 202. Specifically, the gate oxide layer 214 and the gate electrode layer 212 cover the epitaxial platform region 202 and the well region and the source region on both sides of the platform. The gate electrode layer 212 and the source electrode layer 207 are isolated by the interlayer dielectric layer 213.

[0079] Fig.19 FIG. 1 is a schematic plan view of a partial area of ​​a power semiconductor device 1900 according to an embodiment of the present application. It should be understood that Fig.19Only a partial planar structure of the power semiconductor device 1900 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 1900. Fig.17 The difference is, Fig.19 , adjacent first cells 221 (with second cells 1722 in between) are staggered in the second direction (x direction), that is, the central axes of adjacent first cells 221 in the second direction do not overlap. The gate oxide layer 214 and the gate electrode layer 212 cover other areas except the well contact area 205. It should be understood that in order to ensure that the well contact area 205 and the source area 204 are both connected to the source electrode layer 207, the edges of the gate oxide layer 214 and the gate electrode layer 212 maintain a certain distance from the edges of the well contact area 205, so that the source area around the well contact area 205 can be connected to the source electrode layer 207.

[0080] exist Fig.19 In the embodiment, the first cross section along the AA′ line has the same structure as the first cross section 300 of the power semiconductor device 200 , and therefore, for the sake of simplicity, it will not be described in detail herein.

[0081] Fig. 20 According to an embodiment of the present application, Fig.19 FIG. 2 is a schematic diagram of a second cross section 2000 of the power semiconductor device 1900 along line BB'. Fig. 20 As shown, the second cross section 2000 includes: a substrate layer 201, an epitaxial layer 219, a well region 203, a source region 204, a well contact region 205, a gate oxide layer 214, a gate electrode layer 212, an interlayer dielectric layer 213, a source electrode layer 207, and a drain electrode layer 206. Due to the staggered distribution of the first cells 221 in the second direction, the cross sections of the first cells 221 on both sides of the cross section of the second cells 1722 on the second cross section 2000 are asymmetric. On the second cross section 2000, the well regions 203 are distributed in the epitaxial layer 219 at intervals, and the middle is isolated by the epitaxial platform region 202. The source region 204 is located in the well region 203. One side of each second cell 1722 includes a well region 203 with a source region 204, and the other side includes a well region 203 with a source region 204 and a well contact region 205. The well contact region 205 is in contact with the source region 204 in the well region 203, and is in contact with the source metal layer 207 on the upper surface 209 of the epitaxial layer. The gate oxide layer 214 and the gate electrode layer 212 cover a portion of the upper surface 209 of the epitaxial layer, that is, they do not cover the well contact region 205 and a certain range of the surrounding area. The gate electrode layer 212 and the source electrode layer 207 are isolated by an interlayer dielectric layer 213.

[0082] Fig.21 According to an embodiment of the present application, Fig.19 FIG. 2 is a schematic diagram of a third cross section 2100 of the power semiconductor device 1900 along line HH′ in FIG. Fig.21 As shown, the third cross section 2100 includes: substrate layer 201, epitaxial layer 219, well region 203, source region 204, gate oxide layer 214, gate electrode layer 212, interlayer dielectric layer 213, source electrode layer 207 and drain electrode layer 206. Due to the staggered distribution of the first cells 221 in the second direction, the cross sections of the first cells 221 on both sides of the cross section of the second cell 1722 on the third cross section 2100 are asymmetric. On the third cross section 2100, the well regions 203 are distributed in the epitaxial layer 219 at intervals, and the middle is isolated by the epitaxial platform region 202. The source region 204 is located in the well region 203. The gate oxide layer 214 and the gate electrode layer 212 cover the upper surface 209 of the epitaxial layer. The gate electrode layer 212 and the source electrode layer 207 are isolated by the interlayer dielectric layer 213.

[0083] In the power semiconductor device 1900, as the length of the epitaxial platform region 202 of the first cell 221 in the first direction varies, the structure of the first cross section may vary. Fig.19 In the embodiment, when the epitaxial platform region 202 of the first unit cell 221 is long enough so that its projection in the second direction forms an overlapping portion, the first cross section of the overlapping portion along the AA' line is as follows: Figure 3 However, when the length of the epitaxial platform region 202 of the first unit cell 221 is such that its projection in the second direction does not constitute an overlapping portion, there may not be such a Figure 3 The first cross section is shown.

[0084] Fig. 22 FIG. 2 is a schematic plan view of a partial area of ​​a power semiconductor device 2200 according to an embodiment of the present application. It should be understood that Fig. 22 Only a partial planar structure of the power semiconductor device 2200 on one horizontal plane is shown, which does not represent the overall structure of the power semiconductor device 2200. Fig.17 compared to, Fig. 22 In the example, two adjacent second cells 1722 include two parallel first cells 221. Fig. 22 In the embodiment of FIG. 2 , to increase the area of ​​the well contact region, the well contact regions of two adjacent first cells 221 are extended and connected to form a well contact region 2205. It should be understood that in some embodiments, the well contact regions of different first cells do not have to be connected together.

[0085] In some embodiments, three, four, or any other number of first cells 221 may be included between adjacent cells 1722. Well contact regions between adjacent first cells 221 may be connected together or may not be interconnected.

[0086] The first cross section of the power semiconductor device 2200 along the AA′ line has the same structure as the first cross section 300 of the power semiconductor device 200 . Therefore, for the sake of simplicity, it will not be described in detail here.

[0087] The second cross section of the power semiconductor device 2200 along line BB' has a similar structure to the second cross section of the power semiconductor device 1700, with only the width of the well contact region and the corresponding peripheral source region being different. Therefore, for the sake of simplicity, it will not be described in detail here.

[0088] In the embodiment of the present application, in order to better illustrate the structure of the device, the power semiconductor device is divided into a plurality of cells. It should be understood that the division of the cells in the embodiment of the present application is only an exemplary description, and a person skilled in the art can define cells according to different structural division methods.

[0089] This application uses MOSFET devices as an example to illustrate the principles of the invention. It should be understood that the present invention is also applicable to power semiconductor devices of other structures, such as IGBTs, etc. After reading this application, a person of ordinary skill in the art can make improvements based on the device layout of this application as needed and apply it to devices of other structures or types.

[0090] The embodiments of the present application can be used not only for devices using silicon as a semiconductor base layer, but also for devices using wide bandgap materials, such as SiC and GaN, as a semiconductor base layer.

[0091] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A power semiconductor device, comprising a plurality of first cells, wherein each first cell comprises: substrate layer; The epitaxial layer has an epitaxial layer upper surface and an epitaxial layer lower surface, wherein the epitaxial layer lower surface is in contact with the substrate layer; The well region is distributed in the epitaxial layer and is an epitaxial platform region in the shape of a square ring surrounding a strip on the upper surface of the epitaxial layer; The source region is distributed in the well region and is distributed in a square ring shape on the upper surface of the epitaxial layer along the outer contour of the well region, and there is a certain distance between the inner contour of the source region and the inner contour of the well region; as well as A well contact region is distributed in the source region and is located at at least one end of the epitaxial platform region in the first direction; The first direction is parallel to the upper surface of the epitaxial layer and is the length direction of the epitaxial platform region. 2 . The power semiconductor device as claimed in claim 1 , wherein each first cell comprises two well contact regions respectively distributed at two ends of the epitaxial platform region in the first direction. 3 . The power semiconductor device according to claim 2 , wherein a distance between the two well contact regions is greater than 1.2 μm. 4 . The power semiconductor device according to claim 1 , comprising at least two first cells, whose central axes coincide with each other in a second direction, and the second direction is parallel to the upper surface of the epitaxial layer and perpendicular to the first direction. 5 . The power semiconductor device according to claim 4 , wherein the well contact regions located at the same end of the at least two first cells extend in the second direction and are connected into a whole.

6. The power semiconductor device as claimed in claim 1 comprises at least two first cells arranged adjacent to each other in a second direction, wherein the central axes of the adjacent first cells in the second direction do not overlap, and the second direction is equal to the upper surface of the epitaxial layer and perpendicular to the first direction.

7. The power semiconductor device according to claim 1, further comprising a second cell, wherein the second cell shares a substrate layer and an epitaxial layer with the first cell, and the second cell comprises on an upper surface of the epitaxial layer: The epitaxial platform region is distributed in a strip shape along the first direction; Well regions, distributed in strips along the first direction on both sides of the epitaxial platform region; as well as A source region, distributed in the well region in a strip shape along the first direction, wherein a distance exists between a sidewall of the source region along the first direction and a sidewall of the epitaxial platform region on the same side; In the second direction parallel to the upper surface of the epitaxial layer and perpendicular to the first direction, the first cells and the second cells are arranged at intervals, and adjacent source regions of adjacent first cells and second cells are connected.

8. The power semiconductor device according to claim 1, further comprising a second cell, wherein the second cell shares a substrate layer and an epitaxial layer with the first cell, and the second cell comprises on an upper surface of the epitaxial layer: The epitaxial platform region is distributed in a strip shape along the first direction; Well regions, distributed in strips along the first direction on both sides of the epitaxial platform region; as well as A source region, distributed in the well region in a strip shape along the first direction, wherein a distance exists between a sidewall of the source region along the first direction and a sidewall of the epitaxial platform region on the same side; In which, in a second direction parallel to the upper surface of the epitaxial layer and perpendicular to the first direction, multiple first cells are arranged between every two second cells, and adjacent source regions of adjacent first cells and second cells are connected, and adjacent source regions of adjacent first cells are connected. 9 . The power semiconductor device according to claim 8 , wherein the well contact regions of the plurality of first cells between the two second cells and located on the same side extend in the second direction and are connected as a whole.

10. The power semiconductor device according to any one of claims 1 to 9, further comprising: The source electrode layer is connected to the well contact region and the source region around the well contact region.

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