Semiconductor device and manufacturing method thereof

Abstract

According to the semiconductor device and the manufacturing method thereof provided by the invention, the inversion lightly doped region different from the drift region is formed in the drift region close to the drain region below the field plate of the LDMOS device region, so that the electric field at the corner below the field plate is adjusted through the inversion lightly doped region, the breakdown voltage of the LDMOS device is improved, and the HCI effect can be improved. Besides, injection is carried out on the LDMOS device region when injection is carried out on the lightly doped drain region of the CMOS device region to form the inverted lightly doped region, so that a photomask does not need to be additionally arranged, and the cost is relatively low.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) devices are majority carrier conductive MOS devices that use a double-diffused process to form a channel through the concentration difference of lateral double diffusion. Compared with traditional CMOS devices, LDMOS devices generally have a longer low-doped drift region NDFT in the drain part to bear the source-drain voltage, which is why LDMOS devices have a higher voltage resistance than CMOS devices. Due to the advantages of high voltage resistance and good compatibility with CMOS devices, LDMOS devices are widely used in the BCD (Bipolar-CMOS-DMOS) process to prepare power management chips.

[0003] To improve the voltage resistance of LDMOS devices, the following methods are commonly used: (1) Increasing the width of the depletion layer by reducing the doping concentration of the drift region as a whole. However, this method cannot effectively improve the width of the depletion layer near the surface channel of the device, and the surface voltage resistance is still insufficient; (2) The high resistance of the drift region can withstand high voltage, and the breakdown voltage (BV) can be increased by increasing the length of the drift region. However, the increase in the length of the drift region will increase the chip area and on-resistance; (3) Using field plate technology to balance the surface electric field and increase the breakdown voltage.

[0004] Among them, field plate technology is a technical means to improve the withstand voltage by dispersing the electric field concentration to make the electric field distribution more uniform. Its specific principle is as follows: Figure 1 In LDMOS devices, the actual interface between the P-type well PW and the N-type drift region N Drift (i.e., the interface of the PN junction) is not as Figure 1 The ideal interface shown in the figure will have a certain curvature due to the diffusion of the injected ions, and the interface curvature is often large, which makes it easy for the electric field to concentrate. The peak electric field in the depletion region exists at the PN junction interface formed by PW and NDrift. When the P-type region is depleted, an immovable negative positive charge center is left, and when the N-type region is depleted, an immovable positive charge center is left. By adding a field plate, the vertical electric field and the horizontal electric field generated by the field plate are superimposed, which can make the electric field distribution in the drift region more uniform, thereby increasing the breakdown voltage of the LDMOS device. However, the current problem is that the area with relatively strong electric field is mainly concentrated below the field plate, especially at the corner below the field plate, where it reaches the maximum, affecting the breakdown voltage of the LDMOS device. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can adjust the electric field at the corner below the field plate and improve the breakdown voltage of the LDMOS device.

[0006] To achieve the above object, the present invention provides a semiconductor device, comprising:

[0007] A substrate having an LDMOS device region, wherein a drift region of a first conductivity type and a first well of a second conductivity type are formed in the substrate of the LDMOS device region, wherein a second conductivity type inversion lightly doped region and a first conductivity type first drain region are formed in the drift region, wherein a first source region is formed in the first well, wherein the first source region and the first drain region are located on both sides of the inversion lightly doped region, and wherein a doping concentration of the second conductivity type ions in the inversion lightly doped region is lower than a doping concentration of the first conductivity type ions in the first source region;

[0008] A first gate structure is formed on the drift region between the first source region and the inversion lightly doped region;

[0009] A sidewall spacer formed on a sidewall of the gate structure;

[0010] a barrier layer covering the drift region, the inversion lightly doped region and the sidewall between the first gate structure and the first drain region and extending onto a portion of the top of the first gate structure;

[0011] A field plate is formed on the barrier layer, and the inversion lightly doped region is located below the bottom of the field plate.

[0012] Optionally, the doping concentration of the inversion lightly doped region along the direction from the first gate structure to the first drain region is uniform, or the doping concentration of the inversion lightly doped region along the direction from the first gate structure to the first drain region gradually decreases.

[0013] Optionally, the first drain region is not connected to the inversion lightly doped region; and / or the substrate further has a medium voltage CMOS device region, and the inversion lightly doped region is formed together with the second conductivity type lightly doped drain region of the medium voltage CMOS device region.

[0014] Optionally, the semiconductor device further comprises at least one of the following (1) to (7):

[0015] (1) The substrate comprises a base, a buried layer of a first conductivity type, and an epitaxial layer of a second conductivity type stacked in sequence from bottom to top, the drift region and the first well are both formed in the epitaxial layer, and an isolation region of the second conductivity type is also formed in the epitaxial layer below the drift region, and the top of the isolation region is connected to the bottom of the first well and the bottom of the drift region;

[0016] (2) a second well of a second conductivity type is further formed in the LDMOS device region, the second well being laterally distributed outside the drift region along a direction from the first gate structure to the first drain region, a body region of a second conductivity type being formed in both the second well and the first well, the body region in the second well being isolated from the first drain region by a corresponding device isolation structure, and the body region in the first well being connected to the first source region;

[0017] (3) a lightly doped region of the first conductivity type is further formed in the first well between the first source region and the first gate structure, and a doping concentration of the first conductivity type ions in the lightly doped region is lower than a doping concentration of the first conductivity type ions in the first source region;

[0018] (4) a third well of the first conductivity type is further formed in the boundary region of the LDMOS device region, and an ion heavily doped region of the first conductivity type is formed in the third well;

[0019] (5) The substrate further comprises a medium voltage CMOS device region, wherein the medium voltage CMOS device region comprises a medium voltage PMOS device region and a medium voltage NMOS device region, wherein an N-type well is formed in the medium voltage PMOS device region, wherein a P-type well is formed in the medium voltage NMOS device region, wherein a second gate structure is formed on the medium voltage PMOS device region, wherein a third gate structure is formed on the medium voltage NMOS device region, wherein a second source region and a second drain region are formed in the medium voltage PMOS device region on both sides of the second gate structure, and wherein a third source region and a third drain region are formed in the medium voltage NMOS device region on both sides of the third gate structure;

[0020] (6) The first conductivity type is N-type, the second conductivity type is P-type, the drift region is an N-type drift region, and the inversion lightly doped region is a P-type lightly doped region;

[0021] (7) The semiconductor device further includes an interlayer dielectric layer and a plurality of contact plugs, wherein the interlayer dielectric layer buries the first source region and the first drain region, the barrier layer, the sidewall, the first gate structure and the substrate, and the contact plugs penetrate the interlayer dielectric layer and are electrically connected at their bottoms to the first source region or the first drain region or the first gate structure.

[0022] Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0023] Providing a substrate having an LDMOS device region, forming a laterally distributed drift region of a first conductivity type and a first well of a second conductivity type in the LDMOS device region;

[0024] forming a desired first gate structure on the LDMOS device region;

[0025] Performing lightly doped ion implantation of the second conductivity type into a designated area of ​​the drift region close to the first drain region to be formed, so as to form an inversion lightly doped region;

[0026] forming a sidewall spacer on a sidewall of the first gate structure;

[0027] Performing source-drain ion implantation on the LDMOS device region using first conductive type ions to form a first conductive type first drain region in the drift region, and forming a first source region in the first well, wherein the first source region and the first drain region are located on both sides of the inversion lightly doped region, and the doping concentration of the second conductive type ions in the inversion lightly doped region is lower than the doping concentration of the first conductive type ions in the first drain region;

[0028] forming a patterned barrier layer, the barrier layer covering the drift region, the inversion lightly doped region and the sidewall between the first gate structure and the first drain region and extending onto a portion of the top of the first gate structure;

[0029] An interlayer dielectric layer is deposited on the barrier layer and the device surface exposed thereon, and a plurality of contact plugs are formed in the interlayer dielectric layer by a contact plug process, and a field plate required for the LDMOS device region is formed at the same time, wherein the inverted lightly doped region is located below the bottom of the field plate.

[0030] Optionally, the substrate further has a medium voltage CMOS device region, and the step of forming the inversion lightly doped region comprises:

[0031] Coating a photoresist layer on the first gate structure and the substrate;

[0032] The photoresist layer is exposed by using a mask in which each light-transmitting area is a fully light-transmitting area or a half-tone mask, wherein the light-transmitting area of ​​the half-tone mask corresponding to the medium-voltage CMOS device area is a fully light-transmitting area, and the light-transmitting area corresponding to the designated area is a semi-light-transmitting area;

[0033] Developing the exposed photoresist layer to form a patterned photoresist layer to define an area in the medium voltage CMOS device area and the designated area where ion implantation of a lightly doped drain region of the second conductivity type is to be performed;

[0034] Using the patterned photoresist layer as a mask, ion implantation of a lightly doped drain region of a second conductivity type is performed on the medium voltage CMOS device region and the designated region, so as to form the lightly doped drain region of the medium voltage CMOS device region and the inversion lightly doped region in the designated region at the same time;

[0035] Among them, when a mask in which each light-transmitting area is a fully light-transmitting area is used, the doping concentration of the inversion lightly doped area along the direction from the first gate structure to the first drain area is uniform; when a half-tone mask is used, the doping concentration of the inversion lightly doped area along the direction from the first gate structure to the first drain area gradually decreases.

[0036] Optionally, the first drain region is not connected to the inversion lightly doped region.

[0037] Optionally, the substrate further has a medium voltage CMOS device region, and the manufacturing method further comprises at least one of the following (1) to (6):

[0038] (1) after forming the first gate structure and before or after implanting lightly doped ions of the second conductivity type into the designated region, implanting lightly doped ions of the first conductivity type into a region of the first well close to the first gate structure, so as to form a corresponding lightly doped region of the first conductivity type in the first well between the first source region and the first gate structure, wherein the doping concentration of the first conductivity type ions in the lightly doped region is lower than the doping concentration of the first conductivity type ions in the first source region;

[0039] (2) while forming a medium-voltage well of the second conductivity type in the medium-voltage CMOS device region, a second well of the second conductivity type is also formed in the LDMOS device region, the second well being laterally distributed outside the drift region along a direction from the first gate structure to the first drain region, and while forming a source region and a drain region of the second conductivity type in the medium-voltage CMOS device region, a body region of the second conductivity type is formed in both the second well and the first well, the body region in the second well being isolated from the first drain region by a corresponding device isolation structure, and the body region in the first well being connected to the first source region;

[0040] (3) while forming the first gate structure on the LDMOS device region, a required gate structure is also formed on the medium voltage CMOS device region, and while forming a sidewall on the sidewall of the first gate structure, a sidewall is also formed on the sidewall of the gate structure in the medium voltage CMOS device region;

[0041] (4) while implanting lightly doped ions of the second conductivity type into the designated area to form an inversion lightly doped area, also implanting lightly doped ions into a corresponding area of ​​the medium voltage CMOS device area to form a lightly doped drain area of ​​the second conductivity type required by the medium voltage CMOS device area;

[0042] (5) performing source and drain ion implantation on the LDMOS device region using ions of the first conductivity type, and also performing source and drain ion implantation on the medium voltage CMOS device region, so as to form source and drain regions required by the medium voltage CMOS device region;

[0043] (6) While forming a medium-voltage well of the first conductivity type in the medium-voltage CMOS device region, a third well of the first conductivity type is also formed in a boundary region of the LDMOS device region.

[0044] Optionally, the method for manufacturing a semiconductor device further includes at least one of the following (1) to (3):

[0045] (1) The substrate comprises a base, a buried layer of a first conductivity type, and an epitaxial layer of a second conductivity type stacked in sequence from bottom to top, and the drift region and the first well are both formed in the epitaxial layer;

[0046] (2) an isolation layer of a second conductivity type is further formed in the substrate below the drift region, and the bottom of the first well and the bottom of the drift region are both connected to the top of the isolation layer;

[0047] (3) While performing source-drain ion implantation on the LDMOS device region using first conductivity type ions, also performing source-drain ion implantation on the first conductivity type third well in the boundary region of the LDMOS device region to form a first conductivity type ion heavily doped region in the third well.

[0048] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0049] 1. An inversion lightly doped region different from the drift region is formed in the drift region near the drain region under the field plate of the LDMOS device region, thereby utilizing the superposition of the vertical electric field and the horizontal electric field generated by the field plate to modulate the electric field distribution in the drift region. At the same time, the inversion lightly doped region is utilized to adjust the electric field at the corner below the field plate, thereby improving the curvature of the PN junction interface formed by the first well and the drift region, dispersing the electric field concentration, and helping the gate to consume the immovable positive charge center left when the N-type region of the PN junction is depleted, thereby relatively improving the breakdown voltage of the LDMOS device and being beneficial to improving the HCI (hot carrier injection) effect.

[0050] 2. When lightly doped drain region injection (LDD injection) is performed in the CMOS device region, the LDMOS device region is injected at the same time to form the inversion lightly doped region, thereby eliminating the need for an additional photomask and resulting in lower costs.

[0051] 3. Further optionally, the doping concentration of the inversion lightly doped region of the LDMOS device region gradually decreases along the direction from the first gate structure to the first drain region, thereby optimizing the curvature of the PN junction interface formed by the first well and the drift region while adjusting the electric field at the corner below the field plate by using the inversion lightly doped region, making the electric field distribution more uniform, thereby further improving the breakdown voltage of the LDMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0053] Figure 1 It is a schematic flow chart of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention.

[0054] Figures 2 to 4 Schematic diagrams of cross-sectional structures of three exemplary semiconductor devices according to specific embodiments of the present invention.

[0055] Figure 5 It is a schematic flow chart of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention.

[0056] Figures 6 to 11 It is a schematic cross-sectional view of a device structure in a method for manufacturing a semiconductor device according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0057] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0059] Please refer to Figures 2 to 4 An embodiment of the present invention provides a semiconductor device, which includes a substrate 100 having an LDMOS device region, a first gate structure, a spacer, a barrier layer 108 and a field plate 109 .

[0060] The material of the substrate 100 of the LDMOS device region may be any suitable semiconductor substrate material such as silicon, germanium, silicon carbide, silicon germanium, gallium arsenide, indium gallium or silicon on insulator, and its conductivity type may be the second conductivity type (eg, P type).

[0061] A first well 1011 of a second conductivity type (e.g., P type) distributed laterally, a drift region (N Drift) 1012 of a first conductivity type (e.g., N type), and a second well 1013 of a second conductivity type are formed in the substrate 100 of the LDMOS device region. A certain thickness of the substrate 100 that is not further doped may be retained below the bottom of the first well 1011, the drift region 1012, and the second well 1013, and this portion of the substrate 100 may be recorded as a base 1000 (Sub).

[0062] A second conductive type lightly inverted doped region (PLDD) 106 and a first conductive type first drain region 106d are formed in the surface layer of the drift region 1012. A second conductive type body region 107 and a first conductive type first source region 106s are formed in the surface layer of the first well 1011. The first source region 106s and the first drain region 106d are located on both sides of the lightly inverted doped region 106. The doping concentration of the second conductive type ions in the lightly inverted doped region 106 is lower than the doping concentration of the first conductive type ions in the first drain region 106d. A second conductive type body region 107 is also formed in the surface layer of the second well 1013. The body region 107 of the second well 1013 can be separated from the first drain region 106d by a device isolation structure 102 such as a shallow trench isolation structure (STI) or a local field oxygen structure (LOCOS). The body region 107 of the first well 1011 can be connected to the first source region 106s. The body region 107 of the first well 1011 is used to realize the external connection of the first well 1011 and the short circuit between the first well 1011 and the first source region 106s, and the body region 107 of the second well 1013 is used to realize the external connection of the second well 1013. And the doping concentration of the second conductive type ions in the body region 107 of the first well 1011 is greater than the doping concentration of the second conductive type ions in the first well 1011, so that the resistance of the body region 107 of the first well 1011 is small. The doping concentration of the second conductive type ions in the body region 107 of the second well 1013 is greater than the doping concentration of the second conductive type ions in the second well 1013, so that the resistance of the body region 107 of the second well 1013 is small.

[0063] The first drain region 106d and the first source region 106s have the same doping concentration of the first conductive type ions, the second well 1013 and the first well 1011 have the same doping concentration of the second conductive type ions, and the body region 107 in the second well 1013 and the body region 107 in the first well 1011 have the same doping concentration of the second conductive type ions. The doping concentration of the second conductive type ions in the inversion lightly doped region 106 is lower than the doping concentration of the second conductive type ions in the body region 107.

[0064] The doping ion concentration of the first conductive type ions in the drift region 1012 is less than the doping ion concentration of the first conductive type ions in the first drain region 106d, thereby forming a high resistance layer between the first source region 106s and the first drain region 106d, thereby playing a buffering role between the channel and the first drain region 106d, which is conducive to weakening the short channel effect of the LDMOS device, improving the breakdown voltage between the first source region 106s and the first drain region 106d, and reducing the parasitic capacitance between the first source region 106s and the first drain region 106d. Wherein, when the LDMOS device is an N-type device, the first conductive type is N-type, and the second conductive type is P-type. Accordingly, the drift region 1012 is an N-type drift region, and the N-type ions doped therein may include at least one of phosphorus (P), arsenic (As) and antimony (Sb).

[0065] The portion of the first well 1011 covered by the first gate structure is used as an effective channel region. When the drift region 1012 is N-type, the first well 1011 is a P-type well (PW), and the P-type ions doped therein may include at least one of boron (B), gallium (Ga) and indium (In).

[0066] In an example, see Figure 2 The inversion lightly doped region 106 has a uniform doping concentration of the second conductive type ions along the direction from the first gate structure to the first drain region 106d, which is used to adjust the electric field at the corner below the field plate 109, increase the breakdown voltage of the LDMOS device, and improve the hot carrier injection (HCI) effect.

[0067] In another example, see Figure 3 , the doping concentration of the second conductive type ions in the inversion lightly doped region 106 along the direction from the first gate structure to the first drain region 106d can be gradually reduced in any suitable manner, thereby further adjusting the electric field below the field plate 109 by utilizing the gradient distribution of the doping concentration, and improving the breakdown voltage of the LDMOS device. For example, by gradually reducing the depth of the bottom of the inversion lightly doped region 106 along the direction from the first gate structure to the first drain region 106d, the doping concentration of the second conductive type ions in the inversion lightly doped region 106 along the direction from the first gate structure to the first drain region 106d can be gradually reduced. In addition, the inversion lightly doped region 106 is not connected to the first drain region 106d, thereby ensuring the modulation effect of the field plate 109 on the electric field of the drift region 1012.

[0068] Please refer to Figure 7 In one example, the substrate 100 further has a medium voltage CMOS device region (MVCMOS), and the inversion lightly doped region 106 is formed together with a lightly doped drain region of the second conductivity type of the medium voltage CMOS device region.

[0069] The first gate structure is formed on the drift region 1012 between the first source region 106s and the inversion lightly doped region 106, and includes a gate oxide layer 103 and a gate 104 stacked in sequence. Along the width direction of the gate 104, there is a corresponding spacing distance between the first drain region 106s and the first gate structure to improve the withstand voltage performance of the LDMOS device.

[0070] The sidewall is formed on the sidewall of the first gate structure, and may be a single-sided sidewall or a composite sidewall formed by multiple film layers, for example, a double-layer sidewall formed by a silicon oxide layer 1051 and a silicon nitride layer 1052. In other embodiments, the sidewall may also be an ONO structure consisting of a silicon oxide (O) layer, a silicon nitride (N) layer, and a silicon oxide (O) layer stacked sequentially from the inside to the outside.

[0071] The barrier layer 108 covers the drift region 1012, the inversion lightly doped region 106 and the sidewall between the first gate structure and the first drain region 106d, and one end of the barrier layer 108 extends to a portion of the top of the gate 104 of the first gate structure, and the other end may extend to a portion of the top of the first drain region 106d, or may be spaced from the first drain region 106d. The material of the barrier layer 108 may include at least one layer of silicon oxide, silicon nitride, and silicon oxynitride, for example, a double-layer film (ON) structure or a four-layer film (ONON) structure composed of alternately stacked silicon oxide and silicon nitride.

[0072] The field plate 109 is formed on the barrier layer 108, and the inversion lightly doped region 106 is located below the bottom of the field plate 109. The material of the field plate 109 may include at least one of metal silicide and metal. The field plate 109 can generate a superposition of a vertical electric field and a horizontal electric field on the drift region 1012 between the first gate structure and the first drain region 106d, so that the electric field distribution in the drift region 1012 is more uniform, thereby improving the breakdown voltage of the LDMOS device.

[0073] In an example, see Figures 2 to 4 , the field plate 109 is entirely located above the barrier layer 108 and is not in direct contact with the drift region 1012 .

[0074] In other examples, when the interval between the first drain region 106d and the first gate structure is large and the coverage width of the blocking layer 108 is small, the field plate 109 may also extend from the blocking layer 108 to the drift region 1012 exposed by the blocking layer 108 (which is also a part of the drift region 1012 between the first gate structure and the first drain region 106d), and directly contact the drift region 1012 through the metal silicide, thereby reducing the contact resistance between the field plate 109 and the drift region 1012, improving the modulation effect of the field plate 109 on the electric field of the drift region 1012, and improving the breakdown voltage of the LDMOS device.

[0075] Please refer to Figure 4 In one example, the substrate 100 further includes a second conductive type base (Sub) 1000, a first conductive type buried layer (NBL) 1017, and a second conductive type epitaxial layer (PEPI) 1016 stacked in sequence from bottom to top, and the drift region 1012, the first well 1011, and the second well 1013 are all formed on the upper part of the epitaxial layer 1016. Further optionally, an isolation region (P dopedregion) 1015 of the second conductive type is also formed in the epitaxial layer 1016 at the bottom of the drift region 1012 and the first well 1011. In one example, the top of the isolation region 1015 is connected to the drift region 1012 and the first well 1011 at the same time, and the side wall is connected to the second well 1013 (such as Figure 4 As shown in FIG. 1 ), the isolation region 1015, the first well 1011, and the second well 1013 together form a P-type region that surrounds and isolates the sidewalls and bottom of the drift region 1012. In another example, as shown in FIG. Figure 6 As shown, the top of the isolation region 1015 is connected to the drift region 1012 and the first well 1011 at the same time, and there is an epitaxial layer 1016 between the side wall and the second well 1013, so that the isolation region 1015, the first well 1011 and the second well 1013, and the epitaxial layer 1016 between the isolation region 1015 and the second well 1013 together constitute an isolated P-type region surrounding the side wall and bottom of the drift region 1012.

[0076] Further optionally, a third well 1014 of the first conductivity type is formed in the epitaxial layer 1016 outside the second well 1013, the bottom of the third well 1014 is connected to the buried layer 1017, and a first conductivity type ion heavily doped region 111 is formed in the surface layer of the third well 1014, and the doping concentration of the first conductivity type ions in the ion heavily doped region 111 is the same as that of the first drain region 106s. The first well 1011 and the drift region 1012 can be connected in the lateral direction, the third well 1014 and the second well 1013 can be connected in the lateral direction, and the second well 1013 and the drift region 1012 can be connected in the lateral direction.

[0077] Alternatively, please refer to Figure 4 A lightly doped region (NLDD) 110 of the first conductive type is also formed in the first well 1011 between the first source region 106s and the first gate structure, and the doping concentration of the first conductive type ions in the lightly doped region 110 is lower than the doping concentration of the first conductive type ions in the first source region 106s.

[0078] In an example, see Figures 6 to 10 The substrate 100 also has a medium voltage CMOS device region, wherein the medium voltage CMOS device region includes a medium voltage PMOS device region and a medium voltage NMOS device region, wherein an N-type well (MNW, such as Fig. 9201 in the figure), a P-type well (MPW, as shown in FIG. 201 ) is formed in the medium voltage NMOS device region. Fig. 9 202 in the figure), a second gate structure (not marked) is formed on the medium voltage PMOS device region, a third gate structure (not marked) is formed on the medium voltage NMOS device region, and a second source region (as shown in FIG. 202 ) is formed in the medium voltage PMOS device region on both sides of the second gate structure. Fig. 9 204s in FIG. 1 ) and the second drain region (as shown in FIG. Fig. 9 204d in FIG), a third source region (as shown in FIG. 204d ) is formed in the medium voltage NMOS device region on both sides of the third gate structure. Fig. 9 205s in FIG. 205) and the third drain region (as shown in FIG. Fig. 9 205d in the figure). When in this embodiment, the first conductivity type is N-type and the second conductivity type is P-type, the second well 1013 and the P-type well 202 of the medium voltage NMOS device region are formed by the same P-type well ion implantation process, the third well 1014 and the N-type well 201 of the medium voltage PMOS device region are formed by the same N-type well ion implantation process, the inverted lightly doped region 106 and the lightly doped drain region 203 of the medium voltage PMOS device region are formed by the same P-type LDD implantation process, and the lightly doped region 110 and the lightly doped drain region 206 of the medium voltage NMOS device region are formed by the same N-type LDD implantation process. The second source region 204s and the second drain region 204d of the medium voltage PMOS device region, as well as the body region 107 in the first well 1011 and the body region 107 in the second well 1013 of the LDMOS device region are formed by the same P-type source and drain ion implantation. The third source region 205s, the third drain region 205d of the medium voltage NMOS device region and the first source region 106s, the first drain region 106d and the heavily ion doped region 111 of the LDMOS device region are formed by the same P-type source and drain ion implantation.

[0079] Further, in this example, please refer to Fig.10 The semiconductor device further includes an interlayer dielectric layer 112 and a plurality of contact plugs 113. The interlayer dielectric layer 112 buries the substrate 100 and the film layer above the CMOS device region and the LDMOS device region. Each contact plug 113 penetrates the interlayer dielectric layer 112 and the bottom thereof is electrically connected to a corresponding gate, source region or drain region. The field plate 109 is formed together with the process of forming each contact plug 113.

[0080] In the semiconductor device of this embodiment, an inversion lightly doped region different from the drift region is formed in the drift region below the field plate of the LDMOS device region and close to the first drain region, thereby adjusting the electric field at the corner below the field plate through the inversion lightly doped region, thereby increasing the breakdown voltage of the LDMOS device and facilitating improving the HCI (hot carrier injection) effect.

[0081] Based on the same invention concept, please refer to Figure 5 An embodiment of the present invention further provides a method for manufacturing a semiconductor device, which can be used to manufacture the semiconductor device of the present invention. The manufacturing method comprises the following steps:

[0082] S1, providing a substrate having an LDMOS device region, and forming a laterally distributed drift region of a first conductivity type and a first well of a second conductivity type in the LDMOS device region;

[0083] S2, forming a required first gate structure on the LDMOS device region;

[0084] S3, implanting lightly doped ions of the second conductivity type into a designated area of ​​the drift region close to the first drain region to form, so as to form an inversion lightly doped region;

[0085] S4, forming a sidewall spacer on the sidewall of the first gate structure;

[0086] S5, performing source-drain ion implantation on the LDMOS device region using first conductivity type ions to form a first drain region of the first conductivity type in the drift region, and simultaneously forming a first source region in the first well, wherein the first source region and the first drain region are located on both sides of the inversion lightly doped region, and the doping concentration of the second conductivity type ions in the inversion lightly doped region is lower than the doping concentration of the first conductivity type ions in the first source region;

[0087] S6, forming a patterned barrier layer, wherein the barrier layer covers the drift region, the inversion lightly doped region, and the sidewall between the first gate structure and the first drain region and extends onto a portion of the top of the first gate structure;

[0088] S7, depositing an interlayer dielectric layer on the barrier layer and the device surface exposed thereon, and forming a plurality of contact plugs in the interlayer dielectric layer through a contact plug process, and simultaneously forming a field plate required for the LDMOS device region, wherein the inverted lightly doped region is located below the bottom of the field plate.

[0089] This embodiment takes the substrate having a CMOS device region and an LDMOS device region, the first conductivity type being N-type, the second conductivity type being P-type, and the BCD process as an example to explain in detail the method for manufacturing the semiconductor device of this embodiment. In other embodiments, as required, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0090] Please refer to Figure 6 In step S1, the step of providing a substrate 100 includes:

[0091] First, a P-type substrate 1000 is provided. The substrate 1000 can be any suitable semiconductor substrate material, such as silicon, silicon on insulator, germanium, silicon carbide, silicon germanium, etc., and can also be a substrate material with a semiconductor epitaxial layer such as silicon carbide epitaxially grown on the surface.

[0092] Next, an N-type buried layer (NBL) injection region of the substrate 1000 is defined by a photomask, and then N-type ions such as antimony (Sb) are implanted into the surface layer of the N-type buried layer (NBL) injection region of the substrate 1000 to form an N-type buried layer 1017 in the surface layer of the substrate 1000. Then, a P-type buried layer (PBL) injection region of the substrate 1000 is defined by a photomask, and P-type ions such as boron (B) are implanted into the surface layer of the P-type buried layer (PBL) injection region of the substrate 1000 to form a P-type buried layer 200 in the surface layer of the substrate 1000.

[0093] Then, a P-type epitaxial layer 1016 is formed on the N-type buried layer 1017 and the P-type buried layer 200 through an epitaxial growth process.

[0094] Afterwards, a device isolation structure 102 can be formed in the P-type epitaxial layer 1016 through any suitable device isolation process such as a shallow trench isolation process or a local field oxygen isolation process to define a CMOS device area and a LDMOS device area, and corresponding local isolation can be achieved in the CMOS device area and the LDMOS device area. For example, a medium-voltage NMOS device area and a medium-voltage PMOS device area can be defined in the CMOS device area through the corresponding device isolation structure 102.

[0095] In addition, before or after forming the device isolation structure 102, the required P-type well 202 is formed in the P-type epitaxial layer 1016 of the medium voltage NMOS device region, the required N-type well 201 is formed in the P-type epitaxial layer 1016 of the medium voltage PMOS device region, and the drift region 1012, the first well (HVPB) 1011, the second well 1013, and the third well 1014 are formed in the P-type epitaxial layer 1016 of the LDMOS device region. The P-type well 202 and the second well 1013 can be formed by using the same photomask and the same P-well ion implantation process, or by using different photomasks and different P-well ion implantation processes; the third well 1014 and the N-type well 201 can be formed by using the same photomask and the same N-well ion implantation process, or by using different photomasks and N-well ion implantation processes. The first well (HVPB) 1011 can be formed by using a single photomask and a P-well ion implantation process, and divides the LDMOS device region into two LDMOS transistor regions.

[0096] Optionally, please continue to refer to Figure 6Before forming the drift region 1012, a corresponding P-type ion implantation process is performed on the P-type epitaxial layer 1016 by using the same photomask used to manufacture the drift region 1012, so as to form an isolation region (Pdoped region) 1015 of the second conductivity type in the P-type epitaxial layer 1016 deeper than the drift region 1012. The top of the isolation region 1015 can be connected to the bottom of the drift region 1012 and the bottom of the first well 1011 to be formed subsequently. Therefore, after forming the drift region 1012, the first well 1011, the second well 1013, and the third well 1014, the first well 1011 and the isolation region 1016 thereunder, as well as the P-type epitaxial layer around the isolation region 1016, form a P-type isolation ring structure, which surrounds the bottom and sidewalls of the drift region 1012, thereby protecting and electrically isolating the drift region 1012.

[0097] For further information, please refer to Figure 6 The bottoms of the third wells 1014 of the two LDMOS transistor regions are connected to the top of the buried layer 1017, so that the third well 1014 and the buried layer 1017 form an N-type isolation ring structure, which electrically isolates the LDMOS device region from the surrounding medium-voltage CMOS device region.

[0098] It should be understood that the ion doping concentrations of the drift region 1012, each well, isolation region and buried layer need to be reasonably designed according to the withstand voltage requirements and on-resistance and other performance requirements of the LDMOS device, and the present invention does not impose specific limitations on this.

[0099] Please continue to refer to Figure 6 In step S2, a gate oxide layer 103 may be formed on the substrate 10, and polysilicon deposition, photolithography, and etching may be performed to form a plurality of discrete gates 104. In this embodiment, the gate 104 on the LDMOS device region overlaps with the surface of the drift region 1012 and the first well 1011, the gate 104 formed in the medium voltage NMOS device region is located on the P-type well 202, and the gate 104 formed in the medium voltage PMOS device region is located on the N-type well 201, thereby forming an effective channel region.

[0100] In an example, see Figure 7In step S3, first, a photoresist layer 301 is coated on the gate 104 and the gate oxide layer 103; then, a mask (not shown) in which each light-transmitting area is a fully light-transmitting area is used to expose the photoresist layer 301; then, the exposed photoresist layer 301 is developed to form a patterned photoresist layer, so as to define a P-type LDD (lightly doped drain) ion implantation area in the designated area of ​​the drift region 1012 of the medium voltage PMOS device region and the LDMOS device region near the first drain region to be formed, and the patterned photoresist layer masks other areas; then, the patterned photoresist layer is used as a mask to perform P-type LDD (lightly doped drain) ion implantation on the designated area of ​​the medium voltage PMOS device region and the drift region 1012, thereby forming a lightly doped drain region 203 located in the medium voltage PMOS device region and an inverted lightly doped region 106 located in the drift region 1012. In this example, the inverted lightly doped region 106 has a uniform doping concentration in the lateral direction. Afterwards, the photoresist layer 301 is removed by any suitable stripping process such as wet stripping or dry stripping.

[0101] In another example, see Fig.11 In step S3, first, a photoresist layer 301 is coated on the gate electrode 104 and the gate oxide layer 103; then, a half-tone mask 400 is used to expose the photoresist layer 301, wherein the light-transmitting area corresponding to the medium-voltage PMOS device area is a fully light-transmitting area (100% light-transmitting), and the light-transmitting area corresponding to the designated area of ​​the drift region 1012 is a semi-light-transmitting area; then, the exposed photoresist layer 301 is developed to form a patterned photoresist layer, wherein the patterned photoresist layer masks other areas and is formed in the drift region 1012 of the medium-voltage PMOS device area and the LDMOS device area near the designated area where the first drain region is to be formed. In the embodiment, the region for P-type LDD (lightly doped drain) ion implantation is defined, and the opening defining the implantation region of the medium voltage PMOS device region is fully opened, while the opening 301a defining the implantation region of the drift region 1012 is not fully opened at the bottom due to incomplete exposure, which will have a blocking effect on the subsequent P-type LDD ion implantation; thereafter, the patterned photoresist layer is used as a mask to perform P-type LDD (lightly doped drain) ion implantation on the designated region of the medium voltage PMOS device region and the drift region 1012, thereby forming a lightly doped drain region 203 located in the medium voltage PMOS device region and an inversion lightly doped region 106 located in the drift region 1012. In this example, since the opening 301a defining the implantation region of the drift region 1012 in the patterned photoresist layer is not fully exposed and the bottom is not fully opened, it has a blocking effect on the P-type LDD ion implantation, resulting in a gradual decrease in the doping concentration of the inversion lightly doped region 106 along the direction from the gate 104 of the LDMOS device region to the first drain region to be formed. Afterwards, the photoresist layer 301 is removed by any suitable stripping process such as wet stripping or dry stripping.

[0102] Please refer to Figure 8 Optionally, before or after executing step S3, a photoresist layer 302 is first coated on the gate 104 and the gate oxide layer 103; then, a mask (not shown) in which each light-transmitting area is a fully light-transmitting area is used to expose the photoresist layer 302; then, the exposed photoresist layer 302 is developed to form a patterned photoresist layer 302, so as to define an N-type LDD (lightly doped drain) ion implantation area in the first well 1011 of the medium-voltage NMOS device area and the LDMOS device area, and the patterned DE photoresist layer 302 masks other areas; then, using the patterned photoresist layer 302 as a mask, N-type LDD (lightly doped drain) ion implantation is performed on the medium-voltage NMOS device area and the first well 1011, thereby forming a lightly doped drain area 206 located in the medium-voltage NMOS device area and a lightly doped area 110 located in the surface layer of the first well 1011. Afterwards, the photoresist layer 302 is removed by any suitable stripping process such as wet stripping or dry stripping.

[0103] Please refer to Fig. 9 In step S4, the gate oxide layer 103 is first etched, so that the remaining gate oxide layer 103 on the medium voltage PMOS device area and the gate 104 thereon form a second gate structure, and the remaining gate oxide layer 103 on the medium voltage NMOS device area and the gate 104 thereon form a third gate structure; then, a dielectric material deposition and etching process is performed to form a sidewall 105 covering the gate 104 and the sidewall of the gate oxide layer 103. The material of the sidewall 105 may include one or more dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride, and may be a single-layer structure or a stacked-layer structure.

[0104] Please continue to refer to Fig. 9 In step S5, the corresponding regions of the medium voltage PMOS device region and the LDMOS device region are masked, and the third source region 205s and the third drain region 205d of the medium voltage NMOS device region, the first source region 106s and the first drain region 106d of the LDMOS device region, and the heavily ion-doped region 111 are formed by an N-type source-drain ion implantation process. The corresponding regions of the medium voltage NMOS device region and the LDMOS device region are masked, and the second source region 204s and the second drain region 204d of the medium voltage PMOS device region and the body region 107 of the LDMOS device region are formed by a P-type source-drain ion implantation process. The N-type source-drain ion implantation process may be performed first, and then the P-type source-drain ion implantation process may be performed, or the P-type source-drain ion implantation process may be performed first, and then the N-type source-drain ion implantation process may be performed, and the present invention does not specifically limit this.

[0105] Please continue to refer to Fig. 9In step S6, a patterned barrier layer 108 is formed on the LDMOS device region by any suitable process such as dielectric material deposition, photolithography and etching. The barrier layer 108 covers the drift region 1012, the inversion lightly doped region 106 and the sidewall between the first gate structure and the first drain region 106d, and one end of the barrier layer 108 extends to the top of the gate 104 of the first gate structure, and the other end can extend to the top of the first drain region 106d, or there can be a gap between the first drain region 106d. The material of the barrier layer 108 is different from the outer layer material of the sidewall 105, and can include one or more dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be a single-layer structure or a stacked structure. The barrier layer 108 also exposes the surface of other regions.

[0106] Please refer to Fig.10 In step S7, a contact hole etching stop layer (not shown) and an interlayer dielectric layer 112 (which may be a low-k dielectric material with a dielectric constant k lower than that of silicon oxide) are first formed by any appropriate deposition process; then, the interlayer dielectric layer 112 and the contact hole etching stop layer are etched by photolithography and etching processes to form a plurality of required contact holes (not shown) and field plate holes (not shown). These contact holes respectively expose: the top of the third source region 205s, the top of the gate 104 of the medium voltage PMOS device region, the top of the third drain region 205d, the top of the second source region 204s, the top of the gate 104 of the medium voltage NMOS device region, the top of the second drain region 204d, the top of each heavily doped ion region 111 of the LDMOS device region, the top of each body region 107 of the LDMOS device region, the top of the first source region 106s, and the top of the first drain region 106d. Afterwards, metal silicide may be formed in the contact holes and field plate holes by a metal silicide process to reduce contact resistance. Then, metal is deposited and chemical mechanical polishing is performed to form contact plugs 113 in each contact hole and field plates 109 in the field plate holes.

[0107] The manufacturing method of the semiconductor device of this embodiment implants the LDMOS device region at the same time as the lightly doped drain region implantation (LDD implantation) of the CMOS device region to form the required inversion lightly doped region under the field plate. Compared with the prior art, only one CMOS device mask needs to be modified, and no additional mask needs to be added, which is low in cost. Moreover, the electric field at the corner under the field plate can be adjusted through the inversion lightly doped region to increase the breakdown voltage of the LDMOS device.

[0108] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A substrate having an LDMOS device region, wherein a drift region of a first conductivity type and a first well of a second conductivity type are formed in the substrate of the LDMOS device region, wherein a second conductivity type inversion lightly doped region and a first conductivity type first drain region are formed in the drift region, wherein a first source region is formed in the first well, wherein the first source region and the first drain region are located on both sides of the inversion lightly doped region, and wherein a doping concentration of second conductivity type ions in the inversion lightly doped region is lower than a doping concentration of first conductivity type ions in the first drain region; A first gate structure is formed on the drift region between the first source region and the inversion lightly doped region; A sidewall spacer formed on a sidewall of the first gate structure; a barrier layer covering the drift region, the inversion lightly doped region and the sidewall between the first gate structure and the first drain region and extending onto a portion of the top of the first gate structure; A field plate is formed on the barrier layer, and the inversion lightly doped region is located below the bottom of the field plate.

2. The semiconductor device according to claim 1, wherein The doping concentration of the inversion lightly doped region along the direction from the first gate structure to the first drain region is uniform, or the doping concentration along the direction from the first gate structure to the first drain region gradually decreases.

3. The semiconductor device according to claim 1, wherein The first drain region is not connected to the inversion lightly doped region; and / or the substrate further has a medium voltage CMOS device region, and the inversion lightly doped region is formed together with the second conductivity type lightly doped drain region of the medium voltage CMOS device region.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that Also includes at least one of the following (1) to (7): (1) The substrate comprises a base, a buried layer of a first conductivity type, and an epitaxial layer of a second conductivity type stacked in sequence from bottom to top, the drift region and the first well are both formed in the epitaxial layer, and an isolation region of the second conductivity type is also formed in the epitaxial layer below the drift region, and the top of the isolation region is connected to the bottom of the first well and the bottom of the drift region; (2) a second well of a second conductivity type is further formed in the LDMOS device region, the second well being laterally distributed outside the drift region along a direction from the first gate structure to the first drain region, a body region of a second conductivity type being formed in both the second well and the first well, the body region in the second well being isolated from the first drain region by a corresponding device isolation structure, and the body region in the first well being connected to the first source region; (3) a lightly doped region of the first conductivity type is further formed in the first well between the first source region and the first gate structure, and a doping concentration of the first conductivity type ions in the lightly doped region is lower than a doping concentration of the first conductivity type ions in the first source region; (4) a third well of the first conductivity type is further formed in the boundary region of the LDMOS device region, and an ion heavily doped region of the first conductivity type is formed in the third well; (5) The substrate further comprises a medium voltage CMOS device region, wherein the medium voltage CMOS device region comprises a medium voltage PMOS device region and a medium voltage NMOS device region, wherein an N-type well is formed in the medium voltage PMOS device region, wherein a P-type well is formed in the medium voltage NMOS device region, wherein a second gate structure is formed on the medium voltage PMOS device region, wherein a third gate structure is formed on the medium voltage NMOS device region, wherein a second source region and a second drain region are formed in the medium voltage PMOS device region on both sides of the second gate structure, and wherein a third source region and a third drain region are formed in the medium voltage NMOS device region on both sides of the third gate structure; (6) The first conductivity type is N-type, the second conductivity type is P-type, the drift region is an N-type drift region, and the inversion lightly doped region is a P-type lightly doped region; (7) The semiconductor device further includes an interlayer dielectric layer and a plurality of contact plugs, wherein the interlayer dielectric layer buries the first source region and the first drain region, the barrier layer, the sidewall, the first gate structure and the substrate, and the contact plugs penetrate the interlayer dielectric layer and are electrically connected at their bottoms to the first source region or the first drain region or the first gate structure.

5. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate having an LDMOS device region, forming a laterally distributed drift region of a first conductivity type and a first well of a second conductivity type in the LDMOS device region; forming a desired first gate structure on the LDMOS device region; Performing lightly doped ion implantation of the second conductivity type into a designated area of ​​the drift region close to the first drain region to be formed, so as to form an inversion lightly doped region; forming a sidewall spacer on a sidewall of the first gate structure; Performing source-drain ion implantation on the LDMOS device region using first conductive type ions to form a first conductive type first drain region in the drift region, and forming a first source region in the first well, wherein the first source region and the first drain region are located on both sides of the inversion lightly doped region, and the doping concentration of the second conductive type ions in the inversion lightly doped region is lower than the doping concentration of the first conductive type ions in the first drain region; forming a patterned barrier layer, the barrier layer covering the drift region, the inversion lightly doped region and the sidewall between the first gate structure and the first drain region and extending onto a portion of the top of the first gate structure; An interlayer dielectric layer is deposited on the barrier layer and the device surface exposed thereon, and a plurality of contact plugs are formed in the interlayer dielectric layer by a contact plug process, and a field plate required for the LDMOS device region is formed at the same time, wherein the inverted lightly doped region is located below the bottom of the field plate.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The substrate also has a medium voltage CMOS device region, and the steps of forming the inversion lightly doped region include: Coating a photoresist layer on the first gate structure and the substrate; The photoresist layer is exposed by using a mask in which each light-transmitting area is a fully light-transmitting area or a half-tone mask, wherein the light-transmitting area of ​​the half-tone mask corresponding to the medium-voltage CMOS device area is a fully light-transmitting area, and the light-transmitting area corresponding to the designated area is a semi-light-transmitting area; Developing the exposed photoresist layer to form a patterned photoresist layer to define an area in the medium voltage CMOS device area and the designated area where ion implantation of a lightly doped drain region of the second conductivity type is to be performed; Using the patterned photoresist layer as a mask, ion implantation of a lightly doped drain region of a second conductivity type is performed on the medium voltage CMOS device region and the designated region, so as to form the lightly doped drain region of the medium voltage CMOS device region and the inversion lightly doped region in the designated region at the same time; Among them, when a mask in which each light-transmitting area is a fully light-transmitting area is used, the doping concentration of the inversion lightly doped area along the direction from the first gate structure to the first drain area is uniform; when a half-tone mask is used, the doping concentration of the inversion lightly doped area along the direction from the first gate structure to the first drain area gradually decreases.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: The first drain region is not connected to the inversion lightly doped region.

8. The method for manufacturing a semiconductor device according to claim 5, wherein: The substrate also has a medium voltage CMOS device region, and the manufacturing method further includes at least one of the following (1) to (6): (1) after forming the first gate structure and before or after implanting lightly doped ions of the second conductivity type into the designated region, implanting lightly doped ions of the first conductivity type into a region of the first well close to the first gate structure, so as to form a corresponding lightly doped region of the first conductivity type in the first well between the first source region and the first gate structure, wherein the doping concentration of the first conductivity type ions in the lightly doped region is lower than the doping concentration of the first conductivity type ions in the first source region; (2) while forming a medium-voltage well of the second conductivity type in the medium-voltage CMOS device region, a second well of the second conductivity type is also formed in the LDMOS device region, the second well being laterally distributed outside the drift region along a direction from the first gate structure to the first drain region, and while forming a source region and a drain region of the second conductivity type in the medium-voltage CMOS device region, a body region of the second conductivity type is formed in both the second well and the first well, the body region in the second well being isolated from the first drain region by a corresponding device isolation structure, and the body region in the first well being connected to the first source region; (3) while forming the first gate structure on the LDMOS device region, a required gate structure is also formed on the medium voltage CMOS device region, and while forming a sidewall on the sidewall of the first gate structure, a sidewall is also formed on the sidewall of the gate structure in the medium voltage CMOS device region; (4) while implanting lightly doped ions of the second conductivity type into the designated area to form an inversion lightly doped area, also implanting lightly doped ions into a corresponding area of ​​the medium voltage CMOS device area to form a lightly doped drain area of ​​the second conductivity type required by the medium voltage CMOS device area; (5) performing source and drain ion implantation on the LDMOS device region using ions of the first conductivity type, and also performing source and drain ion implantation on the medium voltage CMOS device region, so as to form source and drain regions required by the medium voltage CMOS device region; (6) While forming a medium-voltage well of the first conductivity type in the medium-voltage CMOS device region, a third well of the first conductivity type is also formed in a boundary region of the LDMOS device region.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: Also includes at least one of the following (1) to (3): (1) The substrate comprises a base, a buried layer of a first conductivity type, and an epitaxial layer of a second conductivity type stacked in sequence from bottom to top, and the drift region and the first well are both formed in the epitaxial layer; (2) an isolation layer of a second conductivity type is further formed in the substrate below the drift region, and the bottom of the first well and the bottom of the drift region are both connected to the top of the isolation layer; (3) While performing source-drain ion implantation on the LDMOS device region using first conductivity type ions, also performing source-drain ion implantation on the first conductivity type third well in the boundary region of the LDMOS device region to form a first conductivity type ion heavily doped region in the third well.

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