Cellular structure, preparation method thereof and metal oxide semiconductor field effect transistor

Abstract

The invention relates to a cellular structure, a preparation method thereof and a metal oxide semiconductor field effect transistor. The cellular structure includes: a current spreading layer; the two well regions are located on the side, away from the epitaxial layer, of the current expansion layer in the first direction, and the two well regions are separated by the current expansion layer in the second direction; the two first injection regions are arranged in the first direction, each first injection region is located on the side, away from the current expansion layer, of the corresponding well region, and the two first injection regions are separated by the current expansion layer in the second direction; the groove comprises a groove bottom and two opposite side walls, the groove bottom is located in the two well regions and the current expansion layer between the two well regions, and each side wall is located in the corresponding partial well region and the corresponding first injection region; the gate oxide layer is located in the groove; the grid electrode is positioned on a grid oxide layer in the groove and is also covered by the grid oxide layer; according to the cellular structure, the well region is expanded to the corner of the grid, so that the electric field aggregation of the gate oxide layer at the bottom corner of the groove is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of power electronic devices, and in particular to a cell structure and a preparation method thereof, and a metal oxide semiconductor field effect transistor. Background Art

[0002] In the field of power electronic devices, Silicon Carbide (SiC) power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices are considered to be the most mature and promising SiC power devices due to their high breakdown voltage, high switching speed, high thermal conductivity, low on-resistance, low switching loss and low driving power. In the field of high voltage and low power consumption, vertical MOSFET (VDMOS) is more commonly used. Common SiC VDMOS are mainly divided into two types: flat gate MOSFET and trench MOSFET.

[0003] Flat-gate MOSFETs have been widely used in the automotive and photovoltaic industries. Although the flat-gate MOSFET manufacturing process is mature and the device reliability is high, the problems of flat-gate MOSFETs include: 1) the SiC / SiO2 interface is rough and has many defects; 2) the channel uses the 4H-SiC (0001) crystal plane with low mobility.

[0004] Trench MOSFET, because the channel is located on the side wall, perpendicular to the device surface, through different channel crystal planes to achieve a significant increase in mobility, and eliminate the JFET region resistance of planar MOSFET, so that the on-resistance is further reduced, reducing interface losses. However, because the trench MOSFET is prone to electric field concentration effect at the corner of the gate trench, it is easy to break down the thin layer of gate oxide at the corner of the trench, causing gate-source conduction, which reduces the reliability of the trench MOSFET. Summary of the invention

[0005] Based on this, it is necessary to provide a cell structure and a preparation method thereof, and a metal oxide semiconductor field effect transistor that can improve the reliability of trench MOSFET in order to solve the above technical problems.

[0006] In a first aspect, the present application provides a cellular structure, comprising:

[0007] substrate;

[0008] an epitaxial layer, located on one side of the substrate;

[0009] A current spreading layer, located on a side of the epitaxial layer away from the substrate;

[0010] Two well regions, each of which is located on a side of the current spreading layer away from the epitaxial layer along a first direction, and the two well regions are separated by the current spreading layer along a second direction;

[0011] Two first injection regions, each of which is located at a side of the corresponding well region away from the current spreading layer along a first direction, and the two first injection regions are separated by the current spreading layer along a second direction;

[0012] Two second injection regions, each of which is located at a side of the current spreading layer away from the epitaxial layer along the first direction, and each of which is located at a side of the corresponding well region and the first injection region away from the current spreading layer along the second direction;

[0013] A trench, comprising a trench bottom and two opposite side walls along the second injection region pointing to the first injection region, wherein the trench bottom is located in the two well regions and in the current spreading layer between the two well regions, and each of the side walls is located in a corresponding part of the well region and in a corresponding first injection region;

[0014] A gate oxide layer is located in the trench;

[0015] A gate, the gate oxide layer being located in the trench, wherein the gate is also covered by the gate oxide layer;

[0016] The first direction is perpendicular to the substrate, and the second direction is parallel to the plane where the substrate is located.

[0017] The trench of the cell structure comprises a trench bottom and two opposite side walls pointing in the direction of the second injection region to the first injection region, the trench bottom is located in the two well regions and in the current expansion layer between the two well regions, each of the side walls is located in the corresponding part of the well region and in the corresponding first injection region, the gate oxide layer of the cell structure is located in the trench and covers the trench bottom and the two side walls, and the gate of the cell structure is located in the trench and covers the gate oxide layer; in this way, the cell structure expands the well region to the gate corner, thereby reducing the electric field concentration of the gate oxide layer at the bottom corner of the trench, and in the reverse direction Under bias, when the source-drain voltage is increased, the well region at the bottom corner of the trench is depleted, and the electric field distribution at the bottom of the trench is presented as an L-shaped well region modulation, thereby preventing the gate oxide layer electric field at the corner of the gate channel from reaching the peak value and breaking through the gate oxide layer. The embodiment of the present application thus improves the reliability of the trench MOSFET device; at the same time, by ion implantation below the trench to form a current expansion layer CSL, the current path in the vertical direction of the forward conduction path of the two well regions is prevented from being cut off, thereby eliminating the JEFT effect, so that the on-resistance is greatly reduced and the loss is reduced.

[0018] In one embodiment, it also includes:

[0019] a gate dielectric layer, located on a side of the gate away from the current spreading layer and covering a portion of each of the first injection regions;

[0020] A source electrode, located at a side of the gate dielectric layer away from the gate and covering each of the second injection regions and each of the exposed first injection regions;

[0021] The drain electrode is located on a side of the substrate away from the epitaxial layer.

[0022] In one of the embodiments, the ion implantation type of the current spreading layer is N-type.

[0023] In one of the embodiments, the ion implantation type of the well region is P type.

[0024] In one embodiment, the ion implantation type of the first implantation region is N-type, and the ion implantation type of the second implantation region is P-type.

[0025] In a second aspect, the present application further provides a metal oxide semiconductor field effect transistor, comprising the cell structure provided in the first aspect above.

[0026] In a third aspect, the present application also provides a method for preparing a cellular structure, comprising:

[0027] providing a substrate;

[0028] forming an epitaxial layer located on one side of the substrate;

[0029] forming a current spreading layer located on a side of the epitaxial layer away from the substrate;

[0030] forming two well regions, each of the well regions being located on a side of the current spreading layer away from the epitaxial layer along a first direction, and the two well regions being separated by the current spreading layer along a second direction;

[0031] forming two first injection regions, wherein each of the first injection regions is located at a side of the corresponding well region away from the current spreading layer along a first direction, and the two first injection regions are separated by the current spreading layer along a second direction;

[0032] forming two second injection regions, wherein each of the second injection regions is located at a side of the current spreading layer away from the epitaxial layer along the first direction, and each of the second injection regions is located at a side of the corresponding well region and the first injection region away from the current spreading layer along the second direction;

[0033] Forming a trench, comprising a trench bottom and two opposite side walls along the second injection region pointing to the first injection region, wherein the trench bottom is located in the two well regions and in the current spreading layer between the two well regions, and each of the side walls is located in a corresponding portion of the well region and in a corresponding first injection region;

[0034] forming a gate oxide layer and a gate, wherein the gate oxide layer is located in the trench, the gate is located in the gate oxide layer in the trench and the gate is also covered by the gate oxide layer;

[0035] The first direction is perpendicular to the substrate, and the second direction is parallel to the plane where the substrate is located.

[0036] In one embodiment, forming the groove comprises:

[0037] The trenches are etched using a plasma etching process.

[0038] In one embodiment, the forming of the gate oxide layer includes:

[0039] A gate oxide layer is formed by a dry oxygen oxidation process.

[0040] In one embodiment, forming the gate includes:

[0041] Polysilicon is deposited and ion implanted into the polysilicon to form a gate.

[0042] The above-mentioned cellular structure and its preparation method, and metal oxide semiconductor field effect transistor, wherein the cellular structure can be a cellular structure of a metal oxide semiconductor field effect transistor; an epitaxial layer and a current expansion layer are sequentially arranged on the substrate of the cellular structure; along the direction perpendicular to the substrate, each of the two well regions is located on the side of the current expansion layer away from the epitaxial layer, and along the direction parallel to the plane where the substrate is located, the two well regions are separated by the current expansion layer; along the direction perpendicular to the substrate, each of the two first injection regions is located on the side of the corresponding well region away from the current expansion layer, and along the direction parallel to the plane where the substrate is located, the two first injection regions are separated by the current expansion layer; along the direction perpendicular to the substrate, each of the two second injection regions is located on the side of the current expansion layer away from the epitaxial layer, and along the direction parallel to the plane where the substrate is located, each second injection region is located on the side of the corresponding well region and the first injection region away from the current expansion layer.

[0043] On this basis, the groove of the cellular structure includes a groove bottom and two opposite side walls along the second injection region pointing to the first injection region, the groove bottom is located in the two well regions and in the current expansion layer between the two well regions, each of the side walls is located in the corresponding part of the well region and in the corresponding first injection region, the gate oxide layer of the cellular structure is located in the groove, and the gate of the cellular structure is located in the gate oxide layer in the groove, wherein the gate is also covered by the gate oxide layer; in this way, the cellular structure expands the well region to the gate corner, thereby reducing the electric field concentration of the gate oxide layer at the bottom corner of the groove, Under reverse bias, when the source-drain voltage is increased, the well region at the bottom corner of the trench is depleted, and the electric field distribution at the bottom of the trench is presented as an L-shaped well region modulation, thereby preventing the gate oxide layer electric field at the corner of the gate channel from reaching the peak value and breaking through the gate oxide layer. The embodiment of the present application thus improves the reliability of the trench MOSFET device; at the same time, by ion implantation below the trench to form a current expansion layer CSL, the current path in the vertical direction of the forward conduction path of the two well regions is prevented from being cut off, thereby eliminating the JEFT effect, so that the on-resistance is greatly reduced and the loss is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0045] FIG1 is a schematic diagram of a cell structure in one embodiment;

[0046] Figure 2 This is a second schematic diagram of a cell structure in an embodiment;

[0047] FIG. 3 is a schematic flow chart of a method for preparing a cellular structure in one embodiment. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0050] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0051] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0052] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0053] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0054] The cell structure provided in the embodiments of the present application can be used to form a metal oxide semiconductor field effect transistor, for example, can be used to form a SiC trench MOSFET.

[0055] In an exemplary embodiment, referring to FIG1 , a cell structure is provided, which includes a substrate 110, an epitaxial layer 120, a current spreading layer 130, two well regions 140, two first injection regions 150, two second injection regions 160, a trench, a gate oxide layer 170, and a gate 180. The epitaxial layer 120 is located on one side of the substrate 110. The current spreading layer 130 is located on a side of the epitaxial layer 120 away from the substrate 110.

[0056] In the first direction, each well region 140 is located on a side of the current spreading layer 130 away from the epitaxial layer 120, and in the second direction, the two well regions 140 are separated by the current spreading layer 130. In the first direction, each first injection region 150 is located on a side of the corresponding well region 140 away from the current spreading layer 130, and in the second direction, the two first injection regions 150 are separated by the current spreading layer 130. In the first direction, each second injection region 160 is located on a side of the current spreading layer 130 away from the epitaxial layer 120, and in the second direction, each second injection region 160 is located on a side of the corresponding well region 140 and the first injection region 150 away from the current spreading layer 130.

[0057] The trench includes a trench bottom and two opposite side walls pointing in the direction of the second injection region 160 to the first injection region 150, the trench bottom is located in the two well regions 140 and in the current spreading layer 130 between the two well regions 140, and each side wall is located in the corresponding part of the well region 140 and in the corresponding first injection region 150. The gate oxide layer 170 is located in the trench. The gate 180 is located in the gate oxide layer 170 in the trench, wherein the gate 180 is also covered by the gate oxide layer 170. The first direction is perpendicular to the substrate 110, and the second direction is parallel to the plane where the substrate 110 is located.

[0058] The material of the substrate 110 may be SiC. Compared with traditional silicon (Si) materials, SiC has the advantages of wide bandgap, high critical breakdown electric field, large saturation drift velocity and high thermal conductivity. It is an ideal material for preparing high-voltage and high-power devices. It is widely used in high-efficiency, high-power and high-temperature power electronics technology and has become a research hotspot in current power semiconductor technology. Power MOSFET devices prepared based on SiC have the advantages of high current density, high breakdown voltage, low loss, good high-temperature characteristics and radiation resistance. Compared with traditional Si-based power MOSFET devices, they can simplify the topology of power electronic systems, reduce system volume and reduce power loss. Exemplarily, the substrate 110 is an N-type doped silicon carbide substrate 110.

[0059] The material of the epitaxial layer 120 may be silicon carbide, and the doping type of the epitaxial layer 120 includes N-type doping. The epitaxial layer 120 may be grown on one side of the substrate 110, and then ion implantation may be performed sequentially on the epitaxial layer 120 to sequentially form a current spreading layer 130 (CSL), two well regions 140, and two first implantation regions 150; then a plasma etching method may be used to etch a groove on the epitaxial layer 120, so that the two corners of the groove are located inside the well region 140; then a gate oxide layer 170 may be formed inside the groove by dry oxygen oxidation, and polysilicon may be deposited inside, and ion implantation may be performed on the polysilicon to form a gate 180 of a cellular structure; then two second implantation regions 160 may be formed by ion implantation.

[0060] In the embodiment of the present application, the cellular structure expands the well region 140 to the corner of the gate 180, thereby reducing the electric field concentration of the gate oxide layer 170 at the bottom corner of the trench. Under reverse bias, when the source-drain voltage is increased, the well region 140 at the bottom corner of the trench is depleted, and the electric field distribution at the bottom of the trench is presented as an L-shaped modulation of the well region 140, thereby preventing the gate oxide layer 170 electric field at the corner of the gate 180 channel from reaching a peak value and breaking through the gate oxide layer 170. The embodiment of the present application thus improves the reliability of the trench MOSFET device; at the same time, by forming an N-type current expansion layer 130CSL under the trench, the current path in the vertical direction of the forward conduction path of the two well regions 140 is prevented from being cut off, thereby eliminating the JEFT effect, so that the on-resistance is greatly reduced and the loss is reduced.

[0061] In an exemplary embodiment, referring to Figure 2 The cell structure further includes a gate dielectric layer 190, a source electrode 200 and a drain electrode 210. The gate dielectric layer 190 is located on a side of the gate 180 away from the current spreading layer 130 and covers a portion of each of the first injection regions 150. SiO2 and Si3N4 may be further deposited on the surface of the polysilicon to form a dielectric layer above the gate 180. The source electrode 200 is located on a side of the gate dielectric layer 190 away from the gate 180 and covers each of the second injection regions 160 and the exposed first injection regions 150. The drain electrode 210 is located on a side of the substrate 110 away from the epitaxial layer 120.

[0062] In an exemplary embodiment, the ion implantation type of the current spreading layer 130 is N-type.

[0063] In an exemplary embodiment, the ion implantation type of the well region 140 is P type.

[0064] In an exemplary embodiment, the ion implantation type of the first implantation region 150 is N-type, and the ion implantation type of the second implantation region 160 is P-type.

[0065] In an exemplary embodiment, a metal oxide semiconductor field effect transistor is further provided. The metal oxide semiconductor field effect transistor includes the cell structure provided in any of the above embodiments.

[0066] The metal oxide semiconductor field effect transistor and the cell structure provided in the embodiments of the present application belong to the same inventive concept, can solve the same technical problem, and thus achieve the same technical effect, that is, the groove of the cell structure includes a groove bottom and two opposite side walls along the second injection region pointing to the first injection region, the groove bottom is located in the two well regions and in the current expansion layer between the two well regions, each of the side walls is located in the corresponding partial well region and in the corresponding first injection region, the gate oxide layer of the cell structure is located in the groove and covers the groove bottom and the two side walls, and the gate of the cell structure is located in the groove and covers the gate oxide layer; in this way, the cell structure divides the well region The gate oxide layer is expanded to the corner of the gate, thereby reducing the electric field concentration of the gate oxide layer at the bottom corner of the trench. Under reverse bias, when the source-drain voltage is increased, the well region at the bottom corner of the trench is depleted, and the electric field distribution at the bottom of the trench is presented as an L-shaped well region modulation, thereby preventing the gate oxide layer electric field at the corner of the gate channel from reaching a peak value and breaking through the gate oxide layer. The embodiment of the present application thus improves the reliability of the trench MOSFET device; at the same time, by ion implantation below the trench to form a current expansion layer CSL, the current path in the vertical direction of the forward conduction path of the two well regions is prevented from being cut off, thereby eliminating the JEFT effect, so that the on-resistance is greatly reduced and the loss is reduced.

[0067] In an exemplary embodiment, referring to FIG3 , a method for preparing a cellular structure is also provided. The method can be used to prepare the cellular structure provided in any of the above embodiments. The method comprises:

[0068] S301, providing a substrate.

[0069] S302, forming an epitaxial layer located on one side of the substrate.

[0070] S303, forming a current spreading layer located on a side of the epitaxial layer away from the substrate.

[0071] S304, forming two well regions, along a first direction, each of the well regions is located on a side of the current spreading layer away from the epitaxial layer, and along a second direction, the two well regions are separated by the current spreading layer.

[0072] S305 , forming two first injection regions, wherein along a first direction, each of the first injection regions is located at a side of the corresponding well region away from the current spreading layer, and along a second direction, the two first injection regions are separated by the current spreading layer.

[0073] S306, forming two second injection regions, along the first direction, each of the second injection regions is located at a side of the current spreading layer away from the epitaxial layer, and along the second direction, each of the second injection regions is located at a side of the corresponding well region and the first injection region away from the current spreading layer.

[0074] S307, forming a groove, including a groove bottom and two opposite side walls along the second injection region pointing to the first injection region, the groove bottom is located in the two well regions and in the current expansion layer between the two well regions, and each of the side walls is located in the corresponding part of the well region and the corresponding first injection region.

[0075] Referring to FIG. 1 , the material of the epitaxial layer 120 may be silicon carbide, and the doping type of the epitaxial layer 120 includes N-type doping. The epitaxial layer 120 may be grown on one side of the substrate 110, and then ion implantation is performed sequentially on the epitaxial layer 120 to sequentially form a current spreading layer 130 (CSL), two well regions 140, and two first implantation regions 150; then a plasma etching method is used to etch a groove on the epitaxial layer 120, so that the two end corners of the groove are located inside the well region 140; then a gate oxide layer 170 is formed inside the groove by dry oxygen oxidation, and polysilicon is deposited inside, and ion implantation is performed on the polysilicon to form a gate 180 of a cell structure; then ion implantation is performed to form two second implantation regions 160.

[0076] S308, forming a gate oxide layer located in the trench and covering the trench bottom and the sidewalls.

[0077] S309, forming a gate located in the trench and covering the gate oxide layer.

[0078] The first direction is perpendicular to the substrate, and the second direction is parallel to the plane where the substrate is located.

[0079] In the embodiment of the present application, the above steps S308 and S309 can be understood as: forming a gate oxide layer and a gate, the gate oxide layer is located in the trench, the gate is located in the gate oxide layer in the trench and the gate is also covered by the gate oxide layer. Exemplarily, the gate oxide layer may wrap the gate. Exemplarily, the gate oxide layer may be first formed in the trench, the gate is then formed on the gate oxide layer in the trench, and then the gate oxide layer is formed on the gate to cover the gate.

[0080] The preparation method and the cellular structure provided in the embodiment of the present application belong to the same inventive concept, can solve the same technical problem, and thus achieve the same technical effect, that is, the groove of the cellular structure includes a groove bottom and two opposite side walls along the second injection region pointing to the first injection region, the groove bottom is located in the two well regions and in the current expansion layer between the two well regions, each of the side walls is located in the corresponding partial well region and in the corresponding first injection region, the gate oxide layer of the cellular structure is located in the groove and covers the groove bottom and the two side walls, and the gate of the cellular structure is located in the groove and covers the gate oxide layer; in this way, the cellular structure expands the well region To the gate corner, thereby reducing the electric field concentration of the gate oxide layer at the bottom corner of the trench, under reverse bias, when the source-drain voltage is increased, the well region at the bottom corner of the trench is depleted, and the electric field distribution at the bottom of the trench is presented as an L-shaped well region modulation, thereby preventing the gate oxide layer electric field at the corner of the gate channel from reaching a peak value and breaking through the gate oxide layer. The embodiment of the present application thus improves the reliability of the trench MOSFET device; at the same time, by ion implantation below the trench to form a current expansion layer CSL, the current path in the vertical direction of the forward conduction path of the two well regions is prevented from being cut off, thereby eliminating the JEFT effect, so that the on-resistance is greatly reduced and the loss is reduced.

[0081] In an exemplary embodiment, the forming of the groove includes: etching the groove using a plasma etching process.

[0082] In this embodiment, a plasma etching process is used to etch the groove, so that the process of forming the groove is simple and low in cost.

[0083] In an exemplary embodiment, the forming of the gate oxide layer includes: forming the gate oxide layer by a dry oxygen oxidation process.

[0084] In this embodiment, a dry oxygen oxidation process is adopted to form the gate oxide layer, so that the process of forming the gate oxide layer is simple and low in cost.

[0085] In an exemplary embodiment, the forming of the gate includes: depositing polysilicon and performing ion implantation on the polysilicon to form the gate.

[0086] The cell structure and preparation method thereof, and metal oxide semiconductor field effect transistor provided by the embodiments of the present application, wherein the cell structure may be a cell structure of a metal oxide semiconductor field effect transistor; an epitaxial layer and a current expansion layer are sequentially arranged on the substrate of the cell structure; along a direction perpendicular to the substrate, each of the two well regions is located on a side of the current expansion layer away from the epitaxial layer, and along a direction parallel to the plane where the substrate is located, the two well regions are separated by the current expansion layer; along a direction perpendicular to the substrate, each of the two first injection regions is located on a side of the corresponding well region away from the current expansion layer, and along a direction parallel to the plane where the substrate is located, the two first injection regions are separated by the current expansion layer; along a direction perpendicular to the substrate, each of the two second injection regions is located on a side of the current expansion layer away from the epitaxial layer, and along a direction parallel to the plane where the substrate is located, each second injection region is located on a side of the corresponding well region and the first injection region away from the current expansion layer;

[0087] On this basis, the groove of the cellular structure includes a groove bottom and two opposite side walls along the second injection region pointing to the first injection region, the groove bottom is located in the two well regions and in the current expansion layer between the two well regions, each of the side walls is located in the corresponding part of the well region and in the corresponding first injection region, the gate oxide layer of the cellular structure is located in the groove and covers the groove bottom and the two side walls, and the gate of the cellular structure is located in the groove and covers the gate oxide layer; in this way, the cellular structure expands the well region to the gate corner, thereby reducing the electric field concentration of the gate oxide layer at the bottom corner of the groove, Under reverse bias, when the source-drain voltage is increased, the well region at the bottom corner of the trench is depleted, and the electric field distribution at the bottom of the trench is presented as an L-shaped well region modulation, thereby preventing the gate oxide layer electric field at the corner of the gate channel from reaching the peak value and breaking through the gate oxide layer. The embodiment of the present application thus improves the reliability of the trench MOSFET device; at the same time, by ion implantation below the trench to form a current expansion layer CSL, the current path in the vertical direction of the forward conduction path of the two well regions is prevented from being cut off, thereby eliminating the JEFT effect, so that the on-resistance is greatly reduced and the loss is reduced.

[0088] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0089] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0090] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A cellular structure, characterized in that: include: substrate; an epitaxial layer, located on one side of the substrate; A current spreading layer, located on a side of the epitaxial layer away from the substrate; Two well regions, each of which is located on a side of the current spreading layer away from the epitaxial layer along a first direction, and the two well regions are separated by the current spreading layer along a second direction; Two first injection regions, each of which is located at a side of the corresponding well region away from the current spreading layer along a first direction, and the two first injection regions are separated by the current spreading layer along a second direction; Two second injection regions, each of which is located at a side of the current spreading layer away from the epitaxial layer along the first direction, and each of which is located at a side of the corresponding well region and the first injection region away from the current spreading layer along the second direction; A trench, comprising a trench bottom and two opposite side walls along the second injection region pointing to the first injection region, wherein the trench bottom is located in the two well regions and in the current spreading layer between the two well regions, and each of the side walls is located in a corresponding part of the well region and in a corresponding first injection region; A gate oxide layer is located in the trench; A gate, the gate oxide layer being located in the trench, wherein the gate is also covered by the gate oxide layer; The first direction is perpendicular to the substrate, and the second direction is parallel to the plane where the substrate is located.

2. The cellular structure according to claim 1, characterized in that: Also includes: a gate dielectric layer, located on a side of the gate away from the current spreading layer and covering a portion of each of the first injection regions; A source electrode, located at a side of the gate dielectric layer away from the gate and covering each of the second injection regions and each of the exposed first injection regions; The drain electrode is located on a side of the substrate away from the epitaxial layer.

3. The cellular structure according to claim 1, characterized in that: The ion implantation type of the current spreading layer is N type.

4. The cellular structure according to any one of claims 1 to 3, characterized in that: The ion implantation type of the well region is P type.

5. The cellular structure according to any one of claims 1 to 3, characterized in that: The ion implantation type of the first implantation region is N-type, and the ion implantation type of the second implantation region is P-type.

6. A metal oxide semiconductor field effect transistor, characterized in that: Comprising the cellular structure as described in any one of claims 1-5.

7. A method for preparing a cellular structure, characterized in that: include: providing a substrate; forming an epitaxial layer located on one side of the substrate; forming a current spreading layer located on a side of the epitaxial layer away from the substrate; forming two well regions, each of the well regions being located on a side of the current spreading layer away from the epitaxial layer along a first direction, and the two well regions being separated by the current spreading layer along a second direction; forming two first injection regions, wherein each of the first injection regions is located at a side of the corresponding well region away from the current spreading layer along a first direction, and the two first injection regions are separated by the current spreading layer along a second direction; forming two second injection regions, wherein each of the second injection regions is located at a side of the current spreading layer away from the epitaxial layer along the first direction, and each of the second injection regions is located at a side of the corresponding well region and the first injection region away from the current spreading layer along the second direction; Forming a trench, comprising a trench bottom and two opposite side walls along the second injection region pointing to the first injection region, wherein the trench bottom is located in the two well regions and in the current spreading layer between the two well regions, and each of the side walls is located in a corresponding portion of the well region and in a corresponding first injection region; forming a gate oxide layer and a gate, wherein the gate oxide layer is located in the trench, the gate is located in the gate oxide layer in the trench and the gate is also covered by the gate oxide layer; The first direction is perpendicular to the substrate, and the second direction is parallel to the plane where the substrate is located.

8. The method for preparing a cellular structure according to claim 7, characterized in that: The forming of the groove comprises: The trenches are etched using a plasma etching process.

9. The method for preparing a cellular structure according to any one of claims 7 to 8, characterized in that: The forming of the gate oxide layer comprises: A gate oxide layer is formed by a dry oxygen oxidation process.

10. The method for preparing a cellular structure according to any one of claims 7 to 8, characterized in that: The forming of the gate comprises: Polysilicon is deposited and ion implanted into the polysilicon to form a gate.

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