Power semiconductor device and manufacturing method thereof

Abstract

The invention relates to a power semiconductor device and a manufacturing method thereof. In the power semiconductor device, in a chip region of a substrate, a gate trench is fully distributed in a device region surrounded by an edge region for arranging a field ring, a gate structure is formed in the gate trench, and a source region is formed on the side surface of the gate structure corresponding to a region of the device region for forming a cell. The device area is further provided with a grid leading-out area which is located outside the area where the cells need to be formed and limited by the area where the cells need to be formed, and the grid bonding pad is connected with the grid structure through a grid contact plug formed corresponding to the grid leading-out area. The gate trench can adopt uniform width and spacing, so that the influence of a load effect in an etching process can be reduced, the position and the area of the gate lead-out region in the device region can be flexibly set according to requirements, different packaging form requirements and different customer requirements can be met, and the manufacturing cost is reduced. And the area of the area where the cells are formed and the number of the cells are ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power semiconductor device and a method for manufacturing the power semiconductor device. Background Art

[0002] Power semiconductor devices are core devices for electric energy and power processing. They can be used for frequency conversion, voltage conversion, current conversion, power amplification and power management, and play a key role in the normal operation of equipment. With the development of technology, smaller chip size, smaller on-resistance and faster switching speed are the main development trends of power semiconductor devices. The trench power device formed by the trench process sets the gate in the gate trench, which has the advantages of low on-resistance, fast switching speed and simple driving circuit.

[0003] Figure 1 The present invention is a schematic diagram showing the positions of a cell region and a gate pad region of an existing power semiconductor device. Figure 2 yes Figure 1 Schematic diagram of the gate trench in region A. Figure 1 Hehe Figure 2 In the existing power semiconductor device with gate trench, a cell area 10 and a gate pad area 20 are arranged on the surface of the chip (DIE), and the positions of the cell area 10 and the gate pad area 20 are mainly defined by the layout of the gate trench, wherein the gate trench of the cell area 10 is used to form a trench gate, and the portion of the gate trench extending from the cell area 10 to the outside of the cell area 10 forms a gate lead-out trench 30, so as to define the position of the gate pad area 20 through the gate lead-out trench 30, and the gate lead-out trench 30 is used to form a gate bus (Gate Bus) connected to the trench gate.

[0004] In the above-mentioned power semiconductor device, the spacing of the gate lead-out groove 30 is usually wider than the spacing of the gate groove of the cell area 10 (about 2 to 6 times). In the etching process of forming the gate groove, due to the loading effect, it is easy to cause the bottom of the gate lead-out groove 30 to be not etched cleanly, increasing the risk of electrical failure of the device in the relevant area. In addition, the existing design of the cell area 10 and the gate pad area 20 makes the gate pad area 20 occupy a part of the chip surface area, affecting the area of ​​the cell area 10 and the number of cells, which is not conducive to reducing the on-resistance of the device. Moreover, the position of the gate pad area 20 is determined after the gate groove process is completed, which is not flexible enough and is not convenient to meet the requirements of different packaging forms and different customer needs. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a power semiconductor device and a method for manufacturing the power semiconductor device.

[0006] In one aspect, the present invention provides a power semiconductor device, the power semiconductor device comprising:

[0007] A substrate having a chip region, wherein the chip region includes an edge region for arranging a field ring and a device region surrounded by the edge region, and a gate trench formed in the substrate covers the device region;

[0008] A gate structure formed in the gate trench;

[0009] A source region is formed on the side of the gate structure corresponding to the region where the cell is to be formed in the device region, and the device region further has a gate lead-out region located outside the region where the cell is to be formed and defined by the region where the cell is to be formed; and

[0010] A gate pad is connected to the gate structure via a gate contact plug formed corresponding to the gate lead-out region.

[0011] Optionally, in the device region, the pattern density of the gate trench is uniform.

[0012] Optionally, in the device region, the gate trench has a uniform trench width.

[0013] Optionally, in the device region, the gate trench includes a plurality of parallel trenches extending in the same direction parallel to the top surface of the substrate, and the spacing between two adjacent parallel trenches in the same direction is equal.

[0014] Optionally, in the device region, the gate trenches extend in a direction parallel to the top surface of the substrate and intersect to form a herringbone pattern or a herringbone pattern; or, the gate trenches extend in a direction parallel to the top surface of the substrate to form a plurality of parallel trenches.

[0015] Optionally, the power semiconductor device further includes:

[0016] A well region is formed at least corresponding to the region where the cell is to be formed and is located on the upper portion of the substrate between the gate trenches, the source region is formed on the top of the well region in the region where the cell is to be formed, the well region has a first conductivity type, and the source region has a second conductivity type; and

[0017] The source pad is connected to the source region through a source contact plug formed corresponding to the region where the cell is to be formed.

[0018] In one aspect, the present invention provides a method for manufacturing a power semiconductor device, the method comprising:

[0019] Providing a substrate, wherein the substrate has a chip region, wherein the chip region includes an edge region for arranging a field ring and a device region surrounded by the edge region;

[0020] forming a gate trench covering the device region in the substrate;

[0021] forming a gate structure in the gate trench;

[0022] Performing source region ion implantation corresponding to a region of the device region where a cell is to be formed, so as to form a source region on a side of the gate structure of the region where a cell is to be formed, wherein the device region further has a gate lead-out region located outside the region where a cell is to be formed and defined by the region where a cell is to be formed; and

[0023] A gate contact plug connected to the gate structure is formed corresponding to the gate lead-out region, and a gate pad connected to the gate contact plug is formed.

[0024] Optionally, in the device region, the pattern density of the gate trench is uniform; and / or, in the device region, the trench width of the gate trench is uniform.

[0025] Optionally, in the device region, the gate trench includes a plurality of parallel trenches extending in the same direction parallel to the top surface of the substrate, and the spacing between two adjacent parallel trenches in the same direction is equal.

[0026] Optionally, in the device area, the gate trenches extend in a direction parallel to the top surface of the substrate and intersect to form a zigzag pattern or a herringbone pattern; or, in the device area, the gate trenches extend in a direction parallel to the top surface of the substrate to form multiple parallel trenches.

[0027] In the power semiconductor device and the manufacturing method of the power semiconductor device provided by the present invention, on the one hand, the gate groove formed in the substrate covers the device area surrounded by the edge area in the chip area, and the layout used to make the gate groove is not used to define the position of the gate pad area, and a relatively uniform width and spacing can be used, which can reduce the influence of the load effect in the etching process. On the other hand, the gate pad is connected to the gate structure through a gate contact plug formed corresponding to the gate lead-out area, and the gate lead-out area is located outside the area where the cell is to be formed in the device area and is limited by the area where the cell is to be formed. The area where the cell is to be formed and the gate lead-out area can be defined by the layout of the source area ion implantation. The position and area of ​​the gate lead-out area in the device area can be flexibly set as needed, which helps to meet the requirements of different packaging forms and different customer requirements. In addition, while meeting the gate pad connection, the area of ​​the area where the cell is to be formed and the number of cells can be ensured, which helps to reduce the on-resistance of the device and increase the switching speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1The present invention is a schematic diagram showing the positions of a cell region and a gate pad region of an existing power semiconductor device.

[0029] Figure 2 yes Figure 1 Schematic diagram of the gate trench in area A.

[0030] Figure 3 It is a schematic flow chart of a method for manufacturing a power semiconductor device according to an embodiment of the present invention.

[0031] Figure 4 It is a plan view of a method for manufacturing a power semiconductor device according to an embodiment of the present invention after forming a gate trench.

[0032] FIG. 5A to FIG. 5C Three exemplary gate trench patterns are shown in FIG.

[0033] Figure 6 It is a schematic plan view of a method for manufacturing a power semiconductor device after forming a source region according to an embodiment of the present invention.

[0034] Figure 7 1 is a plan view of a method for manufacturing a power semiconductor device according to an embodiment of the present invention after forming a gate contact plug and a source contact plug.

[0035] Figure 8 Is adopted Figure 3 The cross-sectional schematic diagram of a power semiconductor device formed by the method for manufacturing the power semiconductor device shown. DETAILED DESCRIPTION

[0036] The power semiconductor device and the manufacturing method thereof of the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be understood that the drawings in the specification are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0037] The embodiment of the present invention relates to a power semiconductor device and a method for manufacturing a power semiconductor device. The power semiconductor device is, for example, a power MOSFET or an IGBT, which has a gate trench for arranging a gate structure. Figure 1 and Figure 2The power semiconductor device shown in the figure is different. In the embodiment of the present invention, the layout used to make the gate groove is not used to define the gate pad area. The gate groove in the embodiment of the present invention is distributed in the device area surrounded by the edge area for setting the field ring. The gate groove in the device area is designed according to the size of the cell structure formed, and a relatively uniform width and spacing can be adopted, which helps to reduce the influence of the load effect in the etching process. The lead-out position of the gate structure formed in the gate groove can be flexibly selected in the device area, which is convenient for ensuring the area of ​​the region where the cell is to be formed and the number of cells while satisfying the gate pad connection, which helps to reduce the on-resistance of the device and increase the switching speed of the device, and also helps to meet the requirements of different packaging forms and different customer needs.

[0038] The following combination Figures 3 to 8 A method for manufacturing a power semiconductor device according to an embodiment of the present invention is described.

[0039] Reference Figure 3 , Figure 4 and Figure 8 , performing step S1, providing a substrate 100, wherein the substrate 100 has a chip region, wherein the chip region includes an edge region 40 for setting a field ring and a device region 50 surrounded by the edge region 40. Then performing step S2, forming a gate trench TR covering the device region 50 in the substrate 100. Compared to Figure 2 As shown in the layout of the gate trench, in this embodiment, the layout used to make the gate trench TR no longer defines the gate pad area, but is unified with the repeated structural layout of the gate trench pattern in the cell area, and then the area for setting the gate contact plug for gate electrical lead-out is selected within the device area 50 as needed.

[0040] The substrate 100 is, for example, a silicon substrate or other suitable substrate. An epitaxial layer may be formed on the front side of the silicon substrate, and the epitaxial layer may be used to construct a drift region of a power semiconductor device to be manufactured. A gate trench TR may be formed in the epitaxial layer, and the opening faces the side of the epitaxial layer away from the silicon substrate. Taking a power MOSFET as an example, a drain may be formed on the back side of the silicon substrate later.

[0041] A plurality of cells of uniform size and repeated arrangement can be subsequently formed in the device area 50, and the gate trench TR is set according to the design of the cells in the device area 50. In order to avoid being affected by the load effect during the etching process of forming the gate trench TR, the pattern density of the gate trench TR in the device area 50 changes little, and the pattern density is, for example, uniform (i.e., equal). The pattern density refers to the area ratio of the gate trench TR within a set area range in the device area 50. For example, for two areas with the same area but different positions in the device area 50, the area ratio of the gate trench TR in the two areas, i.e., the pattern density, can be obtained by calculation. In this embodiment, the pattern density of the gate trench TR in the two areas is equal. In addition, the change in the groove width of the gate trench TR in the device area 50 is also small, and the groove width is, for example, uniform. Optionally, in the device region 50, the gate trench TR includes a plurality of parallel trenches extending in the same direction parallel to the top surface of the substrate 100 (for example, may include a plurality of parallel trenches extending in a first direction and a plurality of parallel trenches extending in a second direction). In this embodiment, the difference in spacing between two adjacent parallel trenches in the same direction is small, for example, equal.

[0042] As an example, in the device region 50, the gate trenches TR extend in a direction parallel to the top surface of the substrate 100 and intersect to form a zigzag pattern (see Figure 5A ) or a herringbone pattern (see Figure 5B ), or, in the device region 50, the gate trench TR extends in a direction parallel to the top surface of the substrate 100 to form a plurality of parallel trenches (refer to Figure 5C ).by Figure 5A Taking the arrangement shown as an example, the gate trench TR includes a plurality of transverse trenches TR-a extending in the transverse direction and a plurality of longitudinal trenches TR-b extending in the longitudinal direction. The spacing between any two adjacent transverse trenches TR-a is equal, and the spacing between any two adjacent longitudinal trenches TR-b is equal.

[0043] Then, step S3 is performed to form a gate structure in the gate trench TR. Figure 8 The gate structure may include a gate oxide layer 110 covering the inner surface of the gate trench TR and a polysilicon gate 120 covering the gate oxide layer 110 and filling the gate trench TR.

[0044] After forming the gate structure, the manufacturing method may further include the step of performing well region ion implantation on the substrate 100 to form a well region 101 in the upper part of the substrate 100 between the gate trenches TR. The depth of the gate trench TR is greater than the depth of the well region 101. The well region 101 is formed in the upper part of the substrate 100 between the gate trenches TR at least corresponding to the area where the cell is to be formed. In the following description, the n-channel power MOSFET is mainly used for explanation, and the well region ion implantation is, for example, a p-type implantation. However, the present invention is not limited to this. In another embodiment, the well region ion implantation may also be an n-type implantation. In addition, in some other embodiments, the well region ion implantation may also be completed before forming the gate structure.

[0045] Afterwards, refer to Figure 6 and Figure 8 , step S4 is performed, corresponding to the region of the device region 50 where the cell is to be formed (i.e., the cell region 51), source region ion implantation is performed to form a source region 102 on the side of the gate structure in the region where the cell is to be formed, and the device region 50 also has a gate lead-out region 52 located outside the region where the cell is to be formed and defined by the region where the cell is to be formed. In this embodiment, the source region ion implantation is, for example, n-type heavily doped implantation. The source region 102 is located at the top of the well region 101 in the region where the cell is to be formed.

[0046] In this embodiment, the layout of the source region ion implantation is used to define the region of the device region 50 where the cell is to be formed, and the device region 50 also retains a portion of the region not used to form the cell, namely, the gate lead region 52, and the gate lead region 52 is located outside the region where the cell is to be formed and is limited by the region where the cell is to be formed. By adjusting the layout of the source region ion implantation, the position and area of ​​the region where the cell is to be formed, namely, the cell region 51 and the gate lead region 52 can be adjusted. As an example, by the source region ion implantation, it is defined that the gate lead region 52 is located at the edge region of the device region 50 (refer to Figure 6 In another embodiment, the gate lead-out region 52 may be defined as being located in the central region of the device region 50, and the gate lead-out region 52 may be located at one or more locations within the device region 50. Figure 1 and Figure 2 The layout of the gate trenches shown defines the gate pad region (including the region where the gate leads out) in a completely different manner.

[0047] Afterwards, refer to Figure 3 , Figure 7 and Figure 8 , executing step S5 , forming a gate contact plug 141 connected to the gate structure corresponding to the gate lead-out region 52 , and forming a gate pad GP connected to the gate contact plug 141 .

[0048] In this embodiment, refer to Figure 7 and Figure 8 While forming the gate contact plug 141 and the gate pad GP, a source contact plug 142 connected to the source region 102 and a source pad SP connected to the source contact plug 142 may be formed corresponding to the region where the cell is to be formed.

[0049] As an example, see Figure 8 , step S5 may include the following process:

[0050] An interlayer dielectric layer 130 is formed on the substrate 100, wherein the interlayer dielectric layer 130 covers the substrate 100 after the above process is completed, and the interlayer dielectric layer 130 may include one or more layers of dielectric material;

[0051] A gate contact through hole and a source contact through hole are respectively formed in the interlayer dielectric layer 130, wherein the gate contact through hole exposes a portion of the gate structure of the gate lead-out region 52 (more specifically, exposes a portion of the polysilicon gate 120 of the gate lead-out region 52), and the source contact through hole exposes the source region 102 and the well region 101 below the source region 102. Optionally, after forming the gate contact through hole and the source contact through hole, p+ ion implantation may be performed to form a heavily doped region 103 in the exposed polysilicon gate 120 and in the well region 101 below the source region 102;

[0052] Depositing a metal material, the metal material filling the gate contact through hole and the source contact through hole, and forming a gate contact plug 141 corresponding to the gate contact through hole, and forming a source contact plug 142 corresponding to the source contact through hole, and the metal material also covers the top surface of the interlayer dielectric layer 130;

[0053] The metal material is etched to form a first pad metal layer 151 connected to the gate contact plug 141 and a second pad metal layer 152 connected to the source contact plug 142 on the interlayer dielectric layer 130, wherein the first pad metal layer 151 and the second pad metal layer 152 are insulated from each other;

[0054] forming a passivation layer 160 , wherein the passivation layer 160 covers the first pad metal layer 151 and the second pad metal layer 152 ;

[0055] The passivation layer 160 is etched to expose a portion of the first pad metal layer 151 and a portion of the second pad metal layer 152 . The exposed first pad metal layer 151 forms a gate pad GP, and the exposed second pad metal layer 152 forms a source pad SP.

[0056] In this embodiment, the gate pad GP is connected to the gate structure in the gate lead-out region 52 so that the polysilicon gate 120 is electrically led out. The position of the gate lead-out region 52 can be flexibly selected in the device region 50 as needed. In this embodiment, when the above-mentioned source region ion implantation is performed to form the source region 102 in the region where the cell is to be formed in the device region 50, the source region ion implantation is not performed in a part of the device region 50, and this part is the gate lead-out region 52. The gate contact plug 141 is formed in the gate lead-out region 52 and contacts the polysilicon gate 120 (refer to Figure 6 and Figure 7 ), that is, the gate lead-out region 52 is defined by the layout of the source region ion implantation, and the specific position of the electrical lead-out of the gate structure in the gate lead-out region 52 is further defined by the layout of forming the gate contact plug 141 and the source contact plug 142. The gate pad GP is connected to the gate structure of the gate lead-out region 52 through the gate contact plug 141. The position and number of the gate lead-out region 52 in the device area 50, the position and number of the gate contact plug 141, and the position and range of the gate pad GP can be specifically set according to different packaging requirements and different customer needs. It has high flexibility and can ensure the area and number of cells in the device area 50 where the cells are to be formed while satisfying the connection of the gate pad GP, which helps to reduce the on-resistance of the device and increase the switching speed of the device.

[0057] The embodiment of the present invention also relates to a power semiconductor device, and the power semiconductor device can be formed by using the method for manufacturing the power semiconductor device described in the above embodiment. Figures 3 to 8 , the power semiconductor device comprises:

[0058] A substrate 100, wherein the substrate 100 has a chip region, wherein the chip region includes an edge region 40 for arranging a field ring and a device region 50 surrounded by the edge region 40, and a gate trench TR formed in the substrate 100 covers the device region 50;

[0059] A gate structure is formed in the gate trench TR. The gate structure may include a gate oxide layer 110 covering the inner surface of the gate trench TR and a polysilicon gate 120 covering the gate oxide layer 110 and filling the gate trench TR.

[0060] A source region 102 is formed on the side of the gate structure corresponding to the region of the device region 50 where the cell is to be formed (i.e., the cell region 51), and the device region 50 further has a gate lead-out region 52 located outside the region where the cell is to be formed and defined by the region where the cell is to be formed;

[0061] The gate pad GP is connected to the gate structure through a gate contact plug 141 formed corresponding to the gate lead-out region 52 .

[0062] In addition, the power semiconductor device may further include a well region 101, an interlayer dielectric layer 130, a source contact plug 142, and a source pad SP, wherein the well region 101 is formed at least corresponding to the region to be formed in the upper part of the substrate 100 between the gate trenches TR, the source region 102 is formed at the top of the well region 101 in the region to be formed in the cell, the well region has a first conductivity type (for example, p-type), the source region has a second conductivity type (for example, n-type heavily doped), and the source pad SP is connected to the source region 102 through a source contact plug 142 formed corresponding to the region to be formed in the cell. The gate contact plug 141 and the source contact plug 142 penetrate the interlayer dielectric layer 130. In addition, the power semiconductor device may further include a heavily doped region 103, which is formed in the gate structure (specifically, in the polysilicon gate 120) below the gate contact plug 141 and in the well region 101 below the source contact plug 142.

[0063] In order to avoid being affected by the load effect during the process of etching to form the gate trench TR, in the device area 50, the pattern density of the gate trench TR varies slightly, for example, the pattern density is uniform. The trench width of the gate trench TR also varies slightly, for example, uniform. As an example, in the device area 50, the gate trench TR includes a plurality of parallel trenches extending in the same direction parallel to the top surface of the substrate 100, and the difference in the spacing between two adjacent parallel trenches in the same direction is small, for example, equal.

[0064] In the device region 50, the gate trenches TR may extend in a direction parallel to the top surface of the substrate 100 and intersect to form a zigzag pattern (see Figure 5A ) or a herringbone pattern (see Figure 5B ), or, in the device region 50, the gate trench TR extends in a direction parallel to the top surface of the substrate 100 to form a plurality of parallel trenches (refer to Figure 5C ).

[0065] In the manufacturing method of the power semiconductor device and the power semiconductor device described in the above embodiment, on the one hand, the gate trench TR formed in the substrate 100 covers the device area 50 surrounded by the edge area 40 in the chip area, and the layout used to make the gate trench TR is not used to define the position of the gate pad area, and a relatively uniform width and spacing can be used, which can reduce the influence of the load effect in the etching process. On the other hand, the gate pad GP is connected to the gate structure through a gate contact plug 141 formed corresponding to the gate lead-out area 52, and the gate lead-out area 52 is located outside the area where the cell is to be formed (i.e., the cell area 51) and is limited by the area where the cell is to be formed. The area where the cell is to be formed and the gate lead-out area 52 can be defined by the layout of the source area ion implantation. The position and area of ​​the gate lead-out area 52 in the device area 50 can be flexibly set as needed, which helps to meet different packaging form requirements and different customer requirements. In addition, while meeting the gate pad connection, the area of ​​the area where the cell is to be formed and the number of cells can be ensured, which helps to reduce the device on-resistance and increase the device switching speed.

[0066] It should be noted that the embodiments of this specification are described in a progressive manner. For the power semiconductor device disclosed in the embodiments, since it corresponds to the manufacturing method of the power semiconductor device disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0067] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A power semiconductor device, characterized in that: include: A substrate having a chip region, wherein the chip region includes an edge region for arranging a field ring and a device region surrounded by the edge region, and a gate trench formed in the substrate covers the device region; a gate structure formed in the gate trench; A source region is formed on the side of the gate structure corresponding to the region where the device region is to form a cell, and the device region also has a gate lead-out region located outside the region where the cell is to be formed and defined by the region where the cell is to be formed; as well as A gate pad is connected to the gate structure via a gate contact plug formed corresponding to the gate lead-out region.

2. The power semiconductor device according to claim 1, characterized in that: In the device region, the pattern density of the gate trenches is uniform.

3. The power semiconductor device according to claim 1, characterized in that: In the device region, the gate trench has a uniform trench width.

4. The power semiconductor device according to claim 1, characterized in that: In the device region, the gate trench includes a plurality of parallel trenches extending in the same direction parallel to the top surface of the substrate, and the spacing between two adjacent parallel trenches in the same direction is equal.

5. The power semiconductor device according to claim 1, characterized in that: In the device region, the gate trenches extend in a direction parallel to the top surface of the substrate and intersect to form a herringbone pattern or a herringbone pattern; or, in the device region, the gate trenches extend in a direction parallel to the top surface of the substrate to form a plurality of parallel trenches.

6. The power semiconductor device according to any one of claims 1 to 5, characterized in that: Also includes: A well region is formed at least corresponding to the region where the cell is to be formed on the upper portion of the substrate between the gate trenches, the source region is formed on the top of the well region in the region where the cell is to be formed, the well region has a first conductivity type, and the source region has a second conductivity type; as well as The source pad is connected to the source region through a source contact plug formed corresponding to the region where the cell is to be formed.

7. A method for manufacturing a power semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate has a chip region, wherein the chip region includes an edge region for arranging a field ring and a device region surrounded by the edge region; forming a gate trench covering the device region in the substrate; forming a gate structure in the gate trench; Performing source region ion implantation corresponding to the region of the device region where the cell is to be formed, so as to form a source region on the side of the gate structure of the region where the cell is to be formed, wherein the device region further has a gate lead-out region located outside the region where the cell is to be formed and defined by the region where the cell is to be formed; as well as A gate contact plug connected to the gate structure is formed corresponding to the gate lead-out region, and a gate pad connected to the gate contact plug is formed.

8. The method according to claim 7, characterized in that: In the device region, the pattern density of the gate trench is uniform; and / or, in the device region, the trench width of the gate trench is uniform.

9. The method according to claim 7, characterized in that: In the device region, the gate trench includes a plurality of parallel trenches extending in the same direction parallel to the top surface of the substrate, and the spacing between two adjacent parallel trenches in the same direction is equal.

10. The method according to claim 7, characterized in that: In the device region, the gate trenches extend in a direction parallel to the top surface of the substrate and intersect to form a herringbone pattern or a herringbone pattern; or, in the device region, the gate trenches extend in a direction parallel to the top surface of the substrate to form a plurality of parallel trenches.

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