Semiconductor power module

Abstract

The invention relates to a semiconductor power module, and belongs to the technical field of device packaging. The module comprises a heat dissipation bottom plate, an insulation substrate, a metal layer, a power terminal, a signal terminal, a chip and a temperature sensing resistor. The insulating substrate is arranged on the surface of the heat dissipation bottom plate, the metal layer is arranged on the surface of the insulating substrate, and the power terminal, the signal terminal, the chip and the temperature sensing resistor are all arranged on the insulating substrate and electrically connected with the metal layer. Part of chips form a lower bridge in the middle area of the insulating substrate, the other part of chips form upper bridges on the two sides of the lower bridge, and the number of the upper bridge chips is equal to that of the lower bridge chips. The power terminals, the upper bridge chip and the lower bridge chip jointly form power loops which are equal in size and opposite in direction in the power module. According to the invention, the problems of over-high temperature of individual chips caused by non-uniform current distribution and electromagnetic interference caused by over-large parasitic parameters can be solved.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic device packaging and relates to a semiconductor power module. Background Art

[0002] In today's rapidly developing science and technology field, emerging industries such as renewable energy, electric vehicles, high-speed railways and data centers have increasingly stringent requirements for power electronic systems, not only pursuing higher efficiency and performance, but also expecting to achieve smaller size and longer service life. This trend has directly promoted the innovation of power semiconductor device technology, especially the transition from traditional silicon (Si)-based materials to third-generation semiconductor materials such as silicon carbide (SiC). SiC power devices have become one of the key technologies to improve the efficiency of power electronic systems due to their excellent physical properties, such as high temperature resistance, high breakdown voltage, low on-resistance and extremely high switching speed.

[0003] However, the high performance of SiC power devices also brings new challenges, especially the requirements for packaging technology and power module design are more stringent. Since the switching speed of SiC devices is significantly faster than that of Si devices, their sensitivity to parasitic parameters in the circuit during the switching process increases dramatically. Among them, parasitic inductance is an important factor affecting the performance and reliability of SiC devices. At the moment when the device is quickly turned off, the inductance in the commutation circuit will induce overvoltage. The amplitude of this overvoltage is proportional to the switching speed. Therefore, SiC devices are more susceptible to overvoltage shocks than Si devices. If the overvoltage exceeds the withstand voltage limit of the device, it will directly cause damage to the device and affect the stable operation of the entire system.

[0004] To address this challenge, existing solutions usually include: 1) Selecting devices with higher voltage resistance. Although this can improve the safety margin of the system, high voltage resistance devices are expensive and may not always be necessary, which increases the overall cost of the system. 2) Slowing down the switching speed. Artificially reducing the switching speed by adjusting the control strategy or adding additional circuits can effectively reduce overvoltage, but it also sacrifices the original high-speed switching advantage of SiC devices, resulting in increased switching losses and reduced efficiency. 3) Adding buffer absorption circuits, such as using RCD absorption circuits or active clamping circuits to absorb overvoltage energy. Although these methods are effective, they will also increase the complexity and cost of the system and may introduce new loss points.

[0005] Therefore, it is necessary to start with the design of the power module loop structure and optimize its structure to effectively reduce the parasitic inductance, thereby ensuring the reliability of the power module operation. Summary of the invention

[0006] In view of this, an object of the present invention is to provide a semiconductor power module to solve the problem of excessively high temperature of individual chips due to uneven current distribution and electromagnetic interference caused by excessive parasitic parameters in semiconductor power devices in the prior art.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] A semiconductor power module includes: a heat dissipation base plate, an insulating substrate, a metal layer, a power terminal, a signal terminal, a chip and a temperature-sensitive resistor. The insulating substrate is arranged on the surface of the heat dissipation base plate, the metal layer is arranged on the surface of the insulating substrate, and the power terminal, the signal terminal, the chip and the temperature-sensitive resistor are all arranged on the insulating substrate and electrically connected to the metal layer.

[0009] Furthermore, part of the chips are connected in parallel to form an upper bridge, and another part of the chips are connected in parallel to form a lower bridge, and the number of upper bridge chips and lower bridge chips is equal. The lower bridge chips are arranged in an array in the middle area of ​​the insulating substrate, and the upper bridge chips are symmetrically distributed on both sides of the lower bridge chips.

[0010] Furthermore, the power terminal includes a first DC positive terminal, a second DC positive terminal, a DC negative terminal and an AC terminal, and the first DC positive terminal and the second DC positive terminal are respectively located on both sides of the DC negative terminal.

[0011] Among them, the first DC positive terminal is connected to the drain of one chip on one side of the upper bridge chip, the second DC positive terminal is connected to the drain of the other chip on the upper bridge chip, and the AC terminal is connected to the source of all chips in the upper bridge chip, thereby forming a power loop from the DC positive terminal to the AC terminal. The AC terminal is connected to the drain of all chips in the lower bridge chip, and the DC negative terminal is connected to the source of all chips in the lower bridge chip, thereby forming a power loop from the AC terminal to the DC negative terminal. The currents in these two power loops are equal in magnitude but opposite in direction, and the length of the power loop is short, so the parasitic inductance of the loop can be reduced based on the principle of magnetic field cancellation.

[0012] Furthermore, the power terminal includes an upper bridge drain lead terminal, an upper bridge gate lead terminal and an upper bridge Kelvin source lead terminal arranged on one side of the AC terminal, and a lower bridge gate lead terminal, a lower bridge Kelvin source lead terminal, a first temperature sensing pin and a second temperature sensing pin arranged on the other side of the AC terminal.

[0013] Among them, the upper bridge drain lead terminal is connected to the drain of the upper bridge chip, the upper bridge gate lead terminal is connected to the gate of the upper bridge chip, and the upper bridge Kelvin source lead terminal is connected to the source of the upper bridge chip; the lower bridge gate lead terminal is connected to the gate of the lower bridge chip, and the lower bridge Kelvin source lead terminal is connected to the source of the lower bridge chip; the first temperature sensing pin and the second temperature sensing pin are respectively connected to the temperature sensing resistor.

[0014] Furthermore, the semiconductor power module also includes an AC terminal busbar, a DC negative terminal busbar, a DC positive terminal busbar, a first gate drive signal busbar and a second gate drive signal busbar.

[0015] The drain of the upper bridge chip is electrically connected to the first DC positive terminal, the second DC positive terminal and the upper bridge drain lead terminal through the DC positive terminal busbar, the source of the upper bridge chip is electrically connected to the AC terminal and the upper bridge Kelvin source lead terminal through the AC terminal busbar, and the gate of the upper bridge chip is electrically connected to the upper bridge gate lead terminal through the first gate drive signal busbar.

[0016] The drain of the lower bridge chip is electrically connected to the AC terminal through the AC terminal busbar, the source of the lower bridge chip is electrically connected to the DC negative terminal and the lower bridge Kelvin source lead terminal through the DC negative terminal busbar, and the gate of the lower bridge chip is electrically connected to the lower bridge gate lead terminal through the second gate drive signal busbar.

[0017] Among them, the second gate drive signal busbar is arranged in the middle area of ​​the AC terminal busbar, so that the drive circuit is symmetrically arranged, the second gate drive signal busbar is insulated from the AC terminal busbar, and is electrically connected to the gate of the lower bridge chip and the lower bridge gate lead-out terminal through bonding wires.

[0018] The first gate drive signal busbar is arranged around the edge of the insulating substrate and is electrically connected to the gate of the upper bridge chip and the upper bridge gate lead-out terminal through bonding wires, wherein the connection with the upper bridge gate lead-out terminal is a bonding wire-free surface connection.

[0019] Furthermore, the semiconductor power module also includes heat dissipation pin fins arranged on the heat dissipation base plate to improve heat dissipation efficiency.

[0020] The beneficial effect of the present invention is that: the present application sets the chip layout to an axially symmetrical distribution, and sets the current directions between the upper bridge and lower bridge chips to be opposite, so as to achieve equal currents and opposite directions in the upper and lower bridge arms of the power circuit, thereby utilizing the principle of magnetic field cancellation to greatly reduce the parasitic inductance of the power module circuit, effectively reduce the power module loss, reduce the power chip shutdown voltage spike, and improve the reliability of the power module.

[0021] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0023] Figure 1 A schematic diagram of the structure of a power module provided by an embodiment of the present invention;

[0024] Figure 2 A schematic diagram of a power module heat sink provided by an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of a power circuit of a power module provided in one embodiment of the present invention.

[0026] Figure markings: 1-first DC positive terminal; 2-DC negative terminal; 3-second DC positive terminal; 4-insulating substrate; 5-chip; 6-upper bridge drain lead terminal; 7-upper bridge gate lead terminal; 8-upper bridge Kelvin source lead terminal; 9-AC terminal; 10-lower bridge Kelvin source lead terminal; 11-lower bridge gate lead terminal; 12-first temperature sensing pin; 13-second temperature sensing pin; 14-AC terminal busbar; 15-first gate drive signal busbar; 16-DC negative terminal busbar; 17-second gate drive signal busbar; 18-temperature sensing resistor; 19-DC positive terminal busbar; 20-heat dissipation base plate; 21-pin fin. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0028] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0029] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0030] The present invention proposes a semiconductor power module, which includes a heat dissipation base plate, an insulating substrate, a plurality of chips, and metal terminals. The insulating substrate is located above the heat dissipation base plate, and a metal layer is provided on the surface of the insulating substrate, and the metal terminal is electrically connected to the metal layer. The plurality of chips are located on the insulating substrate and electrically connected to the metal layer, wherein a portion of the chips are connected in parallel to form a lower bridge of the power module, and another portion of the chips are connected in parallel to form an upper bridge of the power module, and the number of chips in the upper bridge and the lower bridge is the same. In addition, the chips in the upper bridge and the lower bridge are arranged in an array, and the upper bridge chips are symmetrically distributed on both sides of the lower bridge chips.

[0031] With this configuration, since the upper and lower bridges in the multiple chip layouts are arranged in an array, the current imbalance can be reduced, avoiding the situation where the current of individual chips is too large and the local temperature is too high. In addition, the heat dissipation base of the power module can increase the heat dissipation area through the pin fins set under the base, achieve rapid heat dissipation, and prevent the chip from being damaged due to excessive temperature.

[0032] It should be noted that the power chip can be a switch chip, the chip 5 can be a MOS tube, a triode, etc., and multiple chips form a single-phase half-bridge structure. In addition, the present invention does not limit the material and quantity of the chip. For example, the switch chip can be a silicon carbide chip, and the number of chips can be 10, 16 or 20.

[0033] like Figure 1 As shown, it is a semiconductor power module proposed in an embodiment of the present invention. In this embodiment, the power chip 5 is a MOS tube, the number of MOS tubes is 16, and there are 8 MOS tubes in the upper bridge and the lower bridge. Among them, the 8 MOS tubes of the lower bridge are arranged in an array in the middle area of ​​the insulating substrate 4, and the 8 MOS tubes of the upper bridge are symmetrically distributed on both sides of the lower bridge, with 4 MOS tubes on each side. Through the symmetrical and mirror-image arrangement of the upper bridge and the lower bridge parallel chips, the imbalance of the current can be reduced, and the current of individual chips can be avoided to be too large. At the same time, it is also convenient to lead out the bonding wires of the chips, which is convenient for installation.

[0034] In this embodiment, the outer structure of the power module is rectangular. The metal terminal includes a power terminal and a signal terminal, wherein the power terminal includes a DC negative terminal 2, an AC terminal 9 and two DC positive terminals, the two DC positive terminals are respectively a first DC positive terminal 1 and a second DC positive terminal 3, wherein the DC negative terminal 2 and the two DC positive terminals are arranged on the same side of the power module, and the module positive pole and the module negative pole are led out in parallel, and the two DC positive terminals are respectively located on both sides of the DC negative terminal 2, and the two DC positive terminals are symmetrically arranged. By symmetrically arranging the two DC positive terminals, the parasitic inductance of the entire power circuit can be reduced, and the turn-off voltage spike and switch oscillation can be further reduced, thereby improving the performance of the power module. The AC terminal 9 and the signal terminal are located on the other side of the power module, and for the portability of the connection and the miniaturization of the power module as a whole, the signal terminal is divided into two parts, and the two signal terminals are respectively located on both sides of the AC terminal 9.

[0035] Specifically, the signal terminal includes an upper bridge drain lead terminal 6, an upper bridge gate lead terminal 7, an upper bridge Kelvin source lead terminal 8, a lower bridge Kelvin source lead terminal 10, a lower bridge gate lead terminal 11, a first temperature sensing pin 12, and a second temperature sensing pin 13. Among them, the upper bridge drain lead terminal 6, the upper bridge gate lead terminal 7, and the upper bridge Kelvin source lead terminal 8 are located on one side of the AC terminal 9, and the lower bridge Kelvin source lead terminal 10, the lower bridge gate lead terminal 11, the first temperature sensing pin 12, and the second temperature sensing pin 13 are located on the other side of the AC terminal 9.

[0036] In this embodiment, the selected chip 5 is a MOS tube, the drain of the chip in the upper bridge is electrically connected to the DC positive terminal, the drain of the chip in the lower bridge is electrically connected to the AC terminal, the source of the upper bridge chip is electrically connected to the AC terminal by leading out a bonding wire, and the source of the lower bridge chip is connected to the DC negative terminal by leading out a bonding wire. Figure 3 As shown, the drain of the upper bridge chip on one side is connected to the first DC positive terminal 1, and the source is connected to the AC terminal 9, and the drain of the upper bridge chip on the other side is connected to the second DC positive terminal, and the source is connected to the AC terminal 9, forming a symmetrical power loop flowing from the DC positive terminal to the AC terminal; and the drain of the chip on the lower bridge is connected to the AC terminal 9, and the source is connected to the DC negative terminal 2, forming a power loop flowing from the AC terminal to the DC negative terminal. In this way, the chip 5 is connected to the metal layer on the insulating substrate 4 through bonding wires to form a power loop. The power loop is short and symmetrically distributed, so that the power loop has a lower parasitic inductance. At the same time, the 16 chips 5 are evenly distributed on the insulating substrate, which can evenly dissipate the heat generated by the chip, avoid excessive thermal coupling between chips, and improve the reliability of the power module.

[0037] In this embodiment, in order to reduce the interference between the power circuit and the drive circuit and improve the switching efficiency of the chip 5, a Kelvin source connection method is adopted when connecting the chip 5.

[0038] The power module also includes an AC terminal busbar 14 and a DC negative terminal busbar 16. The upper bridge Kelvin source lead terminal 8 is located on the AC terminal busbar 14 to realize electrical connection with the upper bridge chip source. The lower bridge chip Kelvin source lead terminal 10 is located on the DC negative terminal busbar 16 to realize electrical connection with the lower bridge chip source.

[0039] The power module also includes a first gate drive signal busbar 15 and a second gate drive signal busbar 17. Bonding wires are used to lead all the gates of the upper bridge chip to the first gate drive signal busbar 15 to achieve electrical connection. The gate of the lower bridge chip is electrically connected to the second gate drive signal busbar 17 through bonding wires, and the second gate drive signal busbar 17 is electrically connected to the lower bridge gate lead-out terminal 11 through bonding wires.

[0040] In addition, in order to detect the temperature of the chip 5 in real time, the power module is also provided with a temperature sensing resistor 18, which can be a platinum resistance temperature sensor, and the temperature sensing resistor 18 is arranged at the side of the module to facilitate the layout of the entire module and make it close to the chip to achieve real-time monitoring of the module working temperature. A temperature measurement output terminal is correspondingly arranged in the metal terminal, and the temperature measurement output terminal includes a first temperature sensing pin 12 and a second temperature sensing pin 13. The temperature sensing resistor 18 is electrically connected to the first temperature sensing pin 12 and the second temperature sensing pin 13 respectively, so that the junction temperature of the chip 5 can be accurately estimated.

[0041] In this embodiment, in order to improve the heat dissipation effect, the surface of the heat dissipation base plate 20 is directly connected to the insulating substrate 4 to improve the heat dissipation efficiency, and heat dissipation pin fins 21 are provided under the heat dissipation base plate 20 to further improve the heat dissipation efficiency.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A semiconductor power module, characterized in that: include: Heat dissipation base plate, insulating substrate, metal layer, power terminal, signal terminal, chip and temperature sensing resistor; The insulating substrate is arranged on the surface of the heat dissipation base plate, the metal layer is arranged on the surface of the insulating substrate, and the power terminal, signal terminal, chip and temperature-sensitive resistor are all arranged on the insulating substrate and electrically connected to the metal layer; The chip comprises an upper bridge chip and a lower bridge chip; the lower bridge chips are arranged in an array in the middle area of ​​the insulating substrate, and the upper bridge chips are symmetrically distributed on both sides of the lower bridge chip; The power terminal comprises a first DC positive terminal, a second DC positive terminal, a DC negative terminal and an AC terminal, wherein the first DC positive terminal and the second DC positive terminal are respectively located on both sides of the DC negative terminal; The first DC positive terminal is connected to the drain of one chip on one side of the upper bridge chip, the second DC positive terminal is connected to the drain of the other chip on the upper bridge chip, and the AC terminal is connected to the source of all chips in the upper bridge chip, thereby forming a power loop from the DC positive terminal to the AC terminal; The AC terminal is connected to the drains of all chips in the lower bridge chip, and the DC negative terminal is connected to the sources of all chips in the lower bridge chip, thereby forming a power loop from the AC terminal to the DC negative terminal.

2. The semiconductor power module according to claim 1, characterized in that: The power terminal includes an upper bridge drain lead terminal, an upper bridge gate lead terminal and an upper bridge Kelvin source lead terminal arranged on one side of the AC terminal, and a lower bridge gate lead terminal, a lower bridge Kelvin source lead terminal, a first temperature sensing pin and a second temperature sensing pin arranged on the other side of the AC terminal; The upper bridge drain lead terminal is connected to the drain of the upper bridge chip, the upper bridge gate lead terminal is connected to the gate of the upper bridge chip, and the upper bridge Kelvin source lead terminal is connected to the source of the upper bridge chip; the lower bridge gate lead terminal is connected to the gate of the lower bridge chip, and the lower bridge Kelvin source lead terminal is connected to the source of the lower bridge chip; the first temperature sensing pin and the second temperature sensing pin are respectively connected to the temperature sensing resistor.

3. The semiconductor power module according to claim 2, characterized in that: It also includes an AC terminal busbar, a DC negative terminal busbar, a DC positive terminal busbar, a first gate drive signal busbar and a second gate drive signal busbar; The drain of the upper bridge chip is electrically connected to the first DC positive terminal, the second DC positive terminal and the upper bridge drain lead terminal through the DC positive terminal busbar, the source of the upper bridge chip is electrically connected to the AC terminal and the upper bridge Kelvin source lead terminal through the AC terminal busbar, and the gate of the upper bridge chip is electrically connected to the upper bridge gate lead terminal through the first gate drive signal busbar; The drain of the lower bridge chip is electrically connected to the AC terminal through the AC terminal busbar, the source of the lower bridge chip is electrically connected to the DC negative terminal and the lower bridge Kelvin source lead terminal through the DC negative terminal busbar, and the gate of the lower bridge chip is electrically connected to the lower bridge gate lead terminal through the second gate drive signal busbar.

4. The semiconductor power module according to claim 3, characterized in that: The second gate drive signal busbar is arranged in the middle area of ​​the AC terminal busbar, and is electrically connected to the gate of the lower bridge chip and the lower bridge gate lead-out terminal through bonding wires.

5. The semiconductor power module according to claim 3, characterized in that: The first gate drive signal busbar is arranged around the edge of the insulating substrate and is electrically connected to the gate of the upper bridge chip and the upper bridge gate lead-out terminal through bonding wires.

6. The semiconductor power module according to any one of claims 1 to 5, characterized in that: The semiconductor power module also includes heat dissipation pin fins arranged on the heat dissipation base plate to improve heat dissipation efficiency.

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