Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a substrate, an isolation layer, an active region, a grid electrode and a grid dielectric layer, the isolation layer is located on the substrate and is provided with two parallel openings; the active region is located on the isolation layer, the active region comprises a source electrode region, a channel region and a drain electrode region which are connected in sequence, the source electrode region and the drain electrode region are arranged in the openings respectively, and the channel region is located above the isolation layer and is parallel to the surface of the substrate; the grid electrode is arranged around the channel region along the extension direction of the channel region in a surrounding manner; and the gate dielectric layer is arranged between the gate and the channel region. According to the semiconductor device, the contact area between the grid electrode and the channel region is increased, the current transmission cross sectional area in the channel region and the electric field control effect are improved, the area of the semiconductor device is reduced, and the short channel effect of the semiconductor device is reduced or avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As the feature size of integrated circuit manufacturing technology continues to shrink, the short channel effect of semiconductor devices is becoming more and more obvious. The method of improving the control ability of the gate only by increasing the channel concentration, reducing the thickness of the gate oxide layer, etc. can no longer meet the requirements of the development of Moore's Law.

[0003] Generally, high-k materials and metal gates can be used to replace the gate dielectric layer and polysilicon gate made of silicon oxynitride (SiON) (i.e. HKMG technology), so that when the gate length is very small, the gate electrode capacitance can be increased by reducing the thickness of the gate oxide layer, thereby improving the gate's control over the channel and adjusting the threshold voltage. However, in semiconductor devices using HKMG, substrate parasitic capacitance has always existed and its influence has become increasingly obvious; at the same time, since the channel shape of the semiconductor device has not changed, it cannot match the improved metal gate well, and there is a defect of too large area in the design. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor device and a manufacturing method thereof, which can reduce or avoid the influence of the short channel effect on the performance of the semiconductor device while saving the area of ​​the semiconductor device.

[0005] In a first aspect, the present application provides a semiconductor device, comprising:

[0006] substrate;

[0007] An isolation layer, located on the substrate, wherein the isolation layer is provided with two openings parallel to each other;

[0008] an active region, located on the isolation layer, the active region comprising a source region, a channel region and a drain region connected in sequence, wherein the source region and the drain region are respectively arranged in one of the openings, and the channel region is located above the isolation layer and parallel to the surface of the substrate;

[0009] A gate, arranged around the channel region along an extension direction of the channel region;

[0010] The gate dielectric layer is arranged between the gate and the channel region.

[0011] In one embodiment, the cross-sectional shape of the active region along a direction perpendicular to the substrate is U-shaped with an opening facing downward.

[0012] In one embodiment, the isolation layer comprises:

[0013] A first isolation layer, located on the substrate, wherein the first isolation layer is provided with the opening;

[0014] The second isolation layer covers the inner wall of the opening and the surface of the first isolation layer away from the substrate.

[0015] In one embodiment, the material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes silicon nitride.

[0016] In one of the embodiments, the material of the gate includes a metal material, and the metal material includes at least one of metal copper, metal aluminum, and metal tungsten; the material of the gate dielectric layer includes a high dielectric constant material.

[0017] In a second aspect, the present application also provides a method for manufacturing a semiconductor device, comprising:

[0018] Providing a substrate, forming an isolation layer on the substrate, and forming two openings parallel to each other in the isolation layer;

[0019] An active region, a gate and a gate dielectric layer are formed on the isolation layer, wherein the active region includes a source region, a channel region and a drain region connected in sequence, the source region and the drain region are respectively formed in one of the openings, the channel region is formed above the isolation layer and is arranged parallel to the surface of the substrate, the gate surrounds the channel region along an extension direction of the channel region, and the gate dielectric layer is formed between the gate and the channel region.

[0020] In one embodiment, the step of forming an active region, a gate and a gate dielectric layer on the isolation layer comprises:

[0021] forming a source region and a drain region in the opening respectively, and the tops of the source region and the drain region are higher than the surface of the isolation layer;

[0022] A lower gate is formed on the isolation layer between two adjacent openings, wherein a first trench is formed in the lower gate, and an extending direction of the first trench is parallel to a connecting direction of the two adjacent openings;

[0023] forming a lower gate dielectric in the first trench, wherein a second trench is formed in the lower gate dielectric and an extension direction of the second trench is parallel to an extension direction of the first trench;

[0024] forming a channel region in the second trench, wherein the channel region connects the source region and the drain region to form an active region of the semiconductor device;

[0025] forming an upper gate dielectric layer on the channel region, wherein the upper gate dielectric layer is connected to the lower gate dielectric layer and forms a gate dielectric layer surrounding the channel region;

[0026] An upper gate is formed on the upper gate dielectric, and the upper gate is connected to the lower gate to form a gate surrounding the channel region.

[0027] In one embodiment, the step of forming a lower gate on the isolation layer between two adjacent openings comprises:

[0028] forming a lower gate on the isolation layer;

[0029] Performing a planarization process on the lower gate to make the surface of the lower gate flush with the surfaces of the source region and the drain region;

[0030] A portion of the lower gate is removed so that the remaining lower gate is located between the two openings, and the first trench is formed in the lower gate.

[0031] In one embodiment, the step of forming a lower gate dielectric in the first trench includes:

[0032] forming the lower gate dielectric on the inner wall of the first trench, wherein the lower gate dielectric at least extends to and covers the lower gate, the source region and the drain region around the first trench;

[0033] The lower gate dielectric is etched so that the remaining lower gate dielectric is located on the inner wall of the first trench and the second trench is formed in the lower gate dielectric.

[0034] In one embodiment, the isolation layer includes the first isolation layer and the second isolation layer, and the step of forming the isolation layer on the substrate and forming two parallel openings in the isolation layer includes:

[0035] forming a first isolation layer on the substrate;

[0036] Etching the first isolation layer to form the opening in the first isolation layer;

[0037] A second isolation layer is formed on the first isolation layer, wherein the second isolation layer covers an inner wall of the opening.

[0038] The unexpected effects of the present application are: by setting a gate surrounding the channel region, the contact area between the gate and the channel region is increased, which is beneficial to increasing the current transmission cross-sectional area in the channel region, thereby improving the electric field control effect in the channel region; by setting an isolation layer between the gate and the substrate, the influence of the short channel effect on the performance of the semiconductor device is reduced or avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 A schematic diagram of a three-dimensional structure of a semiconductor device provided in one embodiment of the present application.

[0041] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor device along the AB direction is shown.

[0042] Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor device along the CD direction is shown.

[0043] Figure 4 A flowchart of a method for manufacturing a semiconductor device provided in one embodiment of the present application.

[0044] Figure 5 A schematic diagram of a three-dimensional structure corresponding to the step of providing a substrate in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0045] Figure 6 A schematic diagram of a three-dimensional structure corresponding to a step of forming an opening in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0046] Figure 7 A schematic diagram of a three-dimensional structure corresponding to the step of forming an isolation layer in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0047] Figure 8 The present invention is a flowchart corresponding to the step of forming an active region, a gate and a gate dielectric layer on an isolation layer in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0048] Fig. 9 A schematic diagram of a three-dimensional structure corresponding to the step of forming a source region and a drain region in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0049] Fig.10 A schematic diagram of a three-dimensional structure corresponding to the step of forming a lower gate in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0050] Fig.11 A schematic diagram of a three-dimensional structure corresponding to the step of forming a first trench in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0051] Fig.12 for Fig.11 Schematic diagram of the cross-sectional structure of the semiconductor device along the AB direction.

[0052] Fig.13 A schematic diagram of a three-dimensional structure corresponding to the step of forming a lower gate dielectric in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0053] Fig.14 for Fig.13 Schematic diagram of the cross-sectional structure of the semiconductor device along the AB direction.

[0054] Fig.15 A schematic diagram of a three-dimensional structure corresponding to a step of forming a channel region in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0055] Fig.16 for Fig.15 Schematic diagram of the cross-sectional structure of the semiconductor device along the AB direction.

[0056] Fig.17 A schematic diagram of a three-dimensional structure corresponding to the step of forming a gate dielectric layer in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0057] Fig.18 for Fig.17 Schematic diagram of the cross-sectional structure of the semiconductor device along the AB direction.

[0058] Fig.19 A schematic diagram of a three-dimensional structure corresponding to a step of forming a gate in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0059] Fig. 20 for Fig.19 Schematic diagram of the cross-sectional structure of the semiconductor device along the AB direction.

[0060] Explanation of the reference numerals: 100 - substrate; 110 - isolation layer; 111 - opening; 112 - first isolation layer; 113 - second isolation layer; 120 - active region; 121 - source region; 122 - drain region; 123 - channel region; 130 - gate; 131 - lower gate; 131a - first trench; 132 - upper gate; 140 - gate dielectric layer; 141 - lower gate dielectric; 141a - second trench; 142 - upper gate dielectric. DETAILED DESCRIPTION

[0061] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0063] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0064] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0065] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0066] Figure 1 A schematic diagram of a three-dimensional structure of a semiconductor device provided in an embodiment of the present application, Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor device along the extension direction of the vertical channel region (i.e., the AB direction), Figure 3 for Figure 1 Schematic diagram of the cross-sectional structure of the semiconductor device along the extension direction of the channel region (ie, CD direction).

[0067] See also Figures 1 to 3 The present application provides a semiconductor device, comprising a substrate 100, an isolation layer 110, an active region 120, a gate 130 and a gate dielectric layer 140; wherein the isolation layer 110 is located on the substrate 100, and the isolation layer 110 is provided with two openings 111 parallel to each other; the active region 120 is located on the isolation layer 110, and the active region 120 comprises a source region 121, a channel region 123 and a drain region 122 connected in sequence, wherein the source region 121 and the drain region 122 are respectively provided in an opening 111, and the channel region 123 is located above the isolation layer 110 and is provided parallel to the surface of the substrate 100; the gate 130 is provided around the channel region 123 along the extension direction (i.e., the X direction) of the channel region 123; and the gate dielectric layer 140 is provided between the gate 130 and the channel region 123.

[0068] As described above, the present application increases the contact area between the gate and the channel region by setting a gate surrounding the channel region, which is beneficial to increasing the current transmission cross-sectional area in the channel region, thereby improving the electric field control effect in the channel region; by setting an isolation layer between the gate and the substrate, the influence of the short channel effect on the performance of the semiconductor device is reduced or avoided.

[0069] See also Figure 1 and Figure 3 In one embodiment, the active region 120 is arranged along a direction perpendicular to the substrate 100 (i.e. Figure 1 The cross-sectional shape of the semiconductor device 100 (in the CD direction) is a U-shape with the opening downward, thereby effectively reducing the area of ​​the active region 120 while matching the morphology of the gate 130, thereby effectively reducing the overall size of the semiconductor device.

[0070] Continue reading Figure 1 and Figure 3 In one embodiment, the isolation layer 110 includes a first isolation layer 112 and a second isolation layer 113, wherein the first isolation layer 112 is located on the substrate 100 and is provided with an opening 111; the second isolation layer 113 covers the inner wall of the opening 111 and the surface of the first isolation layer 112 away from the substrate 100. Optionally, the material of the first isolation layer 112 includes silicon oxide, and the material of the second isolation layer 113 includes silicon nitride. In other embodiments of the present application, the isolation layer 110 can be a single-layer structure made of insulating material, or a stacked structure composed of at least two different insulating materials, which is not limited in the present application.

[0071] It should be noted that, by providing the isolation layer 110, the risk of short circuit between the gate 130 and the subsequently formed source and drain can be reduced or avoided, and the negative impact of ion diffusion of the source and drain on the performance of the semiconductor device can be reduced or avoided. In other words, by isolating the gate 130 from the substrate 100 through the isolation layer 110, the appearance of a diffusion layer in the substrate 100 can be reduced or avoided, thereby reducing or avoiding the short channel effect of the semiconductor device and improving the performance of the semiconductor device.

[0072] In one embodiment, the material of the gate 130 includes a metal material, and the metal material includes at least one of metal copper (Cu), metal aluminum (Al), and metal tungsten (Wu). In other embodiments of the present application, the metal material also includes other commonly used conductive metal materials and alloy materials containing the aforementioned metals.

[0073] It should be noted that by surrounding the gate 130 around the channel region 123, the contact area between the gate 130 and the channel 123 can be increased, so that the cross-sectional area of ​​current transmission in the channel region 123 is increased, thereby making the corresponding resistance smaller and the current higher. In one embodiment, the gate 130 is cylindrical in shape.

[0074] In one embodiment, the material of the gate dielectric layer 140 includes a high dielectric constant material. The high dielectric constant material has a dielectric constant of about greater than 7. Optionally, the high dielectric constant material can be an oxide material containing hafnium (Hf-based), for example, it can be a non-crystalline hafnium silicon oxynitride (HfSiON); a stacked structure formed by stacking nitride and high dielectric constant materials can also be used as a high dielectric constant material layer. In other embodiments of the present application, the high dielectric constant material layer can include at least one of the elements hafnium (Hf), silicon (Si), oxygen (O) or nitrogen (N), and can also include tantalum oxide, lanthanum oxide, aluminum oxide, nitrogen oxide or other commonly used high dielectric constant materials. This is common knowledge known to those skilled in the art, and this application will not be expanded here.

[0075] It should be noted that when the gate 130 is a metal gate and the gate dielectric layer 140 is a high dielectric constant (High-K) material layer, the gate capacitance can be increased by reducing the thickness of the gate dielectric layer 140 when the gate length is very small, thereby improving the control ability of the gate 130 over the channel and adjusting the threshold voltage at the same time.

[0076] Accordingly, see Figure 4 One embodiment of the present application further provides a method for manufacturing a semiconductor device, comprising:

[0077] Step S10: providing a substrate, forming an isolation layer on the substrate, and forming two parallel openings in the isolation layer;

[0078] Step S20: forming an active area, a gate and a gate dielectric layer on the isolation layer, wherein the active area includes a source area, a channel area and a drain area connected in sequence, the source area and the drain area are respectively formed in one of the openings, the channel area is formed above the isolation layer and arranged parallel to the surface of the substrate, the gate surrounds the channel area along an extension direction of the channel area, and the gate dielectric layer is formed between the gate and the channel area.

[0079] It can be seen that the manufacturing method of the above-mentioned semiconductor device can realize the manufacturing process of the semiconductor device mentioned above in this application through a combination of existing process steps without adopting special processes or complex processes, thereby reducing the manufacturing difficulty and production cost of the semiconductor device.

[0080] Figures 5 to 20 The following is a schematic diagram of the structures corresponding to different steps in the method for manufacturing a semiconductor device provided in this application. Figures 5 to 20 The method for manufacturing the semiconductor device provided by the present application is described in detail.

[0081] First, see Figures 5 to 7 , perform step S10, provide a substrate 100, form an isolation layer 110 on the substrate 100, and form two parallel openings 111 in the isolation layer 110. It should be noted that the formation of the isolation layer 110 can avoid the risk of short circuit between the subsequently formed gate and the subsequently formed source and drain, and reduce or avoid ion diffusion of the source and drain.

[0082] In one embodiment, the process of forming the isolation layer 110 having the opening 111 on the substrate 100 includes: Figure 5 , forming a first isolation layer 112 on the substrate 100; Figure 6 , etching the first isolation layer 112 to form an opening 111 in the first isolation layer 112; Figure 7 , a second isolation layer 113 is formed on the first isolation layer 112, the second isolation layer 113 covers the inner wall of the opening 111, and the isolation layer 110 includes the first isolation layer 112 and the second isolation layer 113. Optionally, the isolation layer 110 can be formed by preparing the required film layer through furnace tube, yellow light, etching and other processes.

[0083] In one embodiment, the material of the first isolation layer 112 includes silicon oxide, and the material of the second isolation layer 113 includes silicon nitride. In other embodiments of the present application, the isolation layer 110 may be a single-layer structure made of an insulating material, or a stacked structure composed of at least two different insulating materials, which is not limited in the present application.

[0084] See also Figure 8 In one embodiment, the process of forming an active region, a gate and a gate dielectric layer on the isolation layer includes:

[0085] Step S21: forming a source region and a drain region in the opening respectively, and the tops of the source region and the drain region are higher than the surface of the isolation layer;

[0086] Step S22: forming a lower gate on the isolation layer between two adjacent openings, wherein a first trench is formed in the lower gate, and an extending direction of the first trench is parallel to a connecting direction of the two adjacent openings;

[0087] Step S23: forming a lower gate dielectric in the first trench, wherein a second trench is formed in the lower gate dielectric and an extension direction of the second trench is parallel to an extension direction of the first trench;

[0088] Step S24: forming a channel region in the second trench, wherein the channel region connects the source region and the drain region to form an active region of the semiconductor device;

[0089] Step S25: forming an upper gate dielectric layer on the channel region, wherein the upper gate dielectric layer is connected to the lower gate dielectric layer and forms a gate dielectric layer surrounding the channel region;

[0090] Step S26: forming an upper gate on the upper gate dielectric, wherein the upper gate is connected to the lower gate and forms a gate surrounding the channel region.

[0091] First, see Fig. 9 , performing step S21, forming a source region 121 and a drain region 122 in the opening 111, respectively, and the tops of the source region 121 and the drain region 122 are higher than the surface of the isolation layer 110. In one embodiment, the source region 121 and the drain region 122 can be formed by two epitaxy processes (EPI).

[0092] Next, see Figures 10 to 12 , executing step S22 , forming a lower gate 131 on the isolation layer 110 between two adjacent openings 111 , wherein a first trench 131 a is formed in the lower gate 131 , and an extending direction of the first trench 131 a is parallel to a connecting direction of the two adjacent openings 111 .

[0093] In one embodiment, the process of forming the lower gate 131 on the isolation layer 110 between two adjacent openings 111 includes: Fig.10 , forming a lower gate 131 on the isolation layer 110; performing a planarization process on the lower gate 131 so that the surface of the lower gate 131 is flush with the surfaces of the source region 121 and the drain region 122; referring to Fig.11 and Fig.12 , remove part of the lower gate 131 so that the remaining lower gate 131 is located between the two openings 111, and form a first groove 131a in the lower gate 131. Optionally, a chemical vapor deposition process (Chemical Vapor Deposition, CVD) is used to form the lower gate 131. Optionally, a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP) is used for planarization. Optionally, a process such as yellow light and etching is used to form the first groove 131a in the lower gate 131.

[0094] Then, see Fig.13 and Fig.14 , executing step S23, forming a lower gate dielectric 141 in the first trench 131a, and forming a second trench 141a in the lower gate dielectric 141, and the extension direction of the second trench 141a is parallel to the extension direction of the first trench 131a.

[0095] In one embodiment, the process of forming the lower gate dielectric 141 in the first trench 131a includes: Fig.13 and Fig.14 , forming a lower gate dielectric 141 on the inner wall of the first trench 131a, the lower gate dielectric 141 at least extending and covering the lower gate 131, the source region 121 and the drain region 122 around the first trench 131a; etching the lower gate dielectric 141 so that the remaining lower gate dielectric 141 is located on the inner wall of the first trench 131a, and a second trench 141a is formed in the lower gate dielectric 141. Optionally, the lower gate dielectric 141 is etched by processes such as yellow light and etching.

[0096] In one embodiment, the lower gate 131 and the lower gate dielectric 141 can be etched separately by respectively performing positive and negative development in the case of using the same photomask (not shown in the figure). Exemplarily, in the process of photolithography and etching the lower gate 131 using the photomask, the positive photoresist covering the surface of the portion of the lower gate 131 located in the first groove 131a is removed during the development process, thereby forming the first groove 131a in the lower gate 131; and in the process of photolithography and etching the lower gate dielectric 141 using the photomask, the negative photoresist covering the surface of the portion of the lower gate dielectric 141 located in the first groove 131a is not removed during the development process, so that the remaining lower gate dielectric 141 after etching is all located on the inner wall of the first groove 131a. This method can save one photomask, thereby saving production costs.

[0097] Then, see Fig.15 and Fig.16 , step S24 is performed to form a channel region 123 in the second trench 141a, the channel region 123 connects the source region 121 and the drain region 122 to form an active region 120 of the semiconductor device. It should be noted that the cross section of the active region 120 along the vertical AB direction forms a U-shaped morphology with an opening downward (for example, see Figure 3 ), which can effectively save the plane area of ​​semiconductor devices and help to further reduce the size of semiconductor devices.

[0098] See also Fig.17 and Fig.18, executing step S25 , forming an upper gate dielectric 142 on the channel region 123 , the upper gate dielectric 142 is connected to the lower gate dielectric 141 and forms a gate dielectric layer 140 surrounding the channel region 123 .

[0099] In one embodiment, the material of the gate 130 includes a metal material, and the metal material includes at least one of metal copper (Cu), metal aluminum (Al), and metal tungsten (Wu). In other embodiments of the present application, the metal material also includes other commonly used conductive metal materials and alloy materials containing the aforementioned metals.

[0100] See also Fig.19 and Fig. 20 , executing step S26 , forming an upper gate 132 on the upper gate dielectric 142 , the upper gate 132 and the lower gate 131 are connected to form a gate 130 surrounding the channel region 123 .

[0101] In one embodiment, the material of the gate dielectric layer 140 includes a high dielectric constant material. The high dielectric constant material has a dielectric constant of about greater than 7. Optionally, the high dielectric constant material can be an oxide material containing hafnium (Hf-based), for example, it can be a non-crystalline hafnium silicon oxynitride (HfSiON); a stacked structure formed by stacking nitride and high dielectric constant materials can also be used as a high dielectric constant material layer. In other embodiments of the present application, the high dielectric constant material layer can include at least one of the elements hafnium (Hf), silicon (Si), oxygen (O) or nitrogen (N), and can also include tantalum oxide, lanthanum oxide, aluminum oxide, nitrogen oxide or other commonly used high dielectric constant materials. This is common knowledge known to those skilled in the art, and this application will not be expanded here.

[0102] The unexpected effects of the present application are: by setting a gate surrounding the channel region, the contact area between the gate and the channel region is increased, which is beneficial to increasing the current transmission cross-sectional area in the channel region, thereby improving the electric field control effect in the channel region; by setting an isolation layer between the gate and the substrate, the influence of the short channel effect on the performance of the semiconductor device is reduced or avoided.

[0103] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0104] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the application. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; An isolation layer, located on the substrate, wherein the isolation layer is provided with two openings parallel to each other; an active region, located on the isolation layer, the active region comprising a source region, a channel region and a drain region connected in sequence, wherein the source region and the drain region are respectively arranged in one of the openings, and the channel region is located above the isolation layer and parallel to the surface of the substrate; A gate, arranged around the channel region along an extension direction of the channel region; The gate dielectric layer is arranged between the gate and the channel region.

2. The semiconductor device according to claim 1, wherein: The cross-sectional shape of the active region along a direction perpendicular to the substrate is U-shaped with an opening facing downward.

3. The semiconductor device according to claim 1, wherein: The isolation layer comprises: A first isolation layer, located on the substrate, wherein the first isolation layer is provided with the opening; The second isolation layer covers the inner wall of the opening and the surface of the first isolation layer away from the substrate.

4. The semiconductor device according to claim 3, characterized in that The material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes silicon nitride.

5. The semiconductor device according to claim 1, wherein: The material of the gate electrode includes a metal material, and the metal material includes at least one of metal copper, metal aluminum, and metal tungsten; the material of the gate dielectric layer includes a high dielectric constant material.

6. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, forming an isolation layer on the substrate, and forming two openings parallel to each other in the isolation layer; An active region, a gate and a gate dielectric layer are formed on the isolation layer, wherein the active region is formed with a source region, a channel region and a drain region connected in sequence, the source region and the drain region are respectively formed in one of the openings, the channel region is formed above the isolation layer and is parallel to the surface of the substrate, the gate surrounds the channel region along an extension direction of the channel region, and the gate dielectric layer is formed between the gate and the channel region.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The step of forming an active region, a gate and a gate dielectric layer on the isolation layer comprises: forming a source region and a drain region in the opening respectively, and the tops of the source region and the drain region are higher than the surface of the isolation layer; A lower gate is formed on the isolation layer between two adjacent openings, wherein a first trench is formed in the lower gate, and an extending direction of the first trench is parallel to a connecting direction of the two adjacent openings; forming a lower gate dielectric in the first trench, wherein a second trench is formed in the lower gate dielectric and an extension direction of the second trench is parallel to an extension direction of the first trench; forming a channel region in the second trench, wherein the channel region connects the source region and the drain region to form an active region of the semiconductor device; forming an upper gate dielectric layer on the channel region, wherein the upper gate dielectric layer is connected to the lower gate dielectric layer and forms a gate dielectric layer surrounding the channel region; An upper gate is formed on the upper gate dielectric, and the upper gate is connected to the lower gate to form a gate surrounding the channel region.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The step of forming a lower gate on the isolation layer between two adjacent openings comprises: forming a lower gate on the isolation layer; Performing a planarization process on the lower gate to make the surface of the lower gate flush with the surfaces of the source region and the drain region; A portion of the lower gate is removed so that the remaining lower gate is located between the two openings, and the first trench is formed in the lower gate.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: The step of forming a lower gate dielectric in the first trench comprises: forming the lower gate dielectric on the inner wall of the first trench, wherein the lower gate dielectric at least extends to and covers the lower gate, the source region and the drain region around the first trench; The lower gate dielectric is etched so that the remaining lower gate dielectric is located on the inner wall of the first trench and the second trench is formed in the lower gate dielectric.

10. The method for manufacturing a semiconductor device according to claim 6, wherein: The isolation layer includes a first isolation layer and a second isolation layer, and the step of forming the isolation layer on the substrate, wherein two parallel openings are formed in the isolation layer, includes: forming the first isolation layer on the substrate; Etching the first isolation layer to form the opening in the first isolation layer; The second isolation layer is formed on the first isolation layer, and the second isolation layer covers the inner wall of the opening.

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