Heterojunction battery piece preparation method and heterojunction battery piece

Abstract

The invention provides a preparation method of a heterojunction battery piece, and relates to the technical field of photovoltaic products, and the method comprises the steps: obtaining a silicon wafer; texturing and cleaning the silicon wafer; smoothing the edge area of the first surface of the silicon wafer, the edge area of the second surface of the silicon wafer and a third surface connected with the first surface and the second surface, reserving a pyramid suede of the central area of the first surface and the central area of the second surface, and forming a smooth suede between the smooth surface and the pyramid suede to obtain a battery piece; and sequentially preparing an intrinsic layer, a doped layer and a transparent conductive layer on the first surface and the second surface of the battery piece, and manufacturing electrodes to obtain a target battery. According to the invention, the photoelectric conversion efficiency of the target battery piece is ensured, the mechanical load bending strength of the target battery piece is improved, and the risk of breakage of the target battery piece is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic products, and in particular to a method for preparing a heterojunction solar cell and a heterojunction solar cell. Background Art

[0002] At present, crystalline silicon photovoltaic cells are the most widely used solar cells in today's society and can be seen everywhere in daily life. In addition to the large-scale application of conventional solar cells in ground photovoltaic power stations and distributed photovoltaics, crystalline silicon photovoltaic cells also have huge development space in the fields of wearable electronics, mobile communications, vehicle-mounted mobile energy, photovoltaic building integration, aerospace, etc.

[0003] Among them, the main cost of monocrystalline silicon photovoltaic cells comes from monocrystalline silicon wafers. Reducing the thickness of monocrystalline silicon wafers is an effective technical path to reduce the cost of silicon wafers. At the same time, reducing the thickness of monocrystalline silicon wafers can improve the flexibility of silicon wafers.

[0004] However, the monocrystalline silicon wafer used to prepare the monocrystalline silicon photovoltaic cell is a brittle material. After cleaning and texturing, pyramid velvet exists on the edge, surface and side of the cell, which makes the stress easily concentrated on the bottom of the pyramid at the edges of both sides of the cell during the bending process of the cell. Chinese patent application number CN116435403A proposes stacking texturing silicon wafers and performing plasma edge etching of silicon to achieve smooth velvet in the edge area. In the process of etching the pyramids at the edge of the silicon wafer, this method is prone to produce new surface undulations and introduce new stress concentration points, resulting in a decrease in the bending strength of the silicon wafer instead of an increase. Chinese patent application number CN116230787A proposes applying glue to the edge of the polished silicon wafer, drying it as a mask protection, texturing the middle of the silicon wafer, and then removing the glue to form a silicon wafer with polished edges and velvet in the middle. This method is complicated, and the coating cost of the adhesive film and the treatment of organic wastewater are high, which is not suitable for mass production.

[0005] Therefore, it is necessary to find new methods for preparing silicon wafers with smooth edges, improve the bending strength, improve the flexibility of HJT cells, and expand the application scope of HJT cells. Summary of the invention

[0006] In view of this, an object of the present invention is to provide a method for preparing a heterojunction cell and a heterojunction cell, so as to alleviate the technical problems of low mechanical load bending strength and fragility of heterojunction photovoltaic cells in the prior art.

[0007] In a first aspect, an embodiment of the present invention provides a method for preparing a heterojunction cell, the method comprising: Obtain silicon wafers; Texturing and cleaning of silicon wafers; Smoothing the edge area of ​​the first surface, the edge area of ​​the second surface and the third surface connecting the first surface and the second surface of the silicon wafer, retaining the pyramid velvet surface of the central area of ​​the first surface and the central area of ​​the second surface, and forming a smooth velvet surface area between the smooth surface and the pyramid velvet surface, to obtain a battery cell; An intrinsic layer, a doping layer and a transparent conductive layer are sequentially prepared on the first surface and the second surface of the battery cell, and electrodes are manufactured to obtain a target battery cell.

[0008] In combination with the first aspect, the embodiment of the present invention provides a first possible implementation manner of the first aspect, wherein the edge area of ​​the first surface, the edge area of ​​the second surface, and a third surface connecting the first surface and the second surface of the silicon wafer are smoothed, the suede surface of the central area of ​​the first surface and the central area of ​​the second surface is retained, and a smooth suede surface area is formed between the smooth surface and the suede surface, and the step of obtaining the battery cell includes: Depositing a dielectric film on the first surface and the second surface after texturing; Performing plasma etching on the edge region of the first surface and the edge region of the second surface; Polishing the etched area using an alkaline chemical solution; Using hydrofluoric acid solution to remove the remaining dielectric film; After cleaning and removing the film from the silicon wafer, a battery cell with a smooth edge area, a pyramid velvet surface in the center area and a smooth velvet area between the smooth surface and the pyramid velvet surface is obtained.

[0009] In combination with the first aspect, the embodiment of the present invention provides a first possible implementation of the first aspect, the step of depositing a dielectric film on the first surface and the second surface after texturing, comprising: The dielectric film is deposited on both sides of the silicon wafer by thermal oxidation.

[0010] In combination with the first aspect, an embodiment of the present invention provides a first possible implementation manner of the first aspect, wherein the step of performing plasma etching on the edge region of the first surface and the edge region of the second surface includes: A plurality of silicon wafers are stacked, and the center area of ​​the top surface of the silicon wafer at the top and the center area of ​​the bottom surface of the silicon wafer at the bottom are clamped, and the stacked plurality of silicon wafers are simultaneously subjected to plasma etching treatment.

[0011] In combination with the first aspect, an embodiment of the present invention provides a first possible implementation of the first aspect, wherein a plurality of silicon wafers are stacked, and the central area of ​​the top surface of the silicon wafer at the top and the central area of ​​the bottom surface of the silicon wafer at the bottom are clamped, and the steps of simultaneously performing plasma etching on the stacked plurality of silicon wafers include: Put multiple stacked and clamped silicon wafers into a plasma etcher, and introduce carbon tetrafluoride and oxygen into the plasma etcher to perform plasma etching on the silicon wafers by means of high-frequency glow discharge.

[0012] In combination with the first aspect, the embodiment of the present invention provides a first possible implementation manner of the first aspect, wherein the step of plasma etching the edge region of the first surface and the edge region of the second surface further includes: The etching width of the edge region of the first surface and the edge region of the second surface is 0.5 mm-5 mm.

[0013] In combination with the first aspect, the embodiment of the present invention provides a first possible implementation manner of the first aspect, the step of cleaning the silicon wafer after film removal to obtain a solar cell having a smooth surface in the edge area, a pyramid velvet surface in the center area, and a smooth velvet surface between the smooth surface and the pyramid velvet surface, comprises: Forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the first surface and the second surface in sequence by chemical vapor deposition; Forming a transparent conductive layer on the doped amorphous silicon layer by physical vapor deposition; A metal grid line electrode is formed on the transparent conductive layer by printing.

[0014] In a second aspect, the present application provides a heterojunction cell, which is prepared by the provided method, and includes: a silicon wafer; The silicon wafer has a first surface, a second surface and a third surface, the first surface and the second surface are parallel, and the third surface connects the first surface and the second surface respectively; The edge area of ​​the first surface, the edge area of ​​the second surface and the third surface are all smooth surfaces, the central area of ​​the first surface and the central area of ​​the second surface are pyramid suede surfaces, and the smooth surface and the suede surface are between the smooth surface and the suede surface.

[0015] Furthermore, a first intrinsic layer, a first doped layer, a first transparent conductive layer and a first electrode are sequentially arranged on the first surface; A second intrinsic layer, a second doped layer, a second transparent conductive layer and a second electrode are sequentially arranged on the second surface.

[0016] Furthermore, the width of the smooth surface is 0.5 mm-5 mm; the thickness of the smooth surface is less than the thickness of the pyramid velvet surface.

[0017] The embodiments of the present invention bring the following beneficial effects: The present invention provides a method for preparing a heterojunction battery cell, the method comprising: obtaining a silicon wafer; texturing and cleaning the silicon wafer; smoothing an edge area of ​​a first surface, an edge area of ​​a second surface and a third surface connecting the first surface and the second surface of the silicon wafer, retaining a pyramid velvet surface in a central area of ​​the first surface and a central area of ​​the second surface, and forming a smooth velvet surface between the smooth surface and the pyramid velvet surface, to obtain a battery cell; sequentially preparing an intrinsic layer, a doping layer and a transparent conductive layer on the first surface and the second surface of the battery cell and making electrodes, to obtain a target battery cell.

[0018] Specifically, the present invention performs smoothing on the edge area of ​​the first surface, the edge area of ​​the second surface, and the velvet surface of the third surface of the silicon wafer, and retains the pyramid velvet surface in the central area of ​​the first surface and the second surface to ensure the photoelectric conversion efficiency of the target cell, while the surface of the smooth surface has no sharp defects. In addition, a rounded velvet area with a pyramid tip, corners, and bottom of the pyramid with rounded corners is generated between the pyramid velvet surface and the smooth surface. When the target cell is subjected to mechanical shock and vibration, the rounded velvet area and the smooth surface will consume more energy during the fracture process, avoiding stress concentration at the bottom of the valley of the edge pyramid structure when the silicon wafer is bent, causing the silicon wafer to break, and avoiding the edge area of ​​the first surface and the second surface of the target cell from being broken due to the concentration of force at the sharp defects in the velvet surface and the target cell being too thin. Thereby, while ensuring the photoelectric conversion efficiency of the target cell, the mechanical load bending strength of the target cell is improved, and the risk of the target cell breaking is reduced.

[0019] The present invention also provides a heterojunction solar cell, which is prepared by the provided method, comprising: a silicon wafer; the silicon wafer has a first surface, a second surface and a third surface, the first surface and the second surface are parallel, and the third surface connects the first surface and the second surface respectively; the edge area of ​​the first surface, the edge area of ​​the second surface and the third surface are all smooth surfaces, the central area of ​​the first surface and the central area of ​​the second surface are pyramid velvet surfaces, and the smooth surface and the velvet surface are between the smooth surface and the velvet surface.

[0020] The edge area of ​​the first surface, the edge area of ​​the second surface and the third surface of the battery cell provided by the present invention are all smooth surfaces, the central area of ​​the first surface and the central area of ​​the second surface are pyramid velvet surfaces, and there is a smooth velvet surface between the smooth surface and the pyramid velvet surfaces, the smooth surface and the smooth velvet surfaces will consume more energy during the fracture process, and the pyramid velvet surfaces in the central areas of the first surface and the second surface can ensure the photoelectric conversion efficiency of the heterojunction battery cell. Therefore, the battery cell provided by the present invention can avoid the phenomenon that the defects of the velvet surfaces at the edges of the first surface and the second surface relative to each other are broken due to concentrated force and excessive thinness, while ensuring the photoelectric conversion efficiency of the heterojunction battery cell, thereby improving the mechanical load bending strength of the heterojunction battery cell, and then reducing the risk of heterojunction battery cell breaking.

[0021] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0022] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic diagram of the process of preparing a heterojunction cell provided in Example 1 of the present invention; Figure 2 A schematic diagram of the process of preparing a heterojunction cell provided in Example 2 of the present invention; Figure 3 This is a schematic diagram of the structure of the heterojunction solar cell provided in Example 3 of the present invention.

[0025] Figure Number: 100-silicon wafer; 110-pyramid velvet surface; 120-smooth surface; 130-rounded velvet surface; 200-first intrinsic layer; 300-first doped layer; 400-first transparent conductive layer; 500-first electrode; 600-second intrinsic layer; 700-second doped layer; 800-second transparent conductive layer; 900-second electrode. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0027] In order to facilitate the understanding of this embodiment, the technical terms designed in this application are briefly introduced below.

[0028] Photovoltaic cell texturing is a process of creating tiny texture structures on the surface of silicon wafers, aiming to reduce the reflection of sunlight, enhance light absorption, and thus improve the efficiency of the cell. Texturing is a process for processing solar-grade silicon wafers in the photovoltaic industry, and is a process in the production of silicon solar cells. The specific principle of texturing is to use low-concentration alkaline solutions to have different corrosion rates on different crystal planes (anisotropic corrosion) to form a pyramid (pyramid) structure on the surface of the silicon wafer. This structure can reduce the reflection of sunlight, increase the absorption of light by the silicon wafer, and thus improve the efficiency of photoelectric conversion.

[0029] Photovoltaic cell etching refers to the process of selectively removing unwanted materials from the surface of silicon wafers by physical or chemical methods. This process aims to corrode the surface of silicon wafers that are not covered by photoresist, thereby achieving the final transfer of patterns. Etching plays a vital role in the manufacture of photovoltaic cells, which is directly related to the performance and efficiency of the cells. Etching technology is mainly divided into two categories: wet etching and dry etching. Wet etching uses chemical reagents to react with the etched materials to generate soluble or volatile substances, thereby removing unwanted materials. This method has simple equipment and low cost, but poor controllability, and is suitable for the production of large-scale graphics. Dry etching removes materials by physical or chemical methods, including reactive ion etching, plasma etching, etc., and has the advantages of good anisotropy and strong controllability. Etching technology is widely used in photovoltaic cell manufacturing. For example, in the production of crystalline silicon solar cells, the etching process is used to create a specific texture surface to improve the absorption and conversion efficiency of light. In addition, etching is also used to remove the damaged layer on the surface of the silicon wafer to ensure the quality and performance of the battery.

[0030] CVD is the abbreviation of Chemical Vapor Deposition. This technology is a chemical reaction process that heats one or more gases (called precursors) to decompose them, produce reaction products, and deposit them on the surface of the semiconductor to form the desired thin film.

[0031] ‌PECVD (Plasma Enhanced Chemical Vapor Deposition) is a thin film growth technology that uses plasma for deposition at a relatively low temperature. ‌PECVD activates gas molecules through radio frequency (RF) to cause a chemical reaction at low temperature (room temperature), thereby depositing a thin film on the surface of the substrate. This technology is mainly used to deposit thin films such as amorphous silicon, microcrystalline silicon, silicon germanium, and silicon nitride. In the production of photovoltaic cells, PECVD is mainly used to prepare anti-reflection films and intrinsic layers. The function of the anti-reflection film is to reduce the light reflectivity and improve the utilization rate of photons, thereby increasing the number of photogenerated carriers; the intrinsic layer is used to passivate the dangling bonds on the surface of the silicon wafer, reduce surface traps, and increase the life of minority carriers. Through PECVD technology, a thin film with an appropriate refractive index can be deposited on the surface of the silicon wafer to form a refractive index gradient, and the reflectivity can be reduced by using the principle of optical reflection, thereby improving the conversion efficiency of photovoltaic cells.

[0032] LPCVD (Low Pressure Chemical Vapor Deposition) is a chemical vapor deposition process performed at a relatively low pressure. It reduces the pressure in the reaction chamber so that the movement rate of the gaseous precursor molecules is slower than the chemical reaction rate, thereby improving the quality of the film. LPCVD relies on heating equipment as a heat source to maintain the reaction, and temperature control and gas pressure control are very important. This process is widely used to create various thin films, such as silicon oxide and silicon nitride, and is also used to make doped films and metal films. The advantages of LPCVD include better step coverage, high-quality film formation, and controllable film composition and structure, but the disadvantages include high energy consumption, high cost of quartz consumables, and poor compatibility with silicon wafers of different sizes.

[0033] RPD deposition (catalytic chemical vapor deposition) is a method of material deposition using plasma technology. Its basic principle is to generate a plasma flow through a plasma generator, which is deflected by a magnetic field and hits the substrate to be deposited, thereby achieving material deposition.

[0034] Cat-CVD (Catalytic Chemical Vapor Deposition) is a chemical vapor deposition (CVD) technology that achieves precise control and optimization of thin film materials by controlling the chemical composition of the reaction gas and reaction conditions.

[0035] ITO (Indium Tin Oxides) is an N-type oxide semiconductor with the chemical formula In2O3-SnO2, also known as indium tin oxide. ITO film is a transparent conductive film that usually has two main performance indicators: resistivity and transmittance. ITO film has high transmittance and high conductivity, which makes it widely used in the optoelectronic industry.

[0036] After introducing the technical terms involved in this application, the application scenarios and design concepts of the embodiments of this application are briefly introduced.

[0037] Because the existing heterojunction photovoltaic cells are directly subjected to the PECVD process after double-sided texturing, this will result in the front, back and sides of the photovoltaic cells being all pyramid-structured texturing, with low mechanical load bending strength and very easy to break, especially thin heterojunction photovoltaic cells.

[0038] Example 1 See also Figure 1 The present embodiment provides a method for preparing a heterojunction cell, the method comprising: S100, obtaining a silicon wafer.

[0039] S200, texturing and cleaning the silicon wafer.

[0040] S300, smoothing the edge area of ​​the first surface, the edge area of ​​the second surface and the third surface connecting the first surface and the second surface of the silicon wafer, retaining the pyramid velvet surface of the central area of ​​the first surface and the central area of ​​the second surface, and forming a smooth velvet surface area between the smooth surface and the pyramid velvet surface, to obtain a battery cell.

[0041] S400, sequentially preparing an intrinsic layer, a doping layer and a transparent conductive layer on a first surface and a second surface of the cell and manufacturing electrodes to obtain a target cell.

[0042] In this embodiment, the edge area of ​​the first surface, the edge area of ​​the second surface and the velvet surface of the third surface of the silicon wafer 100 are smoothed, and the surface has no sharp defects, and the pyramid velvet surface 110 is retained in the central area of ​​the first surface and the second surface.

[0043] In addition, a smooth velvet surface 130 with rounded corners at the top, corners and bottom of the pyramid is generated between the pyramid velvet surface 110 and the smooth surface 120. When the target cell is subjected to mechanical shock and vibration, the smooth velvet surface 130 and the smooth surface 120 will consume more energy during the fracture process, thereby preventing the stress from being concentrated at the bottom of the valley of the edge pyramid structure when the silicon wafer 100 is bent, causing the silicon wafer 100 to break.

[0044] The smooth velvet surface 130 forms a transition zone between the smooth surface 120 and the pyramid velvet surface 110. In the transition zone formed by the smooth velvet surface 130, the pyramid still exists, but the top, corners, and bottom of the pyramid are all etched smoothly, which can prevent the stress from concentrating at the bottom of the edge pyramid when the silicon wafer 100 is bent, causing the silicon wafer 100 to break, greatly improving the bending strength of the silicon wafer 100, and avoiding the edge areas of the first surface and the second surface of the target battery cell from breaking due to the concentrated force at the sharp defects in the velvet surface and the target battery cell being too thin.

[0045] The large area of ​​velvet retained in the central area of ​​the first surface and the second surface of the target cell in this embodiment ensures the photoelectric conversion efficiency of the target cell, while ensuring the photoelectric conversion efficiency of the target cell, improving the mechanical load bending strength of the target cell and reducing the risk of breakage of the target cell.

[0046] In addition, it should be noted that the silicon wafer 100 in this embodiment is a single crystal silicon wafer 100, specifically an n-type doped or p-type doped single crystal silicon wafer 100, and can also be a CZ single crystal or an ingot single crystal, and the thickness of the single crystal silicon wafer 100 ranges from 50 um to 150 um. The polished area at the edge of the silicon wafer 100 is 0.5 um to 5 um thinner than the velvet area in the middle.

[0047] Example 2 See also Figure 2 The method for preparing a heterojunction cell provided in this embodiment includes: S100, obtaining a silicon wafer.

[0048] S200, texturing and cleaning the silicon wafer.

[0049] S310, depositing a dielectric film on the first surface and the second surface after texturing.

[0050] S320, performing plasma etching on the edge region of the first surface and the edge region of the second surface.

[0051] S330, polishing the etched area using an alkaline chemical solution.

[0052] S340, using a hydrofluoric acid solution to remove the remaining dielectric film.

[0053] S350, cleaning the silicon wafer after film removal, and obtaining a solar cell with a smooth edge area, a pyramid velvet surface in the center area, and a smooth velvet area between the smooth surface and the pyramid velvet surface.

[0054] S400, sequentially preparing an intrinsic layer, a doping layer and a transparent conductive layer on a first surface and a second surface of the cell and manufacturing electrodes to obtain a target cell.

[0055] Specifically, in the texturing process of this embodiment, all surfaces of the silicon wafer 100 are texturized by using an alkaline texturing solution and a texturing additive, and the temperature is maintained at 65-85°C, and the surface of the silicon wafer 100 is cleaned with an acid-base solution to achieve texturing of the entire surface of the silicon wafer 100.

[0056] After the silicon wafer 100 is textured, a dielectric film is prepared on the first surface and the second surface of the silicon wafer 100. The dielectric film can protect the pyramid velvet surface 110 covered by the dielectric film to prevent the velvet surface to be retained from being processed into a smooth surface during the polishing process. Subsequently, the edge area of ​​the first surface and the edge area of ​​the second surface are plasma etched to peel off the dielectric film covering the edge area of ​​the first surface and the edge area of ​​the second surface, exposing the silicon wafer 100 in the edge area of ​​the first surface and the edge area of ​​the second surface, and retaining the dielectric film in the center area of ​​the first surface and the center area of ​​the second surface.

[0057] The alkaline chemical solution can polish the area not covered by the dielectric film, thereby polishing the edge area of ​​the first surface, the edge area of ​​the second surface and the third surface, while retaining the suede surface covered by the dielectric film.

[0058] It should be noted that, during the plasma etching of the dielectric film at the edge area of ​​the first surface and the edge area of ​​the second surface, the dielectric film at the junction of the edge area of ​​the first surface and the central area of ​​the first surface, and the dielectric film at the junction of the edge area of ​​the second surface and the central area of ​​the second surface are thinned but not completely removed under the action of plasma etching, and the pyramid velvet surface 110 in the area covered by this thinner dielectric film forms a smooth pyramid structure under the treatment of alkaline chemical solution, that is, the top, corners and valleys of the pyramid are all rounded.

[0059] In this embodiment, the alkaline texturing solution and the alkaline chemical solution in the polishing process are both potassium hydroxide solutions.

[0060] In this embodiment, step S310, the step of depositing a dielectric film on the first surface and the second surface after texturing includes: S311, depositing a dielectric film on both sides of the silicon wafer by thermal oxidation.

[0061] Specifically, in this embodiment, the dielectric film is a silicon dioxide film layer, the temperature of the thermal oxidation treatment is 800° C.-900° C., and the thickness of the formed silicon dioxide film layer is 10 nm.

[0062] As an implementable method, double-sided deposition of the mask layer can also be achieved through LPCVD or PECVD process.

[0063] In this embodiment, step S320, the step of performing plasma etching on the edge region of the first surface and the edge region of the second surface includes: S321, stacking a plurality of silicon wafers, clamping the center area of ​​the top surface of the top silicon wafer and the center area of ​​the bottom surface of the bottom silicon wafer, and simultaneously performing plasma etching on the stacked plurality of silicon wafers.

[0064] After multiple silicon wafers 100 are stacked, the central area of ​​the first surface of the top silicon wafer 100 and the central area of ​​the second surface of the bottom silicon wafer 100 are clamped so that the multiple silicon wafers 100 are stacked together, and the stacked silicon wafers 100 are etched at the same time. The etching efficiency is high, and it can ensure that the central area of ​​the stacked silicon wafers 100 is not etched, and the silicon dioxide film layer in the central area is retained.

[0065] The number of silicon wafers 100 may be 200 to 300, so that stacked silicon wafers 100 can be etched simultaneously. In this embodiment, the specific number of silicon wafers 100 is 200.

[0066] Specifically, in this embodiment, step S321, stacking a plurality of silicon wafers, clamping the center area of ​​the top surface of the top silicon wafer and the center area of ​​the bottom surface of the bottom silicon wafer, and simultaneously performing plasma etching on the stacked plurality of silicon wafers also includes: S3210, placing the stacked and clamped multiple silicon wafers into a plasma etcher, and introducing carbon tetrafluoride and oxygen into the plasma etcher to perform plasma etching on the silicon wafers by means of high-frequency glow discharge.

[0067] Among them, carbon tetrafluoride is a reaction gas, and by controlling the power and reaction time, the edge area of ​​the first surface, the edge area of ​​the second surface and the third surface are etched to realize the stripping of the silicon dioxide film layer, exposing the silicon wafer 100 in the edge area of ​​the first surface and the edge area of ​​the second surface, and retaining the silicon dioxide film layer in the central area of ​​the first surface and the second surface.

[0068] Furthermore, in step S320, in the step of performing plasma etching on the edge region of the first surface and the edge region of the second surface, the etching width of the edge region of the first surface and the edge region of the second surface is 0.5 mm-5 mm.

[0069] Specifically, in this embodiment, the etching width of the edge region of the first surface and the edge region of the second surface is specifically 1 mm.

[0070] In this embodiment, step S400, cleaning the silicon wafer after film removal to obtain a cell having a smooth surface in the edge region, a pyramid velvet surface in the center region, and a smooth velvet surface between the smooth surface and the pyramid velvet surface, comprises: S410, forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the first surface and the second surface in sequence by chemical vapor deposition.

[0071] S420, forming a transparent conductive layer on the doped amorphous silicon layer by physical vapor deposition.

[0072] S430, forming a metal grid line electrode on the transparent conductive layer by printing.

[0073] Specifically, in this embodiment, both the intrinsic layer and the doped layer can be formed by PECVD or Cat-CVD, and can be a composite film layer of one or more of undoped amorphous silicon, amorphous silicon oxide, and amorphous silicon carbide semiconductor films.

[0074] The transparent conductive layer can be prepared by magnetron sputtering or RPD deposition, and is specifically a composite layer of one or more of doped indium oxide, zinc oxide or tin oxide, with a thickness of 60-120 nm.

[0075] Furthermore, the metal grid electrode in this embodiment is specifically a composite layer of one or more of Ag, Cu, Al, and Ni, with a thickness of 10-50 um and a width of 5-50 um, and can be prepared by screen printing, inkjet printing, laser transfer, or electroplating.

[0076] Example 3 See also Figure 3 The heterojunction cell provided in this embodiment is prepared by the method provided in Embodiment 1 or Embodiment 2, and specifically includes a silicon wafer 100.

[0077] The silicon wafer 100 has a first surface, a second surface and a third surface, the first surface and the second surface are parallel, and the third surface connects the first surface and the second surface respectively. The edge area of ​​the first surface, the edge area of ​​the second surface and the third surface are all smooth surfaces 120, the central area of ​​the first surface and the central area of ​​the second surface are pyramid velvet surfaces 110, and the smooth velvet surface 130 is between the smooth surface 120 and the velvet surface.

[0078] The edge area of ​​the first surface, the edge area of ​​the second surface and the third surface of the battery cell provided in this embodiment are all smooth surfaces 120, the central area of ​​the first surface and the central area of ​​the second surface are pyramid velvet surfaces 110, and the smooth velvet surface 130 is between the smooth surface 120 and the pyramid velvet surface 110.

[0079] The smooth surface 120 and the smooth velvet surface 130 will consume more energy during the fracture process, and the smooth velvet surface 130 forms a transition zone between the smooth surface 120 and the pyramid velvet surface 110. In the transition zone formed by the smooth velvet surface 130, the pyramid still exists, but the top, corners, and bottom of the pyramid are all etched smooth, which can prevent the stress from concentrating on the bottom of the edge pyramid when the silicon wafer 100 is bent, causing the silicon wafer 100 to break, greatly improving the bending strength of the silicon wafer 100, and avoiding the edge areas of the first surface and the second surface of the battery cell from breaking due to the concentrated force at the sharp defects in the velvet surface and the battery cell being too thin.

[0080] Therefore, the heterojunction cell provided in this embodiment can avoid the phenomenon of cracking due to concentrated force and excessive thinness at the defects of the velvet surface relative to the edges of the first surface and the second surface while ensuring the photoelectric conversion efficiency of the heterojunction cell, thereby improving the mechanical load bending strength of the heterojunction cell and reducing the risk of cracking of the heterojunction cell.

[0081] In this embodiment, the first surface is sequentially provided with a first intrinsic layer 200, a first doped layer 300, a first transparent conductive layer 400 and a first electrode 500. The second surface is sequentially provided with a second intrinsic layer 600, a second doped layer 700, a second transparent conductive layer 800 and a second electrode 900.

[0082] Specifically, in this embodiment, the intrinsic layer on the front side of the silicon wafer 100 is a first intrinsic amorphous silicon with a thickness of 4-6nm and an n-type doped amorphous silicon film layer with a thickness of 5-10nm, and the back side of the silicon wafer 100 is a second intrinsic amorphous silicon with a thickness of 5-7nm and a p-type doped amorphous silicon film layer with a thickness of 8-15nm.

[0083] In this embodiment, the first transparent conductive layer 400 and the second transparent conductive layer 800 are made by magnetron sputtering. The first transparent conductive layer 400 is a 75nm ITO transparent conductive film deposited on an n-type doped amorphous silicon layer, and the second transparent conductive layer 800 is a 75nm ITO transparent conductive film deposited on a p-type doped amorphous germanium layer.

[0084] In addition, the mass percentage of indium in ITO is 90%, and the mass percentage of tin is 10%. The PVD equipment is filled with Ar and O2, the flow ratio of O2 to Ar is 0.025, the pressure is 0.5 Pa, and the substrate temperature is room temperature.

[0085] In addition, the first electrode 500 and the second electrode 900 in the present embodiment are metal gate line electrodes formed by curing low-temperature conductive metal paste.

[0086] The low-temperature metal paste may be one of low-temperature metal pastes such as silver-containing Ag, silver-coated copper, silver-coated aluminum, silver-coated glass, and silver-coated graphite.

[0087] In this embodiment, the width of the smooth surface 120 is 0.5 mm to 5 mm. The thickness of the smooth surface 120 is smaller than the thickness of the pyramid velvet surface 110 .

[0088] Under this structure, the mechanical load bending strength of the battery cell is very excellent, which significantly reduces the risk of rupture. In addition, in this embodiment, the thickness of the smooth surface 120 is 0.5-5 um less than the thickness of the pyramid velvet surface 110.

[0089] Example 4 In this embodiment, the battery cell provided in Embodiment 3 and the battery cell provided in the prior art were subjected to performance tests. An IV tester was used to measure various parameters of the solar cell, and a three-point test method was used to measure the bending strength of the battery cell. The results are shown in Table 1-1.

[0090] Table 1-1 is a schematic table of experimental parameters of the battery cell A provided in this embodiment and the battery cells B and C provided in the prior art.

[0091]

[0092] Among them, battery cell A is the battery cell provided in Example 3, and battery cell B is a battery cell prepared by the prior art.

[0093] Furthermore, the preparation method of the battery cell B is as follows: S1 Texturing and cleaning: Use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and form a surface pyramid texture on the surface of the single crystal silicon wafer to increase the absorption of sunlight and reduce reflection; the single crystal silicon wafer is a phosphorus-doped N-type single crystal silicon wafer with a resistivity of 0.1-10Ωcm and a thickness of 100-200um; then, use the RCA standard cleaning method to clean the surface of the silicon wafer to remove surface contamination impurities. Finally, use 2% hydrofluoric acid solution to remove the surface oxide layer.

[0094] S2: PECVD deposition of front and back intrinsic and doped amorphous silicon layers: Using PECVD deposition, a 4-6nm first intrinsic amorphous silicon layer and a 5-10nm n-type doped amorphous silicon film layer are formed on the front of the silicon wafer; a 5-7nm second intrinsic amorphous silicon layer and a 8-15nm p-type doped amorphous silicon film layer are formed on the back of the silicon wafer; S3: PVD deposition of transparent conductive layers on the front and back: PVD method is used to deposit a 75nm ITO transparent conductive film on the N-type doped amorphous silicon layer, and a 75nm ITO transparent conductive layer on the P-type doped amorphous layer. The mass percentage of indium in ITO is 90%, and the mass percentage of tin is 10%. The PVD equipment is filled with Ar and O2, the O2 to Ar flow ratio is 0.025, the pressure is 0.5Pa, and the substrate temperature is room temperature.

[0095] S4: Screen printing / curing of low-temperature metal paste on the front and back sides: Finally, low-temperature metal electrodes are formed on the front and back transparent conductive layers by low-temperature curing using screen printing.

[0096] The preparation method of battery cell C is as follows: S1 Texturing and cleaning: using acid and alkali chemicals to remove organic contamination and metal impurities on the surface of silicon wafers, forming a surface pyramid texture on the surface of single crystal silicon wafers to increase the absorption of sunlight and reduce reflection; the single crystal silicon wafers are phosphorus-doped N-type single crystal silicon wafers with a resistivity of 0.1-10Ωcm and a thickness of 100-200um; S2: Place the stacked silicon wafers in the ICP plasma etching chamber, use CF4 and O2 as reaction gases, control the power and reaction time, and etch the pyramids at the edge of the silicon wafers; S3: Then, the surface of the silicon wafer is cleaned using the RCA standard cleaning method to remove surface contaminants. Finally, a 2% hydrofluoric acid solution is used to remove the surface oxide layer.

[0097] S4: Prepare HJT cells using the above silicon wafers.

[0098] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0099] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0100] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0101] Finally, it should be noted that the above embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art can still modify the technical solutions recorded in the above embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for preparing a heterojunction cell, characterized in that: The method is as follows: Obtain silicon wafers; Texturing and cleaning the silicon wafer; Smoothing the edge area of ​​the first surface, the edge area of ​​the second surface, and the third surface connecting the first surface and the second surface of the silicon wafer, retaining the pyramid velvet surface of the central area of ​​the first surface and the central area of ​​the second surface, and forming a smooth velvet surface area between the smooth surface and the pyramid velvet surface, to obtain a battery cell; An intrinsic layer, a doping layer and a transparent conductive layer are sequentially prepared on the first surface and the second surface of the cell, and electrodes are manufactured to obtain a target cell.

2. The method according to claim 1, characterized in that The step of smoothing the edge area of ​​the first surface, the edge area of ​​the second surface and the third surface connecting the first surface and the second surface of the silicon wafer, retaining the velvet surface of the central area of ​​the first surface and the central area of ​​the second surface, and forming a smooth velvet surface between the smooth surface and the velvet surface to obtain the solar cell comprises: Depositing a dielectric film on the first surface and the second surface after texturing; Performing plasma etching on the edge area of ​​the first surface and the edge area of ​​the second surface; Polishing the etched area using an alkaline chemical solution; Using a hydrofluoric acid solution to remove the remaining dielectric film; After the silicon wafer is cleaned and the film is removed, a battery cell is obtained in which the edge area is a smooth surface, the central area is a pyramid velvet surface, and the smooth velvet surface is between the smooth surface and the pyramid velvet surface.

3. The method according to claim 2, characterized in that The step of depositing a dielectric film on the first surface and the second surface after texturing comprises: The dielectric film is deposited on both sides of the silicon wafer by thermal oxidation.

4. The method according to claim 2, characterized in that: The step of performing plasma etching on the edge area of ​​the first surface and the edge area of ​​the second surface comprises: The plurality of silicon wafers are stacked, and the center area of ​​the top surface of the silicon wafer at the top and the center area of ​​the bottom surface of the silicon wafer at the bottom are clamped, and the stacked plurality of silicon wafers are simultaneously subjected to plasma etching.

5. The method according to claim 4, characterized in that The step of stacking the plurality of silicon wafers, clamping the center area of ​​the top surface of the silicon wafer at the top and the center area of ​​the bottom surface of the silicon wafer at the bottom, and simultaneously performing plasma etching on the stacked plurality of silicon wafers comprises: The stacked and clamped plurality of silicon wafers are placed in a plasma etcher, and carbon tetrafluoride and oxygen are introduced into the plasma etcher to perform plasma etching on the silicon wafers by means of high-frequency glow discharge.

6. The method according to claim 5, characterized in that The step of performing plasma etching on the edge area of ​​the first surface and the edge area of ​​the second surface further includes: The etching width of the edge region of the first surface and the edge region of the second surface is 0.5 mm-5 mm.

7. The method according to claim 1, characterized in that The step of cleaning and removing the film from the silicon wafer to obtain a cell having a smooth surface at the edge region, a pyramid velvet surface at the center region, and a smooth velvet surface between the smooth surface and the pyramid velvet surface comprises: sequentially forming an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the first surface and the second surface by chemical vapor deposition; forming a transparent conductive layer on the doped amorphous silicon layer by physical vapor deposition; A metal grid line electrode is formed on the transparent conductive layer by printing.

8. A heterojunction cell, characterized in that: Prepared by the method according to any one of claims 1 to 7, characterized in that it comprises: a silicon wafer (100); The silicon wafer (100) has a first surface, a second surface and a third surface, the first surface and the second surface are parallel, and the third surface is connected to the first surface and the second surface respectively; The edge area of ​​the first surface, the edge area of ​​the second surface and the third surface are all smooth surfaces (120), the central area of ​​the first surface and the central area of ​​the second surface are pyramid velvet surfaces (110), and the smooth velvet surface (130) is between the smooth surface (120) and the velvet surfaces.

9. The heterojunction cell according to claim 8, characterized in that: A first intrinsic layer (200), a first doping layer (300), a first transparent conductive layer (400) and a first electrode (500) are sequentially arranged on the first surface; A second intrinsic layer (600), a second doping layer (700), a second transparent conductive layer (800) and a second electrode (900) are sequentially arranged on the second surface.

10. The heterojunction cell according to claim 9, characterized in that: The width of the smooth surface (120) is 0.5 mm to 5 mm; The thickness of the smooth surface (120) is smaller than the thickness of the pyramid velvet surface (110).

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