Display panel

Abstract

A display panel and a method of manufacturing the same are provided. The method of manufacturing the display panel may include: forming an oxide semiconductor pattern on a base layer including a first region and a second region; etching the first insulating layer, the second insulating layer and the third insulating layer to form a first groove overlapped with the second region; forming an electrode on the third insulating layer; forming a fourth insulating layer on the third insulating layer to cover the electrode; performing heat treatment on the fourth insulating layer; forming an organic layer to cover the fourth insulating layer; and forming an organic light emitting diode on the organic layer.

Description

[0001] This application is a divisional application of the invention patent application with the application date of December 6, 2018, application number "201811486068.X" and name "Display panel and its manufacturing method". Technical Field

[0002] The present disclosure relates to a display panel and a method for manufacturing the display panel, and in particular, to a high-reliability display panel and a method for manufacturing the high-reliability display panel. Background Art

[0003] The display panel includes a plurality of pixels and a driving circuit for controlling the pixels. The driving circuit of the display panel is configured to provide electrical control signals to the pixels.

[0004] Each pixel includes a pixel driving circuit and a display device such as an organic light emitting diode (OLED) or a quantum dot light emitting diode connected to the pixel driving circuit. The pixel driving circuit includes at least one thin film transistor and a capacitor. The thin film transistor and the capacitor of the pixel driving circuit control the display device based on the electrical signal received from one or more driving circuits of the display panel. Depending on the required electrical characteristics, the pixel driving circuit can be constructed to include two or more thin film transistors including at least two different semiconductor materials and properties. The pixel driving circuit including two or more thin film transistors can drive pixels in a more stable and reliable manner. Summary of the invention

[0005] Embodiments of the inventive concept provide a method of stably manufacturing a display panel.

[0006] Embodiments of the inventive concept provide a highly reliable display panel.

[0007] According to an embodiment of the inventive concept, a method for manufacturing a display panel may include: forming a silicon semiconductor pattern on a base layer including a first region and a second region extending from the first region, the silicon semiconductor pattern overlapping the first region; forming a first control electrode on the silicon semiconductor pattern, the first control electrode overlapping the silicon semiconductor pattern, and a first insulating layer interposed between the first control electrode and the silicon semiconductor pattern; forming a second control electrode to overlap with the first region and to be spaced apart from the first control electrode, and a second insulating layer interposed between the second control electrode and the first control electrode; forming an oxide semiconductor pattern on the second control electrode to overlap with the second control electrode, and a third insulating layer interposed between the oxide semiconductor pattern and the second control electrode; etching the first insulating layer, the second insulating layer, and the third insulating layer; an insulating layer and a third insulating layer to form a first contact hole and a second contact hole exposing at least a portion of the silicon semiconductor pattern and a first groove overlapping the second region; forming a first input electrode and a first output electrode and a second input electrode and a second output electrode on the third insulating layer, the first input electrode and the first output electrode being connected to the silicon semiconductor pattern through the first contact hole and the second contact hole, and the second input electrode and the second output electrode being connected to the oxide semiconductor pattern; forming a fourth insulating layer on the third insulating layer to cover the first input electrode, the first output electrode, the second input electrode and the second output electrode; heat treating the fourth insulating layer; forming an organic layer to cover the fourth insulating layer; and forming an organic light emitting diode connected to the first output electrode on the organic layer.

[0008] In an embodiment, the step of heat-treating the fourth insulating layer may be performed at a temperature of about 300° C. or higher.

[0009] In an embodiment, the organic layer may include polyimide.

[0010] In an embodiment, the steps of etching the first insulating layer, the second insulating layer, and the third insulating layer may be performed using a single mask to simultaneously form the first and second contact holes and the first recess.

[0011] In an embodiment, the method may further include forming a second groove overlapping the first groove in the fourth insulating layer after forming the fourth insulating layer. An organic layer may be formed to fill the first groove and the second groove.

[0012] In an embodiment, the method may further include forming an inorganic layer between the first insulating layer and the base layer. The step of forming the second groove may include forming a third groove in the inorganic layer overlapping the first groove.

[0013] In an embodiment, the method may further include: forming a third contact hole in the organic layer to expose a portion of the first output electrode; forming a connection electrode on the organic layer to be connected to the first output electrode through the third contact hole; and forming an upper organic layer on the organic layer to cover the connection electrode. The organic light emitting diode may be connected to the connection electrode through the upper organic layer.

[0014] In an embodiment, the connection electrode may be formed of a material different from that of the first output electrode.

[0015] In an embodiment, the connection electrode may be formed of a material having a lower resistance than that of the first output electrode.

[0016] In an embodiment, the step of forming the first input electrode, the first output electrode, the second input electrode, and the second output electrode may include: forming a conductive layer on the third insulating layer to cover the oxide semiconductor pattern; and patterning the conductive layer using an etching gas. The etching gas may contain a fluorine compound.

[0017] In an embodiment, in the step of patterning the conductive layer using the etching gas, the conductive layer may have an etching rate higher than an etching rate of the oxide semiconductor pattern.

[0018] According to an embodiment of the inventive concept, a display panel may include: a base layer including a first region and a second region bent from the first region around a specific bending axis; a first thin film transistor disposed in the first region, the first thin film transistor including a crystalline silicon semiconductor pattern, a first control electrode, and a first input electrode and a first output electrode bonded to the crystalline silicon semiconductor pattern and spaced apart from each other, and the first control electrode is placed between the crystalline silicon semiconductor pattern and the first input electrode and the first output electrode; a second thin film transistor disposed in the first region to have a bottom gate structure, the second thin film transistor including a second control electrode, an oxide semiconductor pattern disposed on the second control electrode, and a second input electrode and a second output electrode contacting the oxide semiconductor pattern and spaced apart from each other; a passivation layer disposed in the first region and the second region to cover the first thin film transistor and the second thin film transistor, and including a first groove overlapping the second region; a plurality of inorganic layers disposed between the passivation layer and the base layer, and including a second groove overlapping the first groove; an organic layer disposed in the first region and the second region and disposed on the passivation layer to cover inner surfaces of the first groove and the second groove; and an organic light emitting diode disposed on the organic layer and disposed in the first region and electrically connected to the first thin film transistor. An etching rate of the second input electrode and the second output electrode by the fluorine compound etching may be higher than an etching rate of the oxide semiconductor pattern by the fluorine compound etching.

[0019] In an embodiment, the second input electrode and the second output electrode may include molybdenum.

[0020] In an embodiment, the display panel may further include: an upper organic layer disposed between the organic layer and the organic light emitting diode; and a connecting electrode disposed between the upper organic layer and the organic layer and coupled to each of the organic light emitting diode and the first output electrode. The connecting electrode includes a material different from that of the first output electrode.

[0021] In an embodiment, the connection electrode may include a material having a lower resistance than that of the first output electrode.

[0022] In an embodiment, the display panel may further include a signal line disposed in the second region and overlapping the first groove and the second groove. The signal line may be disposed on the same layer as the connection electrode.

[0023] In an embodiment, the plurality of inorganic layers may be disposed to expose a portion of a top surface of the base layer, and the organic layer may be disposed to contact the portion of the top surface of the base layer.

[0024] In an embodiment, the display panel may further include a pixel defining layer disposed on the organic layer to define an opening. The organic light emitting diode may be disposed in the opening. The pixel defining layer may overlap the first region and the second region and may include an organic material.

[0025] In an embodiment, the pixel defining layer may further include a concave portion on an inner surface of the opening.

[0026] In an embodiment, the display panel may further include a signal line disposed in the second region and overlapping the first groove and the second groove. The signal line may be disposed on the same layer as the second output electrode.

[0027] In an embodiment, the signal line may include a plurality of patterns disposed in the second region and spaced apart from each other in a direction crossing the bending axis.

[0028] In embodiments, the passivation layer may be in contact with the oxide semiconductor pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0030] Figure 1A and Figure 1B is a perspective view illustrating a display panel according to an embodiment of the inventive concept.

[0031] Figure 2 yes Figure 1A A plan view of a display panel is shown in FIG.

[0032] Figure 3Ais an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept.

[0033] Figure 3B and Figure 3C Both show Figure 3A A cross-sectional view of a portion of a pixel.

[0034] FIG. 4A to FIG. 4C are cross-sectional views each illustrating a curved area of ​​a display panel according to an embodiment of the inventive concept.

[0035] Figure 5 is a cross-sectional view illustrating a region of a display panel according to an embodiment of the inventive concept.

[0036] Figure 6 is a cross-sectional view illustrating a region of a display panel according to an embodiment of the inventive concept.

[0037] FIG. 7A to FIG. 7Q is a cross-sectional view illustrating a process of manufacturing a display panel according to an embodiment of the inventive concept.

[0038] Fig. 8A is a graph showing current-voltage characteristics of a thin film transistor according to a comparative example.

[0039] Figure 8B is a graph showing current-voltage characteristics of a thin film transistor according to an embodiment of the inventive concept.

[0040] Fig. 9 is a cross-sectional view illustrating a portion of a display panel according to an embodiment of the inventive concept.

[0041] FIG. 10A to FIG. 10D is a cross-sectional view illustrating a method of manufacturing a display panel according to an embodiment of the inventive concept.

[0042] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures and / or materials used in certain example embodiments, and are intended to supplement the written description provided below. However, these drawings are not drawn to scale, do not accurately reflect the precise structure or performance characteristics of any given embodiment, and should not be interpreted as limiting or restricting the range or nature of the numerical values ​​included in the example embodiments. For example, for clarity, the relative thickness and position of molecules, layers, regions and / or structural elements can be reduced or exaggerated. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0043] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0044] Figure 1A and Figure 1B is a perspective view illustrating a display panel according to an embodiment of the inventive concept. Figure 2 yes Figure 1A A plan view of a display panel is shown in FIG. Figure 1A shows the display panel DP in the unfolded state, Figure 1B 1 shows a display panel DP in which at least a portion thereof is in a bent state. Figures 1A to 2 Embodiments of the inventive concept are described.

[0045] Reference Figure 1A and Figure 1B , the display panel DP may be provided with a front surface DP-FS, the front surface DP-FS being oriented parallel to the first direction DR1 and the second direction DR2. The front surface DP-FS may include a display area DP-DA and a peripheral area DP-NDA. The display area DP-DA may be an area of ​​the front surface DP-FS for displaying an image. The thickness of the display panel DP may be measured in a third direction DR3 perpendicular to the first direction DR1 and the second direction DR2.

[0046] The peripheral area DP-NDA may be adjacent to the display area DP-DA. In an embodiment, the peripheral area DP-NDA may be disposed along a boundary of the display area DP-DA to surround the display area DP-DA. In an embodiment, the peripheral area DP-NDA may include a portion disposed adjacent to the bending area, and when measured in the second direction DR2, the width of the bending area is smaller than the width of the display area DP-DA. Therefore, the portion of the peripheral area DP-NDA having a reduced width may reduce the bending area of ​​the display panel DP.

[0047] The display panel DP may include at least a curved portion. The display panel DP may be divided into a first area NBA (hereinafter, a non-curved area NBA) and a second area BA (hereinafter, a curved area BA). When measured in the second direction DR2, the curved area BA may be defined at a relatively narrow area of ​​the display panel DP.

[0048] When the bending area BA is in a bent state, the bending area BA may include a curvature area CA bent at a specific curvature and a facing area FA disposed to face the non-bending area NBA. The non-bending area NBA, the curvature area CA, and the facing area FA may be arranged in a first direction DR1. The bending area BA may be bent around a bending axis BX extending in a second direction DR2. For example, the curvature area CA of the bending area BA may be bent around the bending axis BX, and the facing area FA of the bending area BA may be disposed to face a portion of the non-bending area NBA in a third direction DR3.

[0049] Reference Figure 2, the display panel DP may include a plurality of pixels PX, a plurality of signal lines SGL, and a driving circuit GDC. The plurality of pixels PX and the plurality of signal lines SGL may be disposed on the front surface DP-FS.

[0050] The pixel PX may be arranged in the display area DP-DA. In an embodiment, the display area DP-DA is shown as having a quadrilateral or rectangular shape, but the inventive concept is not limited thereto. Each of the pixels PX may be configured to display light having a specific color. The pixels PX may be divided into a plurality of groups according to the color of the light to be emitted by the pixels PX. For example, the pixels PX may include red pixels, green pixels, and blue pixels. In some embodiments, the pixels PX may also include white pixels. Even when the pixels PX are included in different groups, the pixel driving circuits of the pixels PX may be configured to have the same structure.

[0051] The driving circuit GDC may be disposed in the peripheral area DP-NDA. The peripheral area DP-NDA may be adjacent to the display area DP-DA. In the embodiment, the peripheral area DP-NDA is shown to surround the display area DP-DA, but the inventive concept is not limited thereto.

[0052] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may be configured to generate a plurality of gate signals and sequentially output the gate signals to a plurality of gate lines GL described below. In some embodiments, the gate driving circuit may be configured to output other control signals different from the gate signals to the pixel PX.

[0053] The gate driving circuit may include a plurality of thin film transistors formed by the same process as that of the pixel driving circuit of the pixel PX (eg, by a low temperature polysilicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process).

[0054] The signal line SGL may include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. Each of the gate lines GL and each of the data lines DL may be connected to a corresponding pixel PX in the pixels PX. The power line PL may be connected to the pixel PX. The control signal line CSL may be configured to transmit a control signal to the scan drive circuit. The drive circuit GDC may include a scan drive circuit.

[0055] The signal lines SGL may be connected to signal pads (also referred to as pads) DP-PD, respectively. Some of the signal lines SGL (e.g., control signal lines CSL, data lines DL, and power lines PL) may extend from the non-bending area NBA to the bending area BA, and may be connected to corresponding signal pads DP-PD among the signal pads DP-PD. The signal pads DP-PD may be electrically connected to a circuit substrate that may be externally disposed. The signal pads DP-PD may be disposed in a facing area FA of the bending area BA.

[0056] In an embodiment, the display panel DP may further include a driving chip connected to the data line DL. Here, the driving chip may be directly mounted on the display panel DP, and the signal pad DP-PD connected to the data line DL among the signal pads DP-PD may be connected to the driving chip. The structure of the display panel DP may be variously changed, and the inventive concept is not limited to a specific structure of the display panel DP.

[0057] Figure 3A is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept. Figure 3B and Figure 3C Both show Figure 3A For ease of illustration, in Figure 3A A pixel PX is exemplarily shown in FIG. FIG. 3A to FIG. 3C The pixel PX is described in more detail. Figures 1A to 2 The described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0058] like Figure 3A As shown in , the pixel PX can be connected to the corresponding data line DL in the data line DL, the corresponding gate line GL in the gate line GL, and the power line PL. For example, the pixel PX may include an organic light emitting diode or a quantum dot light emitting diode. The light emitting layer of the organic light emitting diode may include an organic light emitting material. The light emitting layer of the quantum dot light emitting diode may include quantum dots and quantum rods. For simplicity, the following description will refer to an example in which the pixel PX includes an organic light emitting diode.

[0059] The pixel PX may include a first thin film transistor T1, a second thin film transistor T2, a capacitor Cst, and an organic light emitting diode OLED. The first thin film transistor T1, the second thin film transistor T2, and the capacitor Cst may constitute a pixel driving circuit for driving the organic light emitting diode OLED. In some embodiments, in addition to the first thin film transistor T1, the second thin film transistor T2, and the capacitor Cst, the pixel driving circuit may further include at least one thin film transistor or at least one capacitor, but the inventive concept is not limited thereto.

[0060] The first thin film transistor T1 may be connected to the organic light emitting diode OLED. The first thin film transistor T1 may be used to control a driving current flowing through the organic light emitting diode OLED according to the amount of charge stored in the capacitor Cst. The second thin film transistor T2 may be connected to the gate line GL and the data line DL. The second thin film transistor T2 may be configured to output a data signal from the data line DL to the capacitor Cst in response to a gate signal applied to the gate line GL. The amount of charge to be stored in the capacitor Cst may be determined by the difference between a voltage corresponding to the data signal output from the second thin film transistor T2 and a first power supply voltage ELVDD transmitted through the power line PL. In addition, the organic light emitting diode OLED may be connected to a second power supply voltage ELVSS.

[0061] The turn-on time of the first thin film transistor T1 may be determined according to the amount of charge stored in the capacitor Cst. The organic light emitting diode OLED may be configured to emit light when the first thin film transistor T1 is in the turn-on period. The color (i.e., wavelength) of the light emitted from the organic light emitting diode OLED may be determined by the material of the light emitting pattern. For example, the organic light emitting diode OLED may be configured to emit red, green, blue, or white light, but the inventive concept is not limited thereto.

[0062] Will refer to Figure 3B and Figure 3C Describe the cross-sectional structure of the pixel PX. Here, Figure 3B 1 shows a region of the pixel PX in which a first thin film transistor T1, a second thin film transistor T2, and an organic light emitting diode OLED are disposed. Figure 3C Another region of the pixel PX in which the first thin film transistor T1, the second thin film transistor T2, the organic light emitting diode OLED and the capacitor Cst are disposed is shown. That is, Figure 3B and Figure 3C Two different areas of the same pixel PX are shown respectively.

[0063] like Figure 3B and Figure 3C As shown in , the display panel DP may include a base layer BL, a circuit device layer DP-CL, a display device layer DP-OLED and an encapsulation layer TFE. The base layer BL, the circuit device layer DP-CL, the display device layer DP-OLED and the encapsulation layer TFE may be stacked in the third direction DR3.

[0064] The base layer BL may be a layer, a film or a plate on which the first thin film transistor T1, the second thin film transistor T2 and the capacitor Cst are formed. The base layer BL may include a plastic substrate, a glass substrate, a metal substrate or a composite substrate including an organic material and / or an inorganic material. The plastic substrate may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. The synthetic resin layer may be a polyimide resin layer, but the inventive concept is not limited to a specific material. For example, the synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin and a perylene resin.

[0065] The base layer BL may define the planar shape of the display panel DP. Figure 1A The shape of the display panel DP shown in FIG. 4 may correspond to the planar shape of the base layer BL. Therefore, the base layer BL may include a non-bending area NBA and a bending area BA including a curvature area CA and a facing area FA, and a portion of the base layer BL corresponding to the bending area BA may be bent around a bending axis BX.

[0066] The circuit device layer DP-CL may be disposed on the base layer BL. The circuit device layer DP-CL may include a pixel driving circuit and a plurality of insulating layers. For example, in addition to the first thin film transistor T1, the second thin film transistor T2, and the capacitor Cst, the circuit device layer DP-CL may be configured to include a barrier layer BRL, a buffer layer BFL, and a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, and a sixth insulating layer 60.

[0067] The barrier layer BRL may be provided to cover the top surface of the base layer BL. The barrier layer BRL may be configured to prevent contamination materials from penetrating into the circuit device layer DP-CL and the display device layer DP-OLED through the base layer BL. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked on the base layer BL.

[0068] The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL may be configured to allow the conductive pattern or the semiconductor pattern to be more closely bonded to the base layer BL. Therefore, compared with a pixel structure in which the conductive pattern and the semiconductor pattern are directly formed on the top surface of the base layer BL without the buffer layer BFL, the conductive pattern and the semiconductor pattern may be stably formed on the buffer layer BFL disposed in the display panel DP. The buffer layer BFL may be formed of at least one of an organic material and an inorganic material, or may include at least one of an organic material and an inorganic material. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked. In some embodiments, at least one of the buffer layer BFL and the barrier layer BRL may be omitted.

[0069] The first semiconductor pattern OSP1 may be disposed on the buffer layer BFL. The first semiconductor pattern OSP1 may be formed of, or may include, a crystalline semiconductor material. For example, the first semiconductor pattern OSP1 may be formed of, or may include, a polycrystalline semiconductor material (eg, polysilicon).

[0070] The first semiconductor pattern OSP1 may include an input region and an output region doped with impurities and a channel region disposed between the input region and the output region. Figure 3B and Figure 3C In the figure, for ease of illustration, the input area and the output area are shown in a shaded pattern.

[0071] The input region may be coupled to the first input electrode DE1, and the output region may be coupled to the first output electrode SE1. When viewed in a plan view, the channel region of the first semiconductor pattern OSP1 may be disposed between the input region and the output region, and may overlap with the first control electrode GE1. The first semiconductor pattern OSP1 may have p-type conductivity or n-type conductivity according to the type of impurities. Depending on the type of the first semiconductor pattern OSP1, electrons or holes may flow as majority carriers in the channel region.

[0072] The channel region of the first thin film transistor T1 may be formed of a polycrystalline semiconductor material or may include a polycrystalline semiconductor material. Therefore, the first thin film transistor T1 may be used as a driving device having high mobility and high reliability.

[0073] The first insulating layer 10 may be disposed on the first semiconductor pattern OSP1. The first insulating layer 10 may be formed of or may include at least one of an inorganic material and an organic material. For example, the first insulating layer 10 may be formed of or may include silicon nitride and / or silicon oxide.

[0074] The first insulating layer 10 may be disposed on the buffer layer BFL to cover at least a portion of the first semiconductor pattern OSP1. However, the inventive concept is not limited thereto, and in some embodiments, the first insulating layer 10 may be disposed in an insulating pattern overlapping at least the channel region of the first semiconductor pattern OSP1. The shape of the first insulating layer 10 may be variously changed, and the inventive concept is not limited to a specific shape of the first insulating layer 10.

[0075] The first control electrode GE1 and the first capacitor electrode E1 of the capacitor Cst may be disposed on the first insulating layer 10. In an embodiment, the first control electrode GE1 may be disposed on the same layer as the first capacitor electrode E1.

[0076] The first control electrode GE1 may overlap at least the channel region of the first semiconductor pattern OSP1. The first control electrode GE1 may be spaced apart from the first semiconductor pattern OSP1, and the first insulating layer 10 is interposed therebetween. In an embodiment, the first insulating layer 10 may serve as a gate insulating layer of the first thin film transistor T1.

[0077] The first capacitor electrode E1 may be used as one of the two electrodes of the capacitor Cst. In an embodiment, the first capacitor electrode E1 and the first control electrode GE1 may correspond to two portions of a single conductive pattern. In some embodiments, the first control electrode GE1 and the first capacitor electrode E1 may correspond to two separate patterns, respectively, which are electrically connected to each other through an additional bridge electrode (not shown), or electrically disconnected from each other and applied with different voltages.

[0078] The second insulating layer 20 may be disposed on the first control electrode GE1 and the first capacitor electrode E1. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the first control electrode GE1 and the first capacitor electrode E1.

[0079] The second insulating layer 20 may be formed of at least one of an inorganic material and an organic material, or may include at least one of an inorganic material and an organic material. The second insulating layer 20 may include a material different from that of the first insulating layer 10. For example, the second insulating layer 20 may include a metal oxide material (e.g., aluminum oxide), and the first insulating layer 10 may include silicon nitride and / or silicon oxide. However, the inventive concept is not limited thereto, and in some embodiments, the second insulating layer 20 may be formed of the same material as that of the first insulating layer 10, or may include the same material as that of the first insulating layer 10. The second insulating layer 20 may be used to protect the first insulating layer 10 in a subsequent process (e.g., for forming the second control electrode GE2), and thus to prevent the first semiconductor pattern OSP1 disposed under the first insulating layer 10 from being damaged.

[0080] The second control electrode GE2 of the second thin film transistor T2, the upper electrode UE, and the second capacitor electrode E2 of the capacitor Cst may be disposed on the second insulating layer 20. When viewed in a plan view, the second control electrode GE2 may not overlap the first control electrode GE1. In an embodiment, the second control electrode GE2 may be disposed on a layer different from a layer disposed under the first control electrode GE1.

[0081] When viewed in a plan view, the upper electrode UE may overlap with the first control electrode GE1. In the case where different voltages are applied to the upper electrode UE and the first control electrode GE1, the upper electrode UE and the first control electrode GE1 may be used as electrodes of a capacitor. In some embodiments, in the case where the same voltage is applied to the upper electrode UE and the first control electrode GE1, the upper electrode UE together with the first control electrode GE1 may be used as a gate electrode for controlling the switching (i.e., on / off) operation of the first thin film transistor T1 or the potential of the channel region of the first semiconductor pattern OSP1.

[0082] When viewed in a plan view, the second capacitor electrode E2 may overlap the first capacitor electrode E1. The second capacitor electrode E2 may be spaced apart from the first capacitor electrode E1 with the second insulating layer 20 interposed therebetween, thereby forming a capacitor Cst.

[0083] In an embodiment, the upper electrode UE, the second capacitor electrode E2, and the second control electrode GE2 may be disposed on the same layer. For example, the upper electrode UE, the second capacitor electrode E2, and the second control electrode GE2 may be formed simultaneously by a single patterning process using the same mask. Therefore, the upper electrode UE, the second capacitor electrode E2, and the second control electrode GE2 may be formed of or include the same material and may have substantially the same stacked structure. In some embodiments, the upper electrode UE may be omitted.

[0084] The third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed to cover the top surface of the second insulating layer 20, the top surface of the upper electrode UE, the top surface of the second control electrode GE2, and the top surface of the second capacitor electrode E2. The third insulating layer 30 may serve as a gate insulating layer of the second thin film transistor T2.

[0085] The third insulating layer 30 may be an inorganic layer and / or an organic layer, and may have a single layer structure or a multilayer structure. For example, the third insulating layer 30 may be an inorganic layer formed of or including at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. For example, the third insulating layer 30 may be a single silicon oxide layer.

[0086] The second semiconductor pattern OSP2 of the second thin film transistor T2 may be disposed on the third insulating layer 30. The second semiconductor pattern OSP2 may be formed of at least one of the oxide semiconductors, or may include at least one of the oxide semiconductors. For example, the oxide semiconductor may include a metal oxide whose metal element is at least one of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) or may include a mixture of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and their oxides. In some embodiments, the second semiconductor pattern OSP2 may include a crystalline oxide semiconductor. The crystalline oxide semiconductor may be provided to have a vertical directionality.

[0087] The second semiconductor pattern OSP2 may include an input region and an output region doped with impurities and a channel region disposed between the input region and the output region. Figure 3B and Figure 3C , for ease of illustration, the input region and the output region of the second semiconductor pattern OSP2 are shown in a shaded pattern. The input region may be coupled to the second input electrode DE2, and the output region may be coupled to the second output electrode SE2. When viewed in a plan view, the channel region of the second semiconductor pattern OSP2 may be disposed between the input region and the output region, and may overlap with the second control electrode GE2. Depending on the type of impurities, the second semiconductor pattern OSP2 may have p-type conductivity or n-type conductivity. Depending on the type of the second semiconductor pattern OSP2, electrons or holes may flow as majority carriers in the channel region.

[0088] The reduced metal material may be used as an impurity in the second semiconductor pattern OSP2. For example, the input region and the output region may contain a metal material reduced from a metal oxide material constituting a channel region, thereby reducing a leakage current of the second thin film transistor T2, and thus, the second thin film transistor T2 may be used as a switching device with improved on-off properties.

[0089] The first input electrode DE1 and the first output electrode SE1 of the first thin film transistor T1 and the second input electrode DE2 and the second output electrode SE2 of the second thin film transistor T2 may be disposed on the third insulating layer 30. In an embodiment, the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2 may be simultaneously formed by a single patterning process using the same mask. Therefore, the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2 may be formed of or include the same material and may have the same stacked structure. For example, the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2 may be formed of molybdenum or may include molybdenum.

[0090] The first contact hole CH1 and the second contact hole CH2 may be formed to expose a portion of the input region and the output region of the first semiconductor pattern OSP1, respectively, and the first input electrode DE1 and the first output electrode SE1 may be coupled to the first semiconductor pattern OSP1 through the first contact hole CH1 and the second contact hole CH2, respectively. The first contact hole CH1 and the second contact hole CH2 may be formed to penetrate the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0091] The second input electrode DE2 and the second output electrode SE2 may be directly coupled to the second semiconductor pattern OSP2. The second input electrode DE2 and the second output electrode SE2 may be coupled to two opposite ends of the second semiconductor pattern OSP2, respectively. At least a portion of the second input electrode DE2 may be directly disposed in the input region of the second semiconductor pattern OSP2, and at least a portion of the second output electrode SE2 may be directly disposed in the output region of the second semiconductor pattern OSP2. In the second thin film transistor T2, each of the second input electrode DE2 and the second output electrode SE2 may be coupled to the second semiconductor pattern OSP2 without any portion being disposed in the contact hole.

[0092] The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2. The fourth insulating layer 40 may be an organic layer or an inorganic layer and may have a single layer structure or a multilayer structure.

[0093] In an embodiment, the fourth insulating layer 40 may be an inorganic layer formed of or including at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. For example, the fourth insulating layer 40 may be a silicon oxide layer. The fourth insulating layer 40 may be referred to as a "passivation layer".

[0094] In an embodiment, the fourth insulating layer 40 may be formed by a heat treatment process. For example, the heat treatment process may be performed at a high temperature of 300° C. or higher, and as a result, a defective fourth insulating layer 40 may be repaired. A detailed description thereof will be omitted.

[0095] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. For example, the fifth insulating layer 50 may be formed of a polymer resin such as polyimide, or may include a polymer resin such as polyimide.

[0096] The connection electrode CNE may be disposed on the fifth insulating layer 50. The connection electrode CNE may be connected to the first output electrode SE1 of the first thin film transistor T1 through a third contact hole CH3 formed to penetrate the fourth insulating layer 40 and the fifth insulating layer 50.

[0097] The connection electrode CNE may be formed of a material different from that of the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2, or may include a material different from that of the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2. For example, the connection electrode CNE may be formed of a material having a lower resistance than that of the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2, or may include a material having a lower resistance than that of the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2. In this case, the contact resistance between the organic light emitting diode OLED and the first thin film transistor T1 may be reduced, thereby improving the electrical characteristics of the display device.

[0098] However, the inventive concept is not limited to the above examples, and in some embodiments, the connection electrode CNE may be formed of the same material as the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2, or may include the same material as the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2. In some embodiments, the connection electrode CNE may be omitted, and the organic light emitting diode OLED and the first thin film transistor T1 may be directly coupled to each other. The structure of the display panel DP may be variously changed, and the inventive concept is not limited to a specific structure of the display panel DP.

[0099] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover the connection electrode CNE. The sixth insulating layer 60 may be an organic layer, and may have a single-layer structure or a multi-layer structure.

[0100] In an embodiment, the fifth insulating layer 50 and the sixth insulating layer 60 may be a polyimide resin layer having a single-layer structure. However, the inventive concept is not limited thereto, and in some embodiments, the fifth insulating layer 50 and the sixth insulating layer 60 may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin.

[0101] The organic light emitting diode OLED may be disposed on the sixth insulating layer 60. The first electrode AE ​​of the organic light emitting diode OLED may be disposed on the sixth insulating layer 60. The first electrode AE ​​may be connected to the connection electrode CNE through a fourth contact hole CH4 formed to penetrate the sixth insulating layer 60.

[0102] The pixel defining layer PDL may be disposed on the sixth insulating layer 60. The pixel defining layer PDL may have an opening OP formed to expose at least a portion of the first electrode AE. The opening OP of the pixel defining layer PDL may define a light emitting region PXA of each pixel PX. For example, a plurality of pixels PX may be regularly arranged on the display panel DP (eg, see Figure 1A ). The area in which the pixels PX are disposed may be defined as a "pixel area", and each pixel area may include a light-emitting area PXA and a non-light-emitting area NPXA adjacent to the light-emitting area PXA. The non-light-emitting area NPXA may surround the light-emitting area PXA.

[0103] The hole control layer HCL may be commonly disposed in the light emitting region PXA and the non-light emitting region NPXA. A common layer such as the hole control layer HCL refers to a layer commonly disposed in a plurality of pixels PX. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0104] The light emitting pattern EML may be disposed on the hole control layer HCL. The light emitting pattern EML may be locally disposed in a region corresponding to the opening OP. The light emitting pattern EML may be divided into a plurality of separate patterns respectively formed in the pixels PX.

[0105] In the embodiment, the light emitting pattern EML is shown as having a patterned structure, but in some embodiments, the light emitting pattern EML may be configured to have a continuous structure running through a plurality of pixels PX. Here, the light emitting pattern EML may be configured to generate white light. In addition, the light emitting pattern EML may be configured to have a multilayer structure.

[0106] The electron control layer ECL may be disposed on the light emitting pattern EML. The electron control layer ECL may include an electron transport layer and an electron injection layer. The second electrode CE may be disposed on the electron control layer ECL. The electron control layer ECL and the second electrode CE may be commonly disposed in a plurality of pixels PX.

[0107] The encapsulation layer TFE may be disposed on the second electrode CE. The encapsulation layer TFE may be disposed to cover a plurality of pixels PX in common. In an embodiment, the encapsulation layer TFE may be disposed to directly cover the second electrode CE. In some embodiments, the capping layer may be disposed to cover the second electrode CE. The capping layer may be an organic layer. In an embodiment, an inorganic layer formed by a sputtering method may be additionally formed on the capping layer. In an embodiment, the stacked structure of the organic light emitting diode OLED may have a structure in which the plurality of pixels PX are commonly covered. Figure 3B The shape obtained by inverting the stacked structure of the organic light emitting diode OLED shown in FIG.

[0108] The encapsulation layer TFE may include at least one of an inorganic encapsulation layer and an organic encapsulation layer. In an embodiment, the encapsulation layer TFE may include two inorganic encapsulation layers and an organic encapsulation layer located between the two inorganic encapsulation layers. In an embodiment, the encapsulation layer TFE may include a plurality of inorganic encapsulation layers and a plurality of organic encapsulation layers stacked alternately.

[0109] The inorganic encapsulation layer may protect the organic light emitting diode OLED from moisture or oxygen, and the organic encapsulation layer may be provided to protect the organic light emitting diode OLED from foreign matter (e.g., dust particles) and provide a flat top surface. The inorganic encapsulation layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but the inventive concept is not limited thereto. The organic encapsulation layer may include an acrylic organic layer, but the inventive concept is not limited thereto.

[0110] FIG. 4A to FIG. 4C are cross-sectional views each illustrating a curved area of ​​a display panel according to an embodiment of the inventive concept. FIG. 4A to FIG. 4C Each of the Figure 2 A cross section of the curvature area CA taken parallel to the first direction DR1 and the third direction DR3. Figure 4A and Figure 4C shows a region on which a signal line SL or SL-PT is provided, Figure 4B Another area on which no signal line is arranged is shown. Figure 4A FIG. 4 shows a signal line SL extending in a first direction DR1. Figure 4C FIG. 4 shows a signal line SL-PT including a plurality of patterns spaced apart from each other in a first direction DR1. FIG. 4A to FIG. 4C The embodiments of the inventive concept are described in more detail. Figures 1A to 3CThe described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0111] like FIG. 4A to FIG. 4C As shown in FIG. , the bending area BA may have a shape similar to that of the first area NBA (see, for example, Figure 1A ) The barrier layer BRL, the buffer layer BFL, and the first to sixth insulating layers 10 to 60 may be sequentially disposed on the top surface of the base layer BL.

[0112] The barrier layer BRL and / or the buffer layer BFL may be disposed to define a groove GV-1 (hereinafter, a first groove GV-1) overlapping the bending area BA. The first groove GV-1 may be defined within the curvature area CA. The first groove GV-1 may extend along the curvature area CA or in a second direction (not shown). The width of the base layer BL exposed by the first groove GV-1 and measured in the first direction DR1 may be smaller than the width of the curvature area CA in the first direction DR1.

[0113] The first to fourth insulating layers 10 to 40 may be disposed to define a groove GV-2 (hereinafter, a second groove GV-2) overlapping the bending area BA. The second groove GV-2 may be defined within the curvature area CA. The first to fourth insulating layers 10 to 40 may be disposed to partially expose the top surface of the inorganic layer including the barrier layer BRL and the buffer layer BFL.

[0114] When viewed in a cross-sectional view, the side surfaces of the barrier layer BRL and the buffer layer BFL defining the first groove GV-1 may be inclined at a certain angle relative to the top surface of the base layer BL. When viewed in a cross-sectional view, the side surfaces of the first to fourth insulating layers 10 to 40 defining the second groove GV-2 may also be inclined at a certain angle relative to the top surface of the base layer BL. The inclination angle of the first groove GV-1 and the inclination angle of the second groove GV-2 may be the same or different.

[0115] The fifth insulating layer 50 may be provided to cover the first area NBA (eg, see Figure 1A ), and may extend from the non-bending area NBA to cover the bending area BA. Here, in the bending area BA, the fifth insulating layer 50 may be disposed to fill the first groove GV-1 and the second groove GV-2. The fifth insulating layer 50 may be in contact with the top surface of the base layer BL exposed by the first groove GV-1, the inclined surface of the first groove GV-1, and the inclined surface of the second groove GV-2. The fifth insulating layer 50 may be in contact with a portion of the top surface of the buffer layer BFL that is not covered by the first insulating layer 10 to the fourth insulating layer 40.

[0116] In an embodiment, the number of stacked insulating layers in the curvature region CA can be reduced by providing the first groove GV-1 and the second groove GV-2 in the curvature region CA. The more insulating layers provided in the curvature region CA, the more likely defects such as delamination or bending due to bending stress may occur. According to an embodiment of the inventive concept, since the number of stacked insulating layers provided in the curvature region CA is reduced, the curvature region CA can be easily bent without causing defects.

[0117] In an embodiment, the first groove GV-1 and the second groove GV-2 may remove the barrier layer BRL, the buffer layer BFL, and the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 in the curvature area CA. As described above, the barrier layer BRL, the buffer layer BFL, and the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may include an inorganic material. According to an embodiment of the inventive concept, by removing the inorganic layer from the curvature area CA, it may be possible to prevent or inhibit the inorganic layer from being damaged due to bending stress.

[0118] In an embodiment, since the first groove GV-1 and the second groove GV-2 are filled with an organic layer (e.g., the fifth insulating layer 50), it is possible not only to prevent cracks from spreading through the inorganic layer, but also to improve the flexibility of the curvature area CA. Since the fifth insulating layer 50 disposed in the non-bending area NBA is used to fill the first groove GV-1 and the second groove GV-2, it is possible to simplify the manufacturing process and the device structure of the display panel DP.

[0119] like Figure 4A As shown in FIG. 5 , at least a portion of the signal line SL may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be disposed to cover and protect the signal line SL. The signal line SL may be connected to the signal pad DP-PD (eg, see Figure 2 ) corresponds to at least one of the signal lines SGL of the signal pad DP-PD. For example, the signal line SL may be a data line or a power line. In some embodiments, the signal line SL may be disposed on a layer different from a layer under the signal line SGL and the signal pad DP-PD, and may be used as a bridge line that connects the signal line SGL and the signal pad DP-PD to each other.

[0120] Although not in Figure 4A , but another portion of the signal line SL (for example, disposed in the display area DP-DA) may be disposed on a different layer. For example, the signal line SL may include another portion disposed on the third insulating layer 30. The two different portions of the signal line SL may be connected to each other through a contact hole formed to penetrate the fourth insulating layer 40 and the fifth insulating layer 50. The contact hole may be formed in the peripheral area DP-NDA of the non-bending area NBA.

[0121] In an embodiment, at least one layer disposed in the display area DP-DA may be extended to cover at least a portion of the top surface of the sixth insulating layer 60. In some embodiments, the sixth insulating layer 60 may not be disposed in the curvature area CA.

[0122] like Figure 4B As shown in , the curvature region CA may include a region where the signal line SL is not disposed. In such a region without the signal line SL, the sixth insulating layer 60 may contact the fifth insulating layer 50 or may cover the top surface of the fifth insulating layer 50 .

[0123] like Figure 4C As shown in , the signal line SL-PT may be a patterned signal line including a plurality of patterns. The patterns of the patterned signal line SL-PT may be spaced apart from each other in the first direction DR1. When viewed in a plan view, the pattern of the patterned signal line SL-PT may be spaced apart from each other in the first direction DR2. Figure 4C In other regions not shown in the figure, the second direction DR2 (for example, see Figure 1A The patterned signal lines SL-PT may be connected to each other in a pattern extending perpendicular to the bending axis BX (for example, see Figure 1B ) has a reduced area, thereby reducing bending stress to be applied to the patterned signal line SL-PT.

[0124] Figure 5 is a cross-sectional view illustrating a region of a display panel according to an embodiment of the inventive concept. Figure 5 Both a portion of the non-bending area NBA and a portion of the bending area BA are shown. Figure 5 In the embodiment, the portion of the non-bending area NBA may include Figure 3B The light emitting area PXA shown in FIG. 1 corresponds to the light emitting area PXA, and the portion of the bending area BA may include Figure 4C For the sake of simplicity, the previous reference Figures 1A to 4C The described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0125] like Figure 5 As shown in , the display panel DP may further include a third groove GV-3 formed in the bending area BA. The second groove GV-2 may be defined in the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30, and the third groove GV-3 may be defined in the fourth insulating layer 40. A portion of the fourth insulating layer 40 overlapping the second groove GV-2 may be removed to form the third groove GV-3.

[0126] The width of the third groove GV-3 in the first direction DR1 may be greater than the width of the second groove GV-2 in the first direction DR1. In addition, the width of the second groove GV-2 in the first direction DR1 may be greater than the width of the first groove GV-1 in the first direction DR1. The first groove GV-1, the second groove GV-2, and the third groove GV-3 may be sequentially formed in the third direction DR3 to form a step structure.

[0127] The fifth insulating layer 50 may be provided to fill the first groove GV-1, the second groove GV-2, and the third groove GV-3 or cover the inner surface of each of the first groove GV-1, the second groove GV-2, and the third groove GV-3. In an embodiment, by forming the first groove GV-1, the second groove GV-2, and the third groove GV-3 and filling them with an organic layer, the display panel DP may be designed to have only an organic layer (e.g., the fifth insulating layer 50) in at least a central portion of the curvature area CA.

[0128] like Figure 5 As shown in , the connection electrode CNE may be used as a signal line passing through the curvature area CA. In the non-bending area NBA, the connection electrode CNE may be configured to connect the first output electrode SE1 of the first thin film transistor T1 to the first electrode AE ​​of the organic light emitting diode OLED.

[0129] The connection electrode CNE may be disposed between the fifth insulating layer 50 and the sixth insulating layer 60 and may be disposed to pass through the non-bending area NBA and the bending area BA. The connection electrode CNE may be used as a bridge pattern that connects a conductive pattern disposed in the non-bending area NBA to a conductive pattern disposed in a facing area (not shown). In an embodiment, the connection electrode CNE may include a plurality of patterns disposed in the curvature area CA and spaced apart from each other in the first direction DR1. In this case, the connection electrode CNE may prevent cracks or disconnections from occurring due to bending stress.

[0130] In some embodiments, the pixel defining layer PDL-H may be provided with a concave portion RS formed around or near an opening area defining the light emitting area PXA. For example, a mask and a spacer supporting the mask may be used in a deposition process for forming the light emitting pattern EML, and the formation of the concave portion RS may be caused by the use of the mask or the spacer. The display panel DP having the concave portion RS may prevent the light emitting pattern EML or the light emitting area PXA from being damaged by the mask. The concave portion RS may be formed by a process in which a halftone mask is used. According to an embodiment of the inventive concept, the pixel defining layer PDL-H is used to form the light emitting pattern EML without an additional process, thereby reducing process costs and simplifying the manufacturing process.

[0131] In an embodiment, at least one or each of the fifth insulating layer 50, the sixth insulating layer 60, and the pixel defining layer PDL-H may include an organic material. The stacked structure overlapping the curvature area CA may be designed to include only organic materials, thereby improving the flexibility of the display panel DP at the curvature area CA and achieving high reliability of the display panel DP even when the folding / unfolding operation is repeated.

[0132] Figure 6 1 is a cross-sectional view showing a region of a display panel according to an embodiment of the inventive concept. For ease of description, Figure 6 The corresponding Figure 3B For the sake of simplicity, the previous reference Figures 1A to 5 The described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0133] like Figure 6 As shown in , the display panel DP may further include a light blocking pattern LSP disposed between the fifth insulating layer 50 and the sixth insulating layer 60 and overlapping the second semiconductor pattern OSP2.

[0134] The light blocking pattern LSP may be formed of or may include a material having high absorptivity or high reflectivity. The light blocking pattern LSP may be disposed above the second semiconductor pattern OSP2 to prevent a portion (e.g., a reflection portion) of light generated in the organic light emitting diode OLED from being incident into the second semiconductor pattern OSP2.

[0135] The light blocking pattern LSP may be formed of the same material as that of the connection electrode CNE, or may include the same material as that of the connection electrode CNE. For example, the light blocking pattern LSP may be formed of a metal material, or may include a metal material. The light blocking pattern LSP may have the same stacking structure as that of the connection electrode CNE. The light blocking pattern LSP and the connection electrode CNE may be simultaneously formed by a single patterning process using the same mask, thereby simplifying the manufacturing process and reducing the process cost.

[0136] FIG. 7A to FIG. 7Q is a cross-sectional view showing a process of manufacturing a display panel according to an embodiment of the inventive concept. For comparison, FIG. 7A to FIG. 7Q Each of the Figure 3B and Figure 4A For the sake of simplicity, the previous reference Figures 1A to 6 The described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0137] like Fig. 7AAs shown in , at least one inorganic layer may be formed on the base layer BL. The at least one inorganic layer may overlap both the non-bending area NBA and the bending area BA. Although not shown, during the manufacturing process, the base layer BL may be placed on the working substrate. The working substrate may be removed after manufacturing the display panel.

[0138] The at least one inorganic layer may be formed by depositing, coating or printing an inorganic material on the base layer BL. Fig. 7A As shown in , the at least one inorganic layer may include a barrier layer BRL and a buffer layer BFL. Forming the barrier layer BRL may include sequentially forming a silicon oxide layer and a silicon nitride layer on the base layer BL. Forming the buffer layer BFL may include sequentially forming a silicon oxide layer and a silicon nitride layer on the barrier layer BRL.

[0139] like Fig. 7A As shown in , a first preliminary semiconductor pattern OSP1-P may be formed on the buffer layer BFL. The first preliminary semiconductor pattern OSP1-P may be formed of a silicon semiconductor material, or may include a silicon semiconductor material. Forming the first preliminary semiconductor pattern OSP1-P may include forming a semiconductor layer and then patterning the semiconductor layer. In an embodiment, the semiconductor layer may be crystallized before or after patterning the semiconductor layer.

[0140] Afterwards, if Figure 7B As shown in FIG. 1 , a first insulating layer 10 may be formed in the non-bending area NBA and the bending area BA to cover the buffer layer BFL and the first preliminary semiconductor pattern OSP1-P. The first insulating layer 10 may be formed by a deposition process, a coating process, or a printing process. At least one or each of the other insulating layers to be formed on the first insulating layer 10 may be formed using one of a deposition process, a coating process, and a printing process.

[0141] The first control electrode GE1 may be formed on the first insulating layer 10. Forming the first control electrode GE1 may include forming a conductive layer on the first insulating layer 10 and then patterning the conductive layer. The first capacitor electrode E1 of the capacitor Cst may be formed using the same process as that for the first control electrode GE1 (eg, see Figure 3C ).

[0142] Next, a doping process may be performed on the first preliminary semiconductor pattern OSP1-P using the first control electrode GE1 as a mask. In the doping process, as indicated by arrows, impurities may be injected into the first preliminary semiconductor pattern OSP1-P through the first insulating layer 10. Here, impurities may not be injected into the channel region of the first preliminary semiconductor pattern OSP1-P overlapping the first control electrode GE1, but may be injected into two side regions (i.e., an input region and an output region) of the first preliminary semiconductor pattern OSP1-P that are spaced apart from each other and between which the channel region is placed. In an embodiment, the input region and the output region of the first preliminary semiconductor pattern OSP1-P may be doped with an n-type dopant (e.g., a group V element). The first semiconductor pattern OSP1 may be formed by doping the first preliminary semiconductor pattern OSP1-P. However, the inventive concept is not limited to the above example, and in some embodiments, the first semiconductor pattern OSP1 may be formed by doping the first preliminary semiconductor pattern OSP1-P with a p-type dopant (e.g., a group III element).

[0143] Afterwards, if Figure 7C As shown in , a second insulating layer 20 may be formed in both the non-bending area NBA and the bending area BA to cover the first insulating layer 10 and the first control electrode GE1. A second control electrode GE2 that does not overlap the first control electrode GE1 may be formed on the second insulating layer 20. For example, when viewed in a plan view, the second control electrode GE2 may be spaced apart from the first control electrode GE1. The second control electrode GE2 and the upper electrode UE may be formed using the same process. Although not shown, the second capacitor electrode E2 of the capacitor Cst may be formed by the same process as that used for the second control electrode GE2 and the upper electrode UE (for example, see Figure 3C ).

[0144] Afterwards, if Fig.7D As shown in FIG. 1 , a third insulating layer 30 may be formed in the non-bending area NBA and the bending area BA to cover the second insulating layer 20 , the second control electrode GE2 , and the upper electrode UE.

[0145] Next, if Fig. 7EAs shown in , a first etching step may be performed to partially remove the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. For example, a first contact hole CH1 and a second contact hole CH2 may be formed to expose at least a portion of an input region and an output region of the first semiconductor pattern OSP1, respectively. In an embodiment, a first etching step may be performed to partially remove the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 in the bending area BA to form a first upper groove GV-21. In an embodiment, the first etching step may use a single mask to form the first contact holes CH1 and the second contact holes CH2 in the non-bending area NBA and the first upper groove GV-21 in the bending area BA, thereby reducing the number of masks required to manufacture the display panel DP.

[0146] Afterwards, if Figure 7F As shown in , a second preliminary semiconductor pattern OSP2-P may be formed on the third insulating layer 30. The second preliminary semiconductor pattern OSP2-P may be formed of a metal oxide semiconductor material, or may include a metal oxide semiconductor material. Forming the second preliminary semiconductor pattern OSP2-P may include forming a metal oxide semiconductor layer and performing a patterning process on the metal oxide semiconductor layer. In an embodiment, the second preliminary semiconductor pattern OSP2-P may be formed to have a conductive property.

[0147] In some embodiments, the references may be performed in a different order. Fig. 7E and Figure 7F For example, a first etching step for forming the first and second contact holes CH1 and CH2 and the first upper groove GV-21 may be performed after forming the second preliminary semiconductor pattern OSP2-P.

[0148] Next, if Figure 7G As shown in FIG, an electrode forming step may be performed to form electrodes DE1, SE1, SE2, and DE2 on the third insulating layer 30. Forming the electrodes DE1, SE1, SE2, and DE2 may include forming a conductive layer using a deposition process and performing a patterning process on the conductive layer.

[0149] The patterning of the conductive layer may be performed by a plasma process using an etching gas. In an embodiment, the etching gas may include an oxygen-containing material, in which case the oxygen plasma generated from the etching gas may be used for the plasma process. The etching gas may be used to reduce the concentration of hydrogen in the region of the second preliminary semiconductor pattern OSP2-P that is not shielded by the second input electrode DE2 and the second output electrode SE2. Therefore, the non-shielded region of the second preliminary semiconductor pattern OSP2-P located between the second input electrode DE2 and the second output electrode SE2 may have a higher resistance than the resistance of the shielded region of the second preliminary semiconductor pattern OSP2-P located under the second input electrode DE2 and the second output electrode SE2. For example, the non-shielded region of the second preliminary semiconductor pattern OSP2-P may be changed to have a semiconductor-like band structure, thereby serving as a channel region. That is, by processing the second preliminary semiconductor pattern OSP2-P having a conductive property with an etching gas, a second semiconductor pattern OSP2 having at least a portion of a semiconductor-like band structure may be formed. The second semiconductor pattern OSP2 may include a channel region having a semiconductor-like band structure and an input region and an output region spaced apart from each other and having the channel region disposed therebetween.

[0150] Afterwards, if Figure 7H As shown in FIG, a preliminary fourth insulating layer 40-I may be formed in both the non-bending area NBA and the bending area BA to cover the third insulating layer 30 and the electrodes DE1, SE1, SE2, and DE2. The preliminary fourth insulating layer 40-I may include a portion filling at least a portion of the first upper groove GV-21.

[0151] Next, if Fig.7I As shown in , the second etching step may be performed to partially remove the preliminary fourth insulating layer 40-I. The second etching step may be performed to form a contact hole CH3-40 penetrating the preliminary fourth insulating layer 40-I and exposing at least a portion of the first output electrode SE1.

[0152] In an embodiment, the second etching step may partially remove the preliminary fourth insulating layer 40-I in the bending area BA, thereby forming a second upper groove GV-22. Here, the first upper groove GV-21 and the second upper groove GV-22 may be defined as a second groove GV-2. In an embodiment, the second etching step may use a single mask to form the contact hole CH3-40 in the non-bending area NBA and the second upper groove GV-22 in the bending area BA, thereby reducing the number of masks required to manufacture the display panel DP.

[0153] like Fig.7I As shown in , the second upper groove GV-22 and the first upper groove GV-21 may be formed to have inner side surfaces aligned with each other, but the inventive concept is not limited thereto. Figure 5 As shown in FIG. 4 , a third groove GV- 3 may be formed in the preliminary fourth insulating layer 40 -I to expose at least a portion of the top surface of the third insulating layer 30 .

[0154] like Figure 7J As shown in , a third etching step may be performed to partially remove the inorganic layers BRL and BFL in the bending area BA. For example, in the third etching step, an etching gas may be used to partially remove the barrier layer BRL and the buffer layer BFL in the bending area BA, thereby forming a first groove GV-1 in the bending area BA. The top surface of the inorganic layer including the barrier layer BRL and the buffer layer BFL may be partially exposed according to the etching time or the etchant. In some embodiments, the first groove GV-1 may be formed to have an inner side surface aligned with the inner side surface of the first upper groove GV-21.

[0155] In an embodiment, the third etching step for forming the first groove GV-1 and the second etching step for forming the second upper groove GV-22 may be performed in a continuous manner. The third etching step and the second etching step may constitute a single process performed using the same mask, but may differ from each other in terms of exposure time to the etching gas or the material of the etching gas. Therefore, the number of masks used in the etching process may be reduced, thereby simplifying the manufacturing process and reducing the manufacturing cost.

[0156] like Figure 7K and Figure 7L As shown in , after the third etching step, the fourth insulating layer 40 may be formed by performing a heat treatment HT on the preliminary fourth insulating layer 40-I. The heat treatment HT may be performed to thermally repair the channel region of the second semiconductor pattern OSP2 covered by the preliminary fourth insulating layer 40-I. When a conductive layer to be used as the second input electrode DE2 and the second output electrode SE2 is deposited, for example, by a physical deposition process, stress may be applied to the channel region of the second semiconductor pattern OSP2. In an embodiment, the heat treatment HT may stably repair defects that may have been formed in the channel region of the second semiconductor pattern OSP2. In addition, the heat treatment HT may be performed to prevent hydrogen atoms in the preliminary fourth insulating layer 40-I from flowing into the channel region of the second semiconductor pattern OSP2.

[0157] In an embodiment, the heat treatment HT may be performed at a high temperature of about 300° C. or higher. The heat treatment HT may include gradually performing an annealing process within a specific process time. According to an embodiment of the inventive concept, the method of manufacturing the display panel DP may further include a heat treatment HT to be performed after forming the preliminary fourth insulating layer 40 -I to improve the reliability of the second semiconductor pattern OSP2 and stabilize the electrical characteristics of the second thin film transistor T2.

[0158] Next, if Figure 7M As shown in , a fifth insulating layer 50 may be formed on the fourth insulating layer 40. The fifth insulating layer 50 may be formed to overlap the non-bending area NBA and the bending area BA. The fifth insulating layer 50 may include portions disposed in the first groove GV-1 and the second groove GV-2. The fifth insulating layer 50 may be formed to partially fill the contact hole CH3-40.

[0159] In an embodiment, the fifth insulating layer 50 may be formed after the heat treatment step of the preliminary fourth insulating layer 40-I. In the case where the fifth insulating layer 50 is formed of a polymer resin such as polyimide, the fifth insulating layer 50 may be damaged during the heat treatment HT. According to an embodiment of the inventive concept, the step of forming a layer including an organic material (e.g., the fifth insulating layer 50) may be postponed until the heat treatment HT of the preliminary fourth insulating layer 40-I is completed to prevent the fifth insulating layer 50 from being damaged by the heat treatment HT, thereby improving the reliability of the manufacturing process.

[0160] like Figure 7N As shown in , a fourth etching step may be performed to remove a portion of the fifth insulating layer 50. For example, a contact hole CH3-50 may be formed in the fifth insulating layer 50 to expose at least a portion of the first output electrode SE1 covered by the fifth insulating layer 50. The contact hole CH3-50 of the fifth insulating layer 50 may be aligned with the contact hole CH3-40 of the fourth insulating layer 40. The contact holes CH3-40 and CH3-50 may be connected to each other to form a single contact hole defined as a third contact hole CH3.

[0161] like Fig.7O As shown in , the connection electrode CNE may be formed on the fifth insulating layer 50. The process of forming the connection electrode CNE may also be used to form a portion of the signal line SL overlapping the bending area BA. As described above, the connection electrode CNE and the signal line SL may be two parts of a single object, or may be two separate objects spaced apart from each other, but the inventive concept is not limited thereto.

[0162] like Figure 7P As shown in FIG, a sixth insulating layer 60 may be formed on the fifth insulating layer 50 to cover not only the connection electrode CNE but also a portion of the signal line SL overlapping the bending area BA. A fourth contact hole CH4 may be formed in the sixth insulating layer 60 to expose at least a portion of the top surface of the connection electrode CNE.

[0163] like Figure 7QAs shown in FIG. 1 , an organic light emitting diode OLED may be formed on the sixth insulating layer 60 in the non-bending area NBA. A first electrode AE ​​may be formed on the sixth insulating layer 60, and the first electrode AE ​​may be connected to the connection electrode CNE through a fourth contact hole CH4. A pixel defining layer PDL may be formed on the sixth insulating layer 60 to expose a central portion of the first electrode AE. A preliminary pixel defining layer may be formed on the sixth insulating layer 60, and the preliminary pixel defining layer may be patterned to form a pixel defining layer PDL having an opening OP.

[0164] Thereafter, a hole control layer HCL, a light emitting pattern EML, an electron control layer ECL, and a second electrode CE may be sequentially formed in the non-bending area NBA of the pixel defining layer PDL. When viewed in a plan view, the hole control layer HCL, the light emitting pattern EML, the electron control layer ECL, and the second electrode CE may be at least aligned with the display area DP-DA (e.g., see FIG. Figure 2 ) overlap.

[0165] An encapsulation layer TFE may be formed on the second electrode CE. For the encapsulation layer TFE, an organic encapsulation layer and / or an inorganic encapsulation layer may be formed by a deposition process or an inkjet printing process. The encapsulation layer TFE may be formed in the non-bending area NBA, and the encapsulation layer TFE may not be formed in the bending area BA, but the inventive concept is not limited thereto.

[0166] Fig. 8A is a graph showing current-voltage characteristics of a thin film transistor according to a comparative example, Figure 8B is a graph showing current-voltage characteristics of a thin film transistor according to an embodiment of the inventive concept.

[0167] Fig. 8A is a graph showing current-voltage characteristics of a thin film transistor that has been processed by heat treatment at a relatively low temperature (eg, 300° C. or lower), Figure 8B FIG. 1 is a diagram showing a thin film transistor (eg, referring to FIG. 1 ) processed by heat treatment at a relatively high temperature according to an embodiment of the inventive concept. Figure 3B The current-voltage characteristic curve diagram of the second thin film transistor T2) described in FIG. Fig. 8A and Figure 8B In the voltage V G represents the gate voltage applied to the gate electrode of the thin film transistor, and the current I DS Indicates the amount of current flowing through the channel region of a thin film transistor to which a gate voltage is applied. In addition to the difference in the treatment temperature in the heat treatment step, Fig. 8A and Figure 8B The thin film transistors have been manufactured to have substantially the same features and structures. For ease of illustration, Fig. 8A and Figure 8BThe curves measured from each thin film transistor at different times are plotted in FIG. Fig. 8A and Figure 8B The inventive concept is described in more detail.

[0168] exist Fig. 8A In the comparative example, the heat treatment step of the thin film transistor is performed at a low temperature (eg, 300° C. or less or about 250° C.) which may be too low to damage the fifth insulating layer 50 . Fig. 8A The first curve PL1, the second curve PL2, the third curve PL3, the fourth curve PL4 and the fifth curve PL5 in FIG. 1 are measured sequentially at different times. Fig. 8A As shown in FIG. 1 , as the processing time increases, the curve gradually moves to the left (i.e., from the first curve PL1 to the fifth curve PL5). The threshold voltage difference between the first curve PL1 representing the initial current-voltage property and the fifth curve PL5 representing the last measured current-voltage property is about -5.68 V. That is, in the case where the thin film transistor is not processed at a sufficiently high temperature as in the comparative example, the thin film transistor may suffer from poor uniformity of electrical characteristics and a short lifespan.

[0169] In contrast, Figure 8B The current-voltage curve of FIG. 1 is obtained by heat-treating a thin film transistor including a semiconductor pattern at a temperature of about 380° C. Figure 8B As shown in , the current-voltage curves measured from the thin film transistor at different times tend to a single indistinguishable curve PL-T.

[0170] exist Figure 8B , the threshold voltage difference between the curve representing the initial current-voltage property and the curve representing the last measured current-voltage property is about -0.20V. This indicates that the thin film transistor according to the embodiment of the inventive concept has a constant current-voltage property or uniform electrical characteristics. According to the embodiment of the inventive concept, since the organic layer (e.g., Figure 3B Therefore, even if the fourth insulating layer 40 is heat-treated at a high temperature of 300° C. or higher, the fifth insulating layer 50 is prevented from being damaged. Therefore, the thin film transistor can be manufactured to have improved electrical characteristics and a longer lifespan. In addition, the method according to the embodiment of the inventive concept can stably provide a display panel with high reliability and improved electrical characteristics.

[0171] Fig. 9 is a cross-sectional view showing a portion of a display panel according to an embodiment of the inventive concept. For ease of description, Fig. 9 It is shown in Figure 7Q In the following, reference will be made to Fig. 9 The embodiments of the inventive concept are described in more detail. Figures 1A to 8B The described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0172] exist Fig. 9 In the display panel shown in FIG. 1 , the connection electrode CNE and the sixth insulating layer 60 may be omitted. Therefore, the first electrode AE ​​may be directly disposed on the fifth insulating layer 50 and may be connected to the first output electrode SE1 through the third contact hole CH3. The signal line SL-DL may include a portion overlapping the bending area BA and directly disposed on the fifth insulating layer 50.

[0173] The portion of the signal line SL-DL overlapping the bending area BA may be formed by the same process as that for the first electrode AE. The portion of the signal line SL-DL overlapping the bending area BA and the first electrode AE ​​may include the same material and may have the same layer structure.

[0174] FIG. 10A to FIG. 10D is a cross-sectional view showing a method of manufacturing a display panel according to an embodiment of the inventive concept. To avoid repetition, FIG. 10A to FIG. 10D Reference is shown in FIG. 7A to FIG. 7Q In the following, reference will be made to some of the steps described in FIG. 10A to FIG. 10D The embodiments of the inventive concept are described in more detail. Figures 1A to 9 The described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0175] like Fig. 10A As shown in FIG. 1 , the second preliminary semiconductor pattern OSP2 -P and the contact holes CH1 and CH2 may be formed in the non-bending area NBA of the base layer BL, and the first upper groove GV- 21 may be formed in the bending area BA. Fig. 10A The structure can basically correspond to Figure 7F For the convenience of description, the above technical features may be omitted below.

[0176] Afterwards, if Fig. 10B and Fig. 10C As shown in , a conductive layer CLL may be formed on the third insulating layer 30, and the conductive layer CLL may be patterned using an etching gas ET to form electrodes DE1, SE1, DE2, and SE2. The conductive layer CLL may be formed to cover a top surface of the third insulating layer 30 and a top surface of the second preliminary semiconductor pattern OSP2-P. The conductive layer CLL may also be formed to fill at least a portion of the first upper groove GV-21 and the contact holes CH1 and CH2.

[0177] The etching gas ET may contain a material capable of etching at least a portion of the conductive layer CLL. The etching gas ET may react with an exposed area of ​​the conductive layer CLL that is not shielded by a mask (not shown), and thus, the exposed area of ​​the conductive layer CLL may be removed. Other areas of the conductive layer CLL shielded by the mask may not be etched, thereby forming electrodes DE1, SE1, DE2, and SE2.

[0178] In an embodiment, the etching gas ET may not contain a chlorine compound. As an example, the etching gas ET may contain a fluorine compound containing fluorine (F). For example, the etching gas ET may contain sulfur hexafluoride (SF 6 ) or hexafluorobutyne (C 4 F 6 ).

[0179] In the case of using a fluorine compound, the second semiconductor pattern OSP2 including an oxide semiconductor material may have a relatively slow etching rate compared to the case of using a chlorine compound. For example, in the case of using a fluorine compound in the etching process, the conductive layer CLL may have an etching rate higher than that of the second semiconductor pattern OSP2. The conductive layer CLL may be formed of, for example, molybdenum (Mo), or may include, for example, molybdenum (Mo).

[0180] If the conductive layer CLL includes titanium (Ti), an etching gas including a chlorine compound may be used to etch the conductive layer CLL. When a chlorine compound is used in an etching process, the oxide semiconductor material may have a relatively high etching rate. Therefore, in the case of patterning the conductive layer CLL using an etching gas including a chlorine compound, the second semiconductor pattern OSP2 including an oxide semiconductor material may be easily damaged.

[0181] According to an embodiment of the inventive concept, an etching gas ET including a fluorine compound may be selected to prevent an exposed region of the second semiconductor pattern OSP2 from being damaged due to an etching process for forming the electrodes DE1 , SE1 , DE2 , and SE2 , and to stably form the second semiconductor pattern OSP2 .

[0182] like Fig. 10D As shown in FIG. 4 , a third contact hole CH3 may be formed in the fourth insulating layer 40 , and a connection electrode CNE may be formed to be connected to the first output electrode SE1 . For convenience of explanation, the connection electrode CNE is shown to be disposed on the fourth insulating layer 40 , but the inventive concept is not limited thereto.

[0183] Since the connection electrode CNE is formed after the fourth insulating layer 40 is formed, the connection electrode CNE can be prevented from being damaged. Fig. 10BIn addition, the connection electrode CNE can be formed independently of the step of forming the second semiconductor pattern OSP2 or other elements. For example, the connection electrode CNE can be patterned without considering damage to other elements, and therefore, the material for the connection electrode CNE can be freely selected.

[0184] In an embodiment, the connection electrode CNE may be formed of a material having a lower resistance than the first output electrode SE1, or may include a material having a lower resistance than the first output electrode SE1. In this case, the first output electrode SE1 and the second output electrode SE2 are formed using the same material. Due to the interdependence between the first output electrode SE1 and the second semiconductor pattern OSP2, there may be a limitation on the material of the first output electrode SE1, and this may result in degradation of the electrical characteristics of the display device. However, the connection electrode CNE having a low resistance may be used to improve the electrical characteristics of the display device. For example, the connection electrode CNE may enable the organic light emitting diode OLED (e.g., see Figure 3B ) and the first thin film transistor T1 are connected to each other with low contact resistance to implement a display panel with improved electrical characteristics.

[0185] According to an embodiment of the inventive concept, in a process of manufacturing a semiconductor device in which semiconductor patterns having different characteristics are disposed, heat treatment can be performed without causing damage to an organic layer, thereby improving electrical characteristics of the semiconductor pattern and reliability of the manufacturing process. In addition, the organic layer can be disposed at a position not affected by the heat treatment, thereby realizing a display panel of a thin film device with high reliability and long life.

[0186] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. A display panel, comprising: a base layer including a first region and a second region bent from the first region along a predetermined bending axis; a first thin film transistor disposed in the first region, the first thin film transistor comprising a silicon semiconductor pattern, a first gate electrode disposed on the silicon semiconductor pattern, and a first source electrode and a first drain electrode disposed on the silicon semiconductor pattern; a second thin film transistor disposed in the first region, the second thin film transistor comprising a second gate electrode, an oxide semiconductor pattern disposed on the second gate electrode, and a second source electrode and a second drain electrode disposed on the oxide semiconductor pattern; a first inorganic layer comprising a first groove overlapping the second region; a second inorganic layer including a second groove overlapping the first groove; A first organic layer is disposed in the first region and the second region to cover inner surfaces of the first groove and the second groove; a connecting electrode, disposed on the first organic layer and connected to the first drain electrode or the first source electrode through a contact hole; a signal line disposed in the second region and overlapping the first groove and the second groove; as well as A second organic layer is provided on the connecting electrode, wherein the first gate electrode and the second gate electrode are arranged on the same layer, Wherein, the signal line and the connection electrode are made of the same material, wherein the second organic layer contacts the first organic layer in the second region, and The first organic layer is disposed to contact a portion of the top surface of the base layer in the second region.

2. The display panel according to claim 1, wherein: The second source electrode and the second drain electrode include molybdenum.

3. The display panel according to claim 1, wherein: The connection electrode includes a material different from that of the first drain electrode.

4. The display panel according to claim 3, wherein: The connection electrode includes a material having a lower resistance than that of the first drain electrode.

5. The display panel according to claim 1, further comprising: a pixel defining layer disposed on the first organic layer and comprising an opening; and an organic light emitting diode disposed in the opening and electrically connected to the first thin film transistor, The pixel defining layer overlaps the first region and the second region and includes an organic material.

6. The display panel according to claim 5, wherein: The pixel defining layer further includes a concave portion on an inner surface of the opening.

7. The display panel according to claim 1, wherein: The signal line and the second drain electrode are arranged on the same layer.

8. The display panel according to claim 7, wherein: The signal line includes a plurality of patterns that are disposed in the second region and are spaced apart from each other in a direction crossing the bending axis.

9. The display panel according to claim 1, wherein: The first inorganic layer contacts the oxide semiconductor pattern.

10. The display panel according to claim 1, wherein: The signal line and the connection electrode are arranged on the same layer.

11. A display panel, comprising: Base layer; a first thin film transistor including a silicon semiconductor pattern, a first gate electrode disposed on the silicon semiconductor pattern, and a first source electrode and a first drain electrode disposed on the silicon semiconductor pattern; a second thin film transistor including a second gate electrode, an oxide semiconductor pattern disposed on and overlapping the second gate electrode, and a second source electrode and a second drain electrode disposed on the oxide semiconductor pattern; A first inorganic layer is arranged to overlap the first thin film transistor and the second thin film transistor in a thickness direction, and the first inorganic layer includes a first groove; A second inorganic layer is disposed between the first thin film transistor, the second thin film transistor and the base layer, and the second inorganic layer includes a second groove; An organic layer, disposed on the first thin film transistor and the second thin film transistor; a connecting electrode, disposed on the organic layer and connected to the first drain electrode through a contact hole; as well as a metal pattern overlapping the oxide semiconductor pattern and formed with the connection electrode through a single patterning process using a same mask, wherein the connection electrode includes a material different from that of the first source electrode and the first drain electrode, The organic layer is disposed to contact a portion of the top surface of the base layer at the first groove and the second groove.

12. The display panel according to claim 11, further comprising a light emitting diode, the light emitting diode being disposed on the organic layer and electrically connected to the first thin film transistor, in, The connection electrode is coupled to each of the light emitting diode and the first drain electrode.

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