Integrated GaN-based logic level shifter

Abstract

A circuit topology for use as a single-ended or differential level conversion interface for a GaN IC that allows the GaN IC to be controlled using a standard low voltage CMOS level input. The logic level conversion circuit is based on a resistance network, so that the logic level conversion circuit is not sensitive to process and temperature changes, and is particularly suitable for being realized in a GaN IC (Integrated Circuit). A resistive network of a single-ended input signal includes a first branch having a voltage divider connected to the input signal. The voltage divider of the first branch provides a level-shifted and scaled input signal at an optimal bias point of the comparator to a first input of the comparator. The resistive network also includes a second voltage divider branch having a hysteresis for providing a jump voltage to a second input of the comparator also at an optimal bias point of the comparator. The comparator outputs a level-converted complementary bipolar signal corresponding to the input signal. For the differential input signal, both branches of the resistive network follow the topology of the first branch of the single-ended input signal.

Description

Background Art

[0001] In general, modern microprocessors implemented in power control systems use logic levels derived from 1.8V or 3.3V supplies. Therefore, the input control logic level of the power integrated circuit (IC) can be as low as 1.4V (for a 1.8V microprocessor supply) or 2.0V (for a 3.3V microprocessor supply). The threshold voltage V of a silicon-based CMOS field effect transistor (FET) is th Typically in the range of 0.6-0.7 V. Therefore, a 1.4 V input high voltage from a CMOS controller is sufficient to turn on the CMOS FET.

[0002] However, the threshold voltage V of GaN FET th In the 1.5-2.5V range, and typically require a control voltage of at least 4V to fully turn on. Therefore, using a 2.4V control signal from a CMOS controller may not reliably guarantee the turn-on of a GaN FET. Therefore, in order for a GaN FET to be controlled using CMOS logic levels, a dedicated circuit is required that can convert the CMOS logic level signal to a signal with a voltage level sufficient to turn on the GaN FET.

[0003] FIG1 is a typical logic level converter circuit 100. The circuit 100 includes a power supply voltage V connected to a FET transistor 102 through a resistor 101. dd1 The source of FET 102 is connected to the gate of FET 104 in inverter stage X, which is connected to a higher supply voltage V ddX Resistors 101 and 103 are selected based on the drive strength (final output level) required for a particular application. The output from inverter stage X is at 0V and the voltage V ddX Switch between.

[0004] In circuit 100, the threshold voltages V of FETs 102 and 104 are th must be significantly lower than the supply voltage V dd , in order to operate the circuit correctly. If V dd Less than or equal to the threshold voltage V of FET 102 th , or the threshold voltage Vth of FET 102 increases with time and becomes greater than V dd , the level converter circuit 100 will not work properly.

[0005] FIG2 is a conventional differential latch-based logic level converter circuit 200. The differential latch-based logic level converter circuit 200 includes inputs Xn and Xn of opposite polarity, which are provided to a differential cross-coupling structure that latches the output to a higher supply voltage V than the input. ddH. Input Xn and X are at a lower voltage V ddL , which is lower than the power supply voltage V ddH As with the circuit of FIG. 1 , the circuit of FIG. 2 is only limited to the threshold voltage V of NFETs 201 - 204. th Significantly lower than the input voltage level V ddL If the input voltage level is less than or equal to the threshold voltage V th , then the differential latch-based logic level converter circuit 200 will not work correctly.

[0006] FIG3 is a typical common gate based logic level conversion circuit 300. The common gate based logic level conversion circuit 300 includes a FET 102 having a source S, a drain D, and a gate G. The input (low side) is fed to the source S of the FET 102, whose gate G is DC biased. The high side output at the drain D of the FET 102 swings in phase with the low side input. Therefore, when the input at the source S swings high to the gate voltage level, the FET 102 is turned off, and the high side swings to a higher pull-up voltage V dd The input threshold level is set using a gate voltage bias (derived from a voltage divider formed by resistors 104 and 106) to reach the threshold voltage V of FET 102 at the input level. th FET 102 is turned off when

[0007] In the circuit of FIG. 3 , a voltage lower than the threshold voltage V of FET 102 may be used. th The input signal level is used to obtain the V dd However, the trip level of the common-gate-based logic level conversion circuit 300 depends on the threshold voltage V of FET 102. th , the value of the threshold voltage is highly dependent on process and temperature. In addition, the hysteresis level achieved by changing the gate voltage level is also affected by the threshold voltage V of FET 102. th Therefore, the jump voltage and hysteresis level of the common gate-based logic level conversion circuit 300 vary with the threshold voltage V of the FET 102. th changes with the changes.

[0008] FIG4 shows a prior art voltage divider level shifting circuit 400. The voltage divider level shifting circuit 400 includes a differential comparator 402 powered by a 5V supply, and a resistor network at the input that converts a negative pulse train into a level shifted complementary bipolar output. A voltage divider formed by resistors 406 and 408 level scales the input signal before applying it to the non-inverting phase of the differential comparator 402. A second voltage divider formed by resistors 404 and 410 is connected to the non-inverting input of the differential comparator 402. The circuit advantageously converts a GaN FET having a threshold voltage V lower than the GaN FET. th The voltage level of the input signal is converted to V CC An output signal that swings between 0 and ground.

[0009] However, in the circuit of FIG4, the floating input of the differential comparator 402 sets the output of the voltage divider logic level converter circuit 400 to be positive (or negative, based on the input configuration). In addition, since the input of the differential comparator 402 is not biased at the optimal gain of the differential comparator 402, the output swing is dependent only on large swings of the input signal. If the circuit of FIG4 is implemented in GaN for use in a GaN IC, the low gain of the GaN comparator will result in a relatively slow response to input signal swings that are not near the optimal bias point of the comparator.

[0010] It would therefore be desirable to provide a level shifter circuit implemented in GaN that shifts low voltage CMOS signals to a level sufficient to turn on a GaN FET and avoids the disadvantages of the above-described circuits. Summary of the invention

[0011] The present invention overcomes the above disadvantages and achieves the above objects by providing a GaN-based level shifter circuit that converts a low voltage CMOS signal to a level sufficient to turn on a GaN FET.

[0012] More specifically, as described herein, the present invention is an integrated GaN-based logic level converter, which includes a GaN differential comparator and a resistor network. The resistor network includes a first voltage divider for receiving a single-ended input signal and outputting a level-converted and scaled signal, and a second voltage divider for generating a jump voltage. The second voltage divider circuit includes a resistor hysteresis circuit. The level-converted and scaled signal is connected to a first input of the GaN differential comparator, and the jump voltage from the second voltage divider is connected to a second input of the GaN differential comparator, so that the positive and negative outputs of the GaN differential comparator include positive and negative complementary bipolar signals corresponding to the input signal after level conversion.

[0013] The present invention also provides an integrated GaN-based logic level converter for differential input signals. For differential inputs, the resistor network includes two voltage divider branches, one for each input. Each branch of the resistor network receives an input signal and outputs a level-converted and scaled signal to a corresponding input of a comparator. A resistor hysteresis circuit may also be included in the negative resistance branch of this embodiment of the present invention.

[0014] The resistor network based level shifter of the present invention is process and temperature insensitive and is particularly suitable for level shifting CMOS level inputs and LVDS type differential signals to higher levels to control GaN FETs whose gate threshold levels are process and temperature dependent. The resistor network of the present invention advantageously provides a level shifted input at an optimal bias point of the GaN comparator. The trip level range of the logic level shifter of the present invention is much smaller than that of a conventional gate level shifter because the trip threshold range is limited only by the input offset level of the comparator.

[0015] Other features and advantages of the present invention will be described in the following description, and some features and advantages will be apparent from the description, or can be understood through the practice of the present invention. The features and advantages of the present invention can be realized and obtained by the means and combinations specifically pointed out in the appended claims. These and other features of the present invention will become more apparent from the following description and the appended claims, or can be understood through the practice of the present invention described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to further illustrate the above and other advantages and features of the present invention, the present invention will be described in more detail with reference to the specific embodiments shown in the accompanying drawings. It should be understood that these drawings depict only typical embodiments of the present invention and should not be considered to limit its scope. The present invention will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0017] FIG1 is a conventional logic level converter circuit;

[0018] FIG2 is a conventional differential latch-based logic level converter;

[0019] FIG3 is a conventional common-gate based logic level converter;

[0020] FIG4 is a prior art voltage divider level converter circuit design;

[0021] Figure 5 The resistor network based logic level converter circuit of the present invention with a single ended input is shown;

[0022] Figure 6 The resistor network based logic level converter circuit of the present invention having a differential input is shown; and

[0023] Figure 7 A resistor network based logic level converter circuit of the present invention is shown having differential inputs and having series input resistors to accommodate large input signals. DETAILED DESCRIPTION

[0024] It should be understood that the drawings and description of the present invention may have been simplified to illustrate only the elements relevant to a clear understanding of the present embodiment. Those of ordinary skill in the art will recognize that other elements may be desirable and / or required in order to implement the present embodiment. It should also be understood that the drawings included herein only provide schematic diagrams of the presently preferred embodiments of the present invention. Reference will now be made to the accompanying drawings, in which similar structures have the same reference numerals.

[0025] Figure 5 The resistor network-based logic level converter of the present invention is shown, which is designed to level-convert a low voltage input signal (e.g., a CMOS level signal) to a voltage level that is higher than the maximum threshold voltage Vth of the GaN transistor integrated in the GaN IC. The level converter circuit 500 includes a resistor network 502, a GaN differential comparator 520, a single-ended input signal In and an input Off (for pulling the input signal low), and power supplies Vdd and Vss. The GaN differential comparator 520 (which is connected to the power supplies Vdd and Vss) receives the input signals InP and Vtrip from the resistor network 502 and generates inverted (complementary bipolar) level-converted output signals OutP and OutN. Vtrip is the level that the input signal "In" must exceed as the minimum V for the output OutP to rise. inHi_LOW Level.

[0026] More specifically, if Figure 5 As shown, the input signal In is connected to a voltage divider between Vdd and Vss, which includes a resistor 504, a scaling resistor 506, and an offset resistor 508, which are connected in series and form a voltage divider for level shifting and scaling the input In to the input InP. The values ​​of the resistor 504 and the scaling resistor 506 are set so that InP hovers near the optimal bias point of the GaN comparator 520, thereby increasing the speed of the comparator. The offset resistor 508 ensures that if the input "In" floats, the output OutP remains low and the output OutN remains high. The value of the offset resistor 508 depends on the amount of the maximum input offset expected at the comparator 520.

[0027] The voltage at Vtrip of the input to the GaN comparator 520 is determined by the values ​​of resistors 510 and 512, which form a voltage divider to set the voltage at Vtrip of the input to the comparator 520. In a manner similar to the voltage divider for the input signal, resistors 510 and 512 are set so that Vtrip hovers around the optimal bias point for the input of the comparator 520. Vtrip is also determined by a hysteresis circuit H formed by resistor 516 and FET 518, which is controlled by one of the positive outputs (similar to output OutP) of the comparator 520. The hysteresis circuit H ensures that any noise voltage in the range around the trip point of the comparator 520 does not reset the output of the comparator 520. This is achieved by increasing (or decreasing) the reference voltage by a scaling amount that exceeds the noise level expected after the comparator 520 has made its first trip. Because the hysteresis is set by the resistor divider, it is not sensitive to process or temperature variations, similar to the rest of the resistor network 502.

[0028] The level shifter circuit 500 generates a positive level shifted output signal OutP and a negative level shifted output signal OutN based on a single-ended input signal. The level shifter circuit 500 can be turned off by applying a logic high signal to the "Off" terminal, which turns on the FET 514, shorting the input InP to VSS (ground), making OutP low and OutN high.

[0029] Figure 6 shows a differential signal input instead of Figure 5 The resistor network 602 is designed for single-ended input. Figure 6 In the differential input embodiment, both input branches of the resistor network 602 follow Figure 5 The topology of the "In" branch of Figure 6 , the differential signal inputs InP and InM are both connected to corresponding resistor dividers between Vdd and VSS. The voltage divider for the positive input InP includes a resistor 604, a scaling resistor 606, and an offset resistor 608 connected in series. Similarly, the voltage divider for the input InM includes a resistor 624, a scaling resistor 626, and an offset resistor 628 connected in series. Although not shown, the signals Pos and Neg from the voltage divider are connected as inputs to the non-inverting terminal and the inverting terminal of the GaN differential comparator, respectively, similar to Figure 5 The connections of InP and Vtrip to GaN comparator 520 are shown in FIG. In addition, similar to Figure 5 FET 514 in , if the input signal Off is set to logic high, FET 614 is used to short Pos to VSS (ground), making OutP low and OutN high. Although not shown, the hysteresis circuit (e.g. Figure 5) as shown in and described above may be connected to the negative resistor branch to produce hysteresis for the corresponding logic converter.

[0030] The value of the offset resistor 628 for the InM input is slightly higher than the value of the offset resistor 608 for the InP input to ensure that if the input signals InP and InM float, the output remains low. The difference in the values ​​of the offset resistors 608 and 628 depends on the amount of maximum input offset expected at the GaN comparator to which the voltage divider outputs Pos and Neg are connected. The values ​​of the offset resistors 608 and 628 can also be set to allow level shifting of low voltage differential signaling (LVDS). A typical LVDS common mode voltage is about 1.3V, which is well below the value of the threshold voltage Vth of the GaN FET.

[0031] Figure 7 The present invention shows a logic level converter circuit based on a resistor network, whose differential input and Figure 6 The differential inputs of are similar, but with series input resistors to accommodate large input signals. Specifically, the logic level converter circuit 700 includes series resistors 716 and 718 at the inputs InP and InM, respectively, for reducing the large input signal voltage to a lower level. Figure 7 In the hysteresis circuit (e.g. Figure 5 The hysteresis circuit shown in FIG. 700 can be connected to the negative resistor branch to produce the corresponding hysteresis of the logic converter. Figure 7 The logic level converter implements the input attenuation and level shifting required to interface with GaN FETs while ensuring that the maximum input voltage swing does not damage the input GaN FETs.

[0032] In summary, in the various embodiments described above, the present invention advantageously provides a circuit topology that can be used as a single-ended or differential level-shifting interface for GaN ICs, thereby allowing the use of standard low-voltage CMOS level input control ICs. The level-shifting circuit of the present invention is based on a resistor network and is therefore insensitive to process and temperature variations, making it particularly suitable for implementation in GaN ICs. The resistor network of the level converter of the present invention includes an offset resistor circuit so that the input of the GaN comparator can be set to hover around the optimal bias point of the comparator. The circuit system of the present invention includes hysteresis, which is also set by a resistor circuit and is therefore also independent of process and temperature variations. Input resistors can be provided to scale down the high-voltage input signals that are prevalent in older analog control systems to avoid damage to the input GaN FETs.

[0033] The present invention may be implemented in other specific forms without departing from its spirit or essential characteristics. The described embodiments should be considered in all respects as illustrative only and not restrictive. Therefore, the scope of the present invention is indicated by the appended claims rather than the foregoing description. All changes within the equivalent meaning and scope of the claims should be included within their scope.

Claims

1. An integrated GaN-based logic level converter, comprising: A GaN differential comparator having first and second inputs and corresponding positive and negative outputs; as well as a resistor network including a plurality of resistors, the resistor network including a first voltage divider for receiving an input signal and outputting a level-shifted and scaled input signal, and a second voltage divider for generating a trip voltage, the second voltage divider including a resistor hysteresis circuit; wherein the level-converted and scaled input signal from the first voltage divider is connected to the first input of the GaN differential comparator, and the trip voltage from the second voltage divider is connected to the second input of the GaN differential comparator, such that the positive output and the negative output of the GaN differential comparator include level-converted complementary bipolar signals corresponding to the input signal. 2 . The integrated GaN-based logic level converter of claim 1 , wherein the first voltage divider comprises a first resistor, a scaling resistor, and an offset resistor arranged in series between a voltage source and a lower voltage.

3. The integrated GaN-based logic level converter of claim 2, wherein the input signal is connected between the scaling resistor and the offset resistor, and the first input of the GaN differential comparator is connected between the first resistor and the scaling resistor.

4. The integrated GaN-based logic level converter of claim 2, wherein the value of the first resistor and the value of the offset resistor are set so that: the level-converted and scaled input signal to the first input of the comparator hovers around an optimal bias point of the comparator. 5 . The integrated GaN-based logic level converter of claim 4 , wherein the second voltage divider generates a trip voltage that hovers around the optimal bias point of the comparator. 6 . The integrated GaN-based logic level converter according to claim 2 , wherein the GaN differential comparator is configured to control the hysteresis circuit by outputting a signal to a gate of a FET connected to the hysteresis circuit.

7. An integrated GaN-based logic level converter for a differential input having a first input signal and a second input signal, the integrated GaN-based logic level converter comprising: A GaN differential comparator having first and second inputs and corresponding positive and negative outputs; as well as A resistor network comprising a plurality of resistors, the resistor network comprising: a first voltage divider for receiving the first input signal and outputting a first level-converted and scaled input signal, and a second voltage divider for receiving the second input signal and outputting a second level-converted and scaled input signal; wherein the first level-converted and scaled input signal from the first voltage divider of the GaN differential comparator is connected to the first input of the GaN differential comparator, and the second level-converted and scaled input signal from the second voltage divider is connected to the second input of the GaN differential comparator, such that the positive output and the negative output of the GaN differential comparator include level-converted complementary bipolar signals corresponding to the first input signal and the second input signal.

8. The integrated GaN-based logic level converter of claim 7, wherein the first voltage divider and the second voltage divider each include a first resistor, a scaling resistor, and an offset resistor arranged in series between a voltage source and a lower voltage.

9. The integrated GaN-based logic level converter of claim 8, wherein the first input signal and the second input signal are connected between the scaling resistor and the offset resistor of the first voltage divider and the second voltage divider, respectively, and the first input and the second input of the GaN differential comparator are connected between the first resistor and the scaling resistor of the first voltage divider and the second voltage divider, respectively.

10. The integrated GaN-based logic level converter of claim 8, wherein the value of the first resistor of the first voltage divider and the value of the offset resistor of the second voltage divider are set so that: the level-converted and scaled input signals at the first input and the second input of the comparator hover around an optimal bias point of the comparator.

11. The integrated GaN-based logic level converter of claim 7, wherein the first voltage divider and the second voltage divider each further comprise a respective resistive hysteresis circuit. 12 . The integrated GaN-based logic level converter according to claim 7 , further comprising a first input resistor and a second input resistor, the first input resistor and the second input resistor being used to reduce voltage levels of the first input signal and the second input signal, respectively.

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