A HVIC undervoltage protection test circuit and test method

Abstract

The present invention relates to the field of integrated circuit technology, and in particular to an HVIC undervoltage protection test circuit and test method. The present invention uses an undervoltage protection test circuit and test method based on the outside of HVIC to test the undervoltage threshold, reset voltage and trigger delay of the power supply VCC and bootstrap voltage VB of the HVIC at different temperatures, and judge whether the undervoltage protection function of the power supply voltage VCC and the bootstrap voltage VB of the HVIC is normal, so as to achieve the effect of checking whether the undervoltage protection function of the HVIC is normal. Through a unified detection process, it is possible to prevent products with unqualified undervoltage protection functions from entering the market, thereby improving the availability of circuit devices.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a HVIC undervoltage protection test circuit and a test method. Background Art

[0002] With the rapid development of industry, intelligent power modules (IPM) are widely used in various fields. As one of the key components inside IPM, the performance of high-voltage integrated circuits (HVIC) determines the performance of IPM, and the undervoltage protection circuit is a very important circuit inside HVIC. The power supply voltage VCC and VB voltage (VB voltage is obtained by charging VCC) of HVIC work. If the voltage of VCC and VB is too low, the heat of the subsequent circuit of HVIC will increase, reduce its efficiency, and even damage the subsequent circuit in severe cases. In the HVIC circuit structure, an undervoltage protection circuit is introduced to monitor the VCC voltage and VB voltage. When the VCC or VB voltage is too low, the two output ends of HVIC are simultaneously at a low level (the subsequent circuit stops working) to protect the subsequent circuit. Therefore, when HVIC is produced off the line, it is necessary to test whether the performance indicators of its undervoltage protection circuit meet the standards.

[0003] However, the existing HVIC undervoltage protection circuit test process is not unified, the detection process does not have a relatively complete standard, and the test results are relatively incomplete. Summary of the invention

[0004] The invention provides a HVIC undervoltage protection test circuit and a test method, aiming to solve the problems that the existing undervoltage protection circuit test process is not standard and the test results are not comprehensive.

[0005] In order to solve the above technical problems, in a first aspect, the present invention provides an HVIC undervoltage protection test circuit, the HVIC undervoltage protection test circuit comprises a first path, a second path, a third path, a fourth path, and a fifth path, the voltage terminal VCC / VB, the high level input terminal HIN, the high level output terminal HO, the low level input terminal LIN, and the low level output terminal LO of the HVIC undervoltage protection circuit to be tested are connected to the ground terminal GND through the first path, the second path, the third path, the fourth path, and the fifth path, respectively, wherein:

[0006] The first path, the second path, the third path, the fourth path, and the fifth path are respectively provided with a first oscilloscope signal sampling input channel, a second oscilloscope signal sampling input channel, a third oscilloscope signal sampling input channel, a fourth oscilloscope signal sampling input channel, and a fifth oscilloscope signal sampling input channel connected to an external oscilloscope in series, a first end of each oscilloscope signal sampling input channel is connected to the corresponding voltage terminal VCC / VB, the high level input terminal HIN, the high level output terminal HO, the low level input terminal LIN, and the low level output terminal LO, and a second end of each oscilloscope signal sampling input channel is connected to the ground terminal GND;

[0007] The HVIC undervoltage protection test circuit also includes a first electrical switch, a second electrical switch, an adjustable DC power supply, a power pin filter capacitor, a first signal generator output port, a second signal generator output port, and a third signal generator output port, wherein a first end of the first electrical switch is connected to a first end of the first oscilloscope signal sampling input channel, a second end of the first electrical switch is respectively connected to a first end of the adjustable DC power supply and a first end of the power pin filter capacitor, and a second end of the adjustable DC power supply and a second end of the power pin filter capacitor are respectively connected to a second end of the first oscilloscope signal sampling input channel;

[0008] A first end of the second electrical switch is connected to a first end of the first oscilloscope signal sampling input channel, a second end of the second electrical switch is connected to a first end of the first signal generator output port, and a second end of the first signal generator output port is connected to a second end of the first oscilloscope signal sampling input channel;

[0009] A first end of the second signal generator output port is connected to a first end of the second oscilloscope signal sampling input channel, and a second end of the second signal generator output port is connected to a second end of the second oscilloscope signal sampling input channel;

[0010] A first end of the third signal generator output port is connected to a first end of the third oscilloscope signal sampling input channel, and a second end of the third signal generator output port is connected to a second end of the third oscilloscope signal sampling input channel.

[0011] Furthermore, the maximum output voltage of the adjustable DC power supply is 20V, and the maximum output current is 0.5A.

[0012] Furthermore, the output voltage range of the output port of the first signal generator is 9V-15V.

[0013] Furthermore, the output voltage range of the second signal generator output port and the third signal generator output port is 0V-5V.

[0014] In a second aspect, the present invention further provides an HVIC undervoltage protection test method implemented based on the HVIC undervoltage protection test circuit as described in any one of the above items, comprising the following steps:

[0015] S101, determining an undervoltage threshold, a reset voltage, and a maximum delay of an HVIC undervoltage protection circuit to be tested;

[0016] S102, setting the test temperature;

[0017] S103, turning off the second electrical switch, closing the first electrical switch, inputting a first pulse to the high level input terminal HIN and the low level input terminal LIN through the adjustable DC power supply, and adjusting the voltage terminal VCC / VB downward from the first preset voltage, and reading the voltage meter reading through an external oscilloscope;

[0018] S104, when the output voltages of the high level output terminal HO and the low level output terminal LO both jump to a low level, recording the jump power supply voltage as an undervoltage threshold test result;

[0019] S105, turning off the second electrical switch, closing the first electrical switch, inputting the first pulse to the high level input terminal HIN and the low level input terminal LIN through the adjustable DC power supply, and adjusting the voltage terminal VCC / VB upward from the second preset voltage, and reading the voltage meter reading through the external oscilloscope;

[0020] S106, when the output voltages of the high level output terminal HO and the low level output terminal LO both jump to the same voltage as the voltage terminal VCC / VB, record the jump power supply voltage as the reset voltage threshold test result;

[0021] S107, opening the first electrical switch, closing the second electrical switch, inputting a second pulse to the voltage terminal VCC / VB through a signal generator, reading a voltage waveform through the external oscilloscope, and recording a delay time of voltage input and output as a trigger delay test result;

[0022] S108, comparing the undervoltage threshold test result, the reset voltage threshold test result, and the trigger delay test result with the undervoltage threshold, the reset voltage, and the maximum delay, respectively, to obtain the HVIC undervoltage protection test result of the current test temperature.

[0023] Furthermore, the HVIC undervoltage protection test method further comprises the steps of:

[0024] S109, determining the operating temperature of the HVIC undervoltage protection circuit to be tested, changing the current test temperature through the temperature control box, and then returning to step S103.

[0025] Furthermore, the undervoltage threshold, the reset voltage and the maximum delay are 10V, 10.7V and 20µs respectively, the first pulse is a pulse with a high voltage of 5V, a low voltage of 0V and a width greater than 50µs, the second pulse is a pulse with a high voltage of 15V, a low voltage of 9V and a width greater than 50µs, the first preset voltage is 15V, and the second preset voltage is 5V.

[0026] The beneficial effect achieved by the present invention is that the undervoltage threshold, reset voltage and trigger delay of the power supply VCC and the bootstrap voltage VB of the HVIC are tested at different temperatures by an undervoltage protection test circuit and a test method based on the outside of the HVIC, and whether the undervoltage protection function of the power supply voltage VCC and the bootstrap voltage VB of the HVIC is normal is judged, so as to achieve the effect of checking whether the undervoltage protection function of the HVIC is normal. Through a unified detection process, products with unqualified undervoltage protection functions can be prevented from entering the market, thereby improving the availability of circuit devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 1 is a schematic diagram of the structure of an HVIC undervoltage protection test circuit provided by an embodiment of the present invention;

[0028] Figure 2 1 is a schematic diagram of the steps of the HVIC undervoltage protection test method provided by an embodiment of the present invention;

[0029] Figure 3 is a schematic diagram of the timing of an undervoltage threshold test provided by an embodiment of the present invention;

[0030] Figure 4 is a schematic diagram of a reset voltage threshold test timing sequence provided by an embodiment of the present invention;

[0031] Figure 5 It is a timing diagram of a trigger delay time test provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0033] Please refer to Figure 1 , Figure 12 is a schematic diagram of the structure of the HVIC undervoltage protection test circuit provided by an embodiment of the present invention. The HVIC undervoltage protection test circuit 200 includes a first path, a second path, a third path, a fourth path, and a fifth path. The voltage terminal VCC / VB, the high level input terminal HIN, the high level output terminal HO, the low level input terminal LIN, and the low level output terminal LO of the HVIC undervoltage protection circuit 201 to be tested are connected to the ground terminal GND through the first path, the second path, the third path, the fourth path, and the fifth path, respectively.

[0034] The first path, the second path, the third path, the fourth path, and the fifth path are respectively connected in series with a first oscilloscope signal sampling input channel 206, a second oscilloscope signal sampling input channel 207, a third oscilloscope signal sampling input channel 208, a fourth oscilloscope signal sampling input channel 209, and a fifth oscilloscope signal sampling input channel 210 connected to an external oscilloscope, a first end of each oscilloscope signal sampling input channel is connected to the corresponding voltage terminal VCC / VB, the high level input terminal HIN, the high level output terminal HO, the low level input terminal LIN, and the low level output terminal LO, and a second end of each oscilloscope signal sampling input channel is connected to the ground terminal GND;

[0035] The HVIC undervoltage protection test circuit 200 also includes a first electrical switch 204, a second electrical switch 205, an adjustable DC power supply 202, a power supply pin filter capacitor 203, a first signal generator output port 211, a second signal generator output port 212, and a third signal generator output port 213, wherein a first end of the first electrical switch 204 is connected to a first end of the first oscilloscope signal sampling input channel 206, a second end of the first electrical switch 204 is respectively connected to a first end of the adjustable DC power supply 202 and a first end of the power supply pin filter capacitor 203, and a second end of the adjustable DC power supply 202 and a second end of the power supply pin filter capacitor 203 are respectively connected to a second end of the first oscilloscope signal sampling input channel 206;

[0036] A first end of the second electrical switch 205 is connected to a first end of the first oscilloscope signal sampling input channel 206, a second end of the second electrical switch 205 is connected to a first end of the first signal generator output port 211, and a second end of the first signal generator output port 211 is connected to a second end of the first oscilloscope signal sampling input channel 206;

[0037] A first end of the second signal generator output port 212 is connected to a first end of the second oscilloscope signal sampling input channel 207, and a second end of the second signal generator output port 212 is connected to a second end of the second oscilloscope signal sampling input channel 207;

[0038] A first end of the third signal generator output port 213 is connected to a first end of the third oscilloscope signal sampling input channel 208 , and a second end of the third signal generator output port 213 is connected to a second end of the third oscilloscope signal sampling input channel 208 .

[0039] Furthermore, the maximum output voltage of the adjustable DC power supply 202 is 20V, and the maximum output current is 0.5A.

[0040] Furthermore, the output voltage range of the first signal generator output port 211 is 9V-15V.

[0041] Furthermore, the output voltage range of the second signal generator output port 212 and the third signal generator output port 213 is 0V-5V.

[0042] The present invention also provides a HVIC undervoltage protection test method based on the HVIC undervoltage protection test circuit as described in any one of the above items, please refer to Figure 2 , including the following steps:

[0043] S101, determining an undervoltage threshold, a reset voltage, and a maximum delay of an HVIC undervoltage protection circuit to be tested;

[0044] S102, setting the test temperature;

[0045] S103, turning off the second electrical switch 205, closing the first electrical switch 204, inputting a first pulse to the high level input terminal HIN and the low level input terminal LIN through the adjustable DC power supply 202, and adjusting the voltage terminal VCC / VB downward from the first preset voltage, and reading the voltage meter reading through an external oscilloscope;

[0046] S104, when the output voltages of the high level output terminal HO and the low level output terminal LO both jump to a low level, record the jump power supply voltage UVt as the undervoltage threshold test result; the undervoltage threshold test timing is as follows: Figure 3 As shown, in this step, at the beginning, the voltage meter readings of the high level output terminal HO and the low level output terminal LO should be consistent with the power supply voltage readings. When the power supply voltage VCC and VB readings are lower than a certain value, the output HO and LO voltages should suddenly jump to a low level. At this time, the jump power supply voltage UVt is recorded as the undervoltage threshold test result;

[0047] S105, turning off the second electrical switch 205, closing the first electrical switch 204, inputting the first pulse to the high level input terminal HIN and the low level input terminal LIN through the adjustable DC power supply 202, and adjusting the voltage terminal VCC / VB upward from the second preset voltage, and reading the voltage meter reading through the external oscilloscope;

[0048] S106, when the output voltages of the high level output terminal HO and the low level output terminal LO both jump to the same voltage as the voltage terminal VCC / VB, record the jump power supply voltage UVr as the reset voltage threshold test result; the reset voltage threshold test timing is as follows: Figure 4 As shown, in this step, at the beginning, the voltage readings of the high level output terminal HO and the low level output terminal LO should remain at a low level. When the power supply voltage VCC and VB readings are higher than a certain value, the HO and LO voltages should suddenly jump to readings consistent with the power supply voltage. At this time, the power supply voltage continues to increase, and the output voltage should be consistent with the power supply voltage.

[0049] S107, disconnect the first electrical switch 204, close the second electrical switch 205, input a second pulse to the voltage terminal VCC / VB through the signal generator, read the voltage waveform (VIN, VOUT) through the external oscilloscope, and record the voltage input and output delay time tUV as the trigger delay test result; the trigger delay time test timing is as follows Figure 5 As shown;

[0050] S108, comparing the undervoltage threshold test result, the reset voltage threshold test result, and the trigger delay test result with the undervoltage threshold, the reset voltage, and the maximum delay, respectively, to obtain the HVIC undervoltage protection test result of the current test temperature.

[0051] Generally, the undervoltage threshold, the reset voltage and the maximum delay in the embodiment of the present invention are all specific values. When the undervoltage threshold test result, the reset voltage threshold test result and the trigger delay test result are compared with the undervoltage threshold, the reset voltage and the maximum delay respectively, a numerical comparison result will be obtained, wherein the undervoltage threshold and the maximum delay are both upper limit values, and the reset voltage is a comparison value. During the implementation process, if the undervoltage threshold test result is less than the undervoltage threshold, it means that the undervoltage capability of the HVIC at the current temperature is normal, otherwise, it means that the undervoltage capability of the HVIC at the current temperature does not meet the requirements;

[0052] Correspondingly, if the trigger delay test result is less than the maximum delay, it means that the HVIC delay time at the current temperature is normal, otherwise it does not meet the requirements;

[0053] If the reset voltage threshold test result is equal to the reset voltage, it means that the voltage reset capability of the HVIC at the current temperature is normal, otherwise it means that the voltage reset capability of the HVIC does not meet the requirements.

[0054] Furthermore, the HVIC undervoltage protection test method further comprises the steps of:

[0055] S109, determine the operating temperature of the HVIC undervoltage protection circuit to be tested, change the current test temperature through the temperature control box, and return to step S103. The operating characteristics of HVIC will change to a certain extent at different temperatures. Therefore, to determine whether the performance of an HVIC meets the standard, it is necessary to test whether the parameters of each functional circuit meet the standard at different temperatures. Generally, the temperature control range of the temperature control box is best between -45℃ and 145℃, and the control accuracy is 1℃.

[0056] Furthermore, the undervoltage threshold, the reset voltage and the maximum delay are 10V, 10.7V and 20µs respectively, the first pulse is a pulse with a high voltage of 5V, a low voltage of 0V and a width greater than 50µs, the second pulse is a pulse with a high voltage of 15V, a low voltage of 9V and a width greater than 50µs, the first preset voltage is 15V, and the second preset voltage is 5V.

[0057] The beneficial effect achieved by the present invention is that the undervoltage threshold, reset voltage and trigger delay of the power supply VCC and the bootstrap voltage VB of the HVIC are tested at different temperatures by an undervoltage protection test circuit and a test method based on the outside of the HVIC, and whether the undervoltage protection function of the power supply voltage VCC and the bootstrap voltage VB of the HVIC is normal is judged, so as to achieve the effect of checking whether the undervoltage protection function of the HVIC is normal. Through a unified detection process, products with unqualified undervoltage protection functions can be prevented from entering the market, thereby improving the availability of circuit devices.

[0058] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0059] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0060] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0061] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A HVIC undervoltage protection test circuit, characterized in that: The HVIC undervoltage protection test circuit includes a first path, a second path, a third path, a fourth path, and a fifth path. The voltage terminal VCC / VB, the high level input terminal HIN, the high level output terminal HO, the low level input terminal LIN, and the low level output terminal LO of the HVIC undervoltage protection circuit to be tested are connected to the ground terminal GND through the first path, the second path, the third path, the fourth path, and the fifth path, respectively. The first path, the second path, the third path, the fourth path, and the fifth path are respectively provided with a first oscilloscope signal sampling input channel, a second oscilloscope signal sampling input channel, a third oscilloscope signal sampling input channel, a fourth oscilloscope signal sampling input channel, and a fifth oscilloscope signal sampling input channel connected to an external oscilloscope in series, a first end of each oscilloscope signal sampling input channel is connected to the corresponding voltage terminal VCC / VB, the high level input terminal HIN, the high level output terminal HO, the low level input terminal LIN, and the low level output terminal LO, and a second end of each oscilloscope signal sampling input channel is connected to the ground terminal GND; The HVIC undervoltage protection test circuit also includes a first electrical switch, a second electrical switch, an adjustable DC power supply, a power pin filter capacitor, a first signal generator output port, a second signal generator output port, and a third signal generator output port, wherein a first end of the first electrical switch is connected to a first end of the first oscilloscope signal sampling input channel, a second end of the first electrical switch is respectively connected to a first end of the adjustable DC power supply and a first end of the power pin filter capacitor, and a second end of the adjustable DC power supply and a second end of the power pin filter capacitor are respectively connected to a second end of the first oscilloscope signal sampling input channel; A first end of the second electrical switch is connected to a first end of the first oscilloscope signal sampling input channel, a second end of the second electrical switch is connected to a first end of the first signal generator output port, and a second end of the first signal generator output port is connected to a second end of the first oscilloscope signal sampling input channel; A first end of the second signal generator output port is connected to a first end of the second oscilloscope signal sampling input channel, and a second end of the second signal generator output port is connected to a second end of the second oscilloscope signal sampling input channel; A first end of the third signal generator output port is connected to a first end of the third oscilloscope signal sampling input channel, and a second end of the third signal generator output port is connected to a second end of the third oscilloscope signal sampling input channel.

2. The HVIC undervoltage protection test circuit according to claim 1, characterized in that: The maximum output voltage of the adjustable DC power supply is 20V, and the maximum output current is 0.5A.

3. The HVIC undervoltage protection test circuit according to claim 1, characterized in that: The output voltage range of the output port of the first signal generator is 9V-15V.

4. The HVIC undervoltage protection test circuit according to claim 1, characterized in that: The output voltage range of the second signal generator output port and the third signal generator output port is 0V-5V.

5. A HVIC undervoltage protection test method implemented based on the HVIC undervoltage protection test circuit according to any one of claims 1 to 4, characterized in that: The following steps are involved: S101, determining an undervoltage threshold, a reset voltage, and a maximum delay of an HVIC undervoltage protection circuit to be tested; S102, setting the test temperature; S103, turning off the second electrical switch, closing the first electrical switch, inputting a first pulse to the high level input terminal HIN and the low level input terminal LIN through the adjustable DC power supply, and adjusting the voltage terminal VCC / VB downward from the first preset voltage, and reading the voltage meter reading through an external oscilloscope; S104, when the output voltages of the high level output terminal HO and the low level output terminal LO both jump to a low level, recording the jump power supply voltage as an undervoltage threshold test result; S105, turning off the second electrical switch, closing the first electrical switch, inputting the first pulse to the high level input terminal HIN and the low level input terminal LIN through the adjustable DC power supply, and adjusting the voltage terminal VCC / VB upward from the second preset voltage, and reading the voltage meter reading through the external oscilloscope; S106, when the output voltages of the high level output terminal HO and the low level output terminal LO both jump to the same voltage as the voltage terminal VCC / VB, record the jump power supply voltage as the reset voltage threshold test result; S107, opening the first electrical switch, closing the second electrical switch, inputting a second pulse to the voltage terminal VCC / VB through a signal generator, reading a voltage waveform through the external oscilloscope, and recording a delay time of voltage input and output as a trigger delay test result; S108, comparing the undervoltage threshold test result, the reset voltage threshold test result, and the trigger delay test result with the undervoltage threshold, the reset voltage, and the maximum delay, respectively, to obtain the HVIC undervoltage protection test result of the current test temperature.

6. The HVIC undervoltage protection test method according to claim 5, characterized in that: The HVIC undervoltage protection test method further comprises the steps of: S109, determining the operating temperature of the HVIC undervoltage protection circuit to be tested, changing the current test temperature through the temperature control box, and then returning to step S103.

7. The HVIC undervoltage protection test method according to claim 5, characterized in that: The undervoltage threshold, the reset voltage and the maximum delay are 10V, 10.7V and 20µs respectively; the first pulse is a pulse with a high value of 5V, a low value of 0V and a width greater than 50µs; the second pulse is a pulse with a high value of 15V, a low value of 9V and a width greater than 50µs; the first preset voltage is 15V, and the second preset voltage is 5V.

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