High-accuracy charge pump phase-locked loop mass production test system and test method thereof
By using signal extraction and processing modules in the charge pump phase-locking loop mass production test system, the difference signal is generated to verify the chip locking state, which solves the problem of reduced accuracy in mass production test and achieves high accuracy and reliability. Test results.
Patent Information
- Application Number
- CN202411552028.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-02-07
AI Technical Summary
In the mass production test of chips, relying solely on the lock detection module inside the chip for lock testing often leads to problems such as degradation of accuracy, including other problems of the chip itself that lead to lock detection failure and some chip designs do not consider mass production convenience. Reserve lock detection signal.
Provide a high-accuracy charge pump phase-locked loop mass production test system, including a signal extraction module and a signal processing module, which performs amplification, filtering, difference calculation and integration processing by extracting reference signals and signals to be tested to generate a difference signal To verify that the chip is locked.
It improves the accuracy and reliability of mass production testing, ensuring that only chips with good performance will be judged as qualified, with high system flexibility and stable tests.
Smart Images
Figure CN119395507A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-accuracy charge pump phase-locked loop mass production test system and a test method thereof. Background Art
[0002] Charge Pump Phase-Locked Loop (CPPLL) plays a key role in serial communication and RF wireless transceivers. It is favored by circuit designers because of its advantages such as easy integration, low power consumption, and high performance, as it uses a large number of digital circuits in its circuit structure. However, with the continuous increase in the locking frequency and the frequency of the phase frequency detector (PFD), in the mass production test of the chip, only relying on the lock detection module inside the chip for lock testing often leads to the problem of reduced accuracy. Specifically, it includes at least the following problems of actual non-normal locking:
[0003] 1. Other problems with the chip itself cause the lock detection to fail, and the abnormal chip is mistakenly judged as a normal chip.
[0004] 2. Some chips are designed without considering the convenience of mass production, and no lock detection signal is reserved, so it is impossible to determine whether the lock is normal through the lock detection signal. Summary of the invention
[0005] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to propose a high-accuracy charge pump phase-locked loop mass production test system and a test method thereof, which adopts the following technical solutions:
[0006] In one aspect, the present invention provides a high-accuracy charge pump phase-locked loop mass production test system, comprising:
[0007] A signal extraction module, including a reference loop and a circuit to be tested, extracts a reference signal Vtune1 and a signal to be tested Vtune2 of the reference loop and the circuit to be tested;
[0008] The signal processing module includes a first-stage amplifier circuit, a second-stage amplifier circuit, an integrator circuit, a first subtractor OP3 and a second subtractor OP8. After the reference signal Vtune1 and the signal to be measured Vtune2 are amplified by the first-stage amplifier circuit, a reference gain signal Vt l_bf and a test gain signal Vt l_bf are output. The reference gain signal Vt l_bf and the test gain signal Vt l_bf are connected to the first subtractor OP3 for subtraction operation, and a first difference signal Vdf_vt between the reference signal Vtune1 and the signal to be measured Vtune2 is obtained;
[0009] The reference gain signal Vt l_bf and the test gain signal Vt l_bf are also connected to the second-stage amplifier circuit, and the output reference gain signal 2 and the test gain signal 2 are subjected to noise signal extraction through the integrator circuit, and are subjected to subtraction operation through the second subtractor to obtain a second difference signal Vdf_noise;
[0010] The testing machine is used to read the first difference signal Vdf_vt and verify whether the voltage of the first difference signal Vdf_vt satisfies the first preset range; and is also used to read the second difference signal Vdf_no is and verify whether the voltage of the second difference signal Vdf_no is satisfies the second preset range.
[0011] As a further improvement, the signal extraction module includes a circuit to be tested and a reference circuit, the circuit to be tested includes a chip to be tested, a low-pass filter 1 and a voltage-controlled oscillator 1 connected in series to form a circuit; the reference circuit includes a reference chip, a low-pass filter 2 and a voltage-controlled oscillator 2 connected in series to form a circuit; the chip to be tested and the reference chip both include a frequency detector, a charge pump and a frequency divider; the low-pass filter 1 and the low-pass filter 2 output the reference signal Vtune1 and the signal to be tested Vtune2 respectively.
[0012] As a further improvement, the first-stage amplifier circuit includes a first amplifier OP1 and a second amplifier OP2, and the reference signal Vtune1 and the measured signal Vtune2 are respectively connected to the positive input terminals of the first amplifier OP1 and the second amplifier OP2 through a filter capacitor C1; a first-order low-pass filter is arranged between the first-stage amplifier circuit and the first subtractor OP3.
[0013] As a further improvement, the second-stage amplifier circuit includes a third amplifier OP4 and a fourth amplifier OP5, the reference gain signal Vt l_bf and the test gain signal Vt l_bf are respectively input into the positive input terminals of the third amplifier OP4 and the fourth amplifier OP5, and the output signals of the third amplifier OP4 and the fourth amplifier OP5 are input into the integrator circuit in a capacitive coupling manner.
[0014] As a further improvement, the above-mentioned integrator circuit includes a first integrator OP6 and a second integrator OP7, and diodes are arranged before the positive and negative input ends of the above-mentioned first integrator OP6 and the second integrator OP7, so that the lower half waveforms of the above-mentioned reference gain signal 2 and the test gain signal 2 enter the above-mentioned integrator for integration.
[0015] As a further improvement, the first integrator OP6 and the second integrator OP7 are both provided with switch elements, and the switch elements are closed to discharge the first integrator OP6 and the second integrator OP7.
[0016] As a further improvement, the positive input terminals of the first subtractor OP3 and the second subtractor OP8 are both input with a fixed positive offset voltage.
[0017] The present invention further provides a testing method using the high-accuracy charge pump phase-locked loop mass production testing system having the structure as described above, comprising the following steps:
[0018] S1: close the first integrator OP6 and the second integrator OP7 to discharge the integrators;
[0019] S2: disconnect the first integrator OP6 and the second integrator OP7 to start the integrators;
[0020] S3: After the test time t, the first difference signal Vdf_vt is read by the test machine to verify whether the voltage of the first difference signal Vdf_vt meets the first preset range. If so, proceed to step S4; if not, indicate the chip to be tested as an abnormal chip;
[0021] S4: Read the second difference signal Vdf_no ise and verify whether the voltage of the second difference signal Vdf_no ise satisfies a second preset range. If so, it indicates that the chip under test is a normal chip; if not, it indicates that the chip under test is an abnormal chip.
[0022] Compared with the prior art, the present invention has the following beneficial effects:
[0023] First, the present invention amplifies the extracted reference signal Vtune1 and the signal to be tested Vtune2 through the first stage amplifier circuit, enhances the driving force, generates a reference gain signal Vt l_bf and a test gain signal Vt l_bf, and the reference gain signal Vt l_bf and the test gain signal Vt l_bf enter the first subtractor after filtering to obtain a first difference signal Vdf_vt, which reflects the frequency difference between the reference signal Vtune1 and the signal to be tested Vtune2. By comparing the first difference signal Vdf_vt with the test machine to see if it meets the preset interval, it can be preliminarily determined whether the test chip is locked, thereby improving the test efficiency of mass production, and the system has high flexibility and stable testing.
[0024] Secondly, the present invention inputs the reference gain signal Vt l_bf and the test gain signal Vt l_bf into the second-stage amplifier circuit for further amplification, inputs them into the integrator circuit in a capacitive coupling manner, integrates the waveform of the lower half of the signal using the unidirectional conductivity of the diode, extracts the power of the noise / ripple for analysis, and subtracts the signal outputs of the reference signal and the signal to be tested through a second subtractor, and outputs a second difference signal Vdf_noi se, which reflects the noise difference between the reference signal Vtune1 and the signal to be tested Vtune2. By comparing the second difference signal Vdf_noi se with a preset interval by a test machine, it can be further determined whether the test chip is locked, which helps to improve the accuracy and reliability of mass production testing and ensure that only chips with good performance are judged to be qualified.
[0025] Third, in the present invention, the positive input terminals of the first subtractor OP3 and the second subtractor OP8 are both input with a fixed positive offset voltage, which effectively prevents the negative output of the subtractor from affecting subsequent signal processing, provides a stable reference level, and helps reduce misjudgment during the test process. At the same time, there is no need to increase positive and negative power supplies, making the circuit structure simpler. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0027] Figure 1 It is a schematic diagram of the overall framework structure of the present invention;
[0028] Figure 2 is a circuit flow diagram of the first difference signal Vdf_vt in the present invention;
[0029] Figure 3 4 is a circuit flow diagram of the second difference signal Vdf_noise in the present invention. DETAILED DESCRIPTION
[0030] In order to facilitate understanding by those skilled in the art, the structure of the present invention is further described in detail with reference to the embodiments in conjunction with the accompanying drawings:
[0031] In the description of the present invention, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features, and therefore cannot be understood as limiting the present invention.
[0032] like Figure 1As shown, the present application provides a high-accuracy charge pump phase-locked loop mass production test system and a test method thereof, including a signal extraction module, a signal processing module and a test machine.
[0033] like Figure 1 As shown, the signal extraction module includes a reference loop and a test loop, and the two loops are independent of each other. Specifically, the test loop includes a test chip DUT, a low-pass filter LPF1, and a voltage-controlled oscillator VCO1 connected in series; the reference loop includes a reference chip DRFE, a low-pass filter LPF2, and a voltage-controlled oscillator VCO2 connected in series.
[0034] Generally speaking, the reference chip DRFE is an excellent chip selected in a laboratory environment using a spectrum analyzer and other equipment. These chips and the chip under test DUT include a frequency detector, a charge pump, and a divider (not shown in the figure). The voltage-controlled oscillator VCO1 and the voltage-controlled oscillator VCO2 are low-noise voltage-controlled oscillators with consistent performance parameters.
[0035] The low pass filter 1 LPF1 and the low pass filter 2 LPF2 respectively output a reference signal Vtune1 and a signal to be measured Vtune2 for subsequent processing.
[0036] like Figure 2-Figure 3 As shown, the signal processing module includes a first-stage amplifier circuit, a second-stage amplifier circuit, an integrator circuit, a first subtractor OP3 and a second subtractor OP8.
[0037] like Figure 2 As shown, after the reference signal Vtune1 and the signal to be tested Vtune2 are amplified by the first stage amplifier circuit, a reference gain signal Vt l_bf and a test gain signal Vt l_bf are output. The reference gain signal Vt l_bf and the test gain signal Vt l_bf are connected to the first subtractor OP3 for subtraction operation, and a first difference signal Vdf_vt between the reference signal Vtune1 and the signal to be tested Vtune2 is obtained.
[0038] Specifically, if Figure 2 As shown, the first-stage amplifier circuit includes a first amplifier OP1 and a second amplifier OP2. The reference signal Vtune1 and the measured signal Vtune2 are connected to the positive input terminals of the first amplifier OP1 and the second amplifier OP2 through a filter capacitor C1, respectively. A DC bias is added to the negative input terminals to amplify the signal and enhance the driving capability. In this circuit structure, the filter capacitor C1 is set to filter high-frequency interference and to avoid affecting Figure 1 To take advantage of the characteristics of the mid-loop filter, the capacitance of the filter capacitor C1 should be set small enough.
[0039] Further, combined with Figure 2 and Figure 3 The reference gain signal Vt l_bf output by the first amplifier OP1 is connected to the second stage amplifier circuit on one hand, and connected to the first subtractor through a first-order low-pass filter on the other hand; the test gain signal Vt l_bf output by the second amplifier OP2 is connected to the second stage amplifier circuit on one hand, and connected to the first subtractor through another first-order low-pass filter on the other hand. The two first-order low-pass filters have the same structure and parameters, such as Figure 2 In the circuit structure shown, two resistors R2 and two capacitors C2 respectively form two first-order low-pass filters, and the cut-off frequency of the first-order low-pass filter is set relatively low to obtain the average value of the signal.
[0040] like Figure 2 As shown, the reference gain signal Vt l_bf and the test gain signal Vt l_bf are respectively connected to the first subtractor through a first-order low-pass filter, and the first subtractor performs a subtraction operation on the two signals to obtain a first difference signal Vdf_vt. If the frequency deviation of the reference gain signal Vt l_bf and the test gain signal Vt l_bf is large, a first difference signal Vdf_vt with a large voltage will be generated after subtraction. The first difference signal is input into the test machine to verify whether the voltage of the first difference signal Vdf_vt meets the first preset range. If not, the chip is determined to be an abnormal chip.
[0041] It should be noted that the actual subtractor may generate a negative number after operation, which usually requires the addition of positive and negative power supplies, increasing the complexity of the circuit. Therefore, in this solution, a fixed positive offset voltage is also input to the positive input terminal of the first subtractor OP3, such as Figure 2 As shown, the offset voltage is brought by a T-type resistor network formed by connecting resistors Rx, Ry, and R3 to a power supply VCC and a ground GND. The T-type resistor network is also used to form a DC bias for the negative input terminals of the first amplifier OP1 and the second amplifier OP2.
[0042] Recombination Figure 3 The reference gain signal Vtl_bf and the test gain signal Vtl_bf amplified by the first stage amplifier circuit are further connected to the second stage amplifier circuit. The second stage amplifier circuit further amplifies the reference gain signal Vtl_bf and the test gain signal Vtl_bf. At the same time, since the latter stage amplifier circuit is an asymmetric load, when the amplifier output signal goes in the low voltage direction, the load impedance is relatively small, and when the amplifier output voltage goes in the high direction, the load impedance is relatively large, which will cause the output voltage to be distorted.
[0043] Specifically, the second-stage amplifier circuit includes a third amplifier OP4 and a fourth amplifier OP5, the reference gain signal Vt l_bf and the test gain signal Vt l_bf are respectively input to the positive input terminals of the third amplifier OP4 and the fourth amplifier OP5, the negative input terminals of the third amplifier OP4 and the fourth amplifier OP5 are also increased with a DC bias through a T-type resistor network, and the output signals of the third amplifier OP4 and the fourth amplifier OP5 are input to the integrator circuit in a capacitive coupling manner through the capacitor Cc.
[0044] like Figure 3 As shown, the integrator circuit includes a first integrator OP6 and a second integrator OP7. The reference gain signal 2 output by the third amplifier OP4 is connected to the first integrator OP6 via the capacitor Cc. A diode is provided before the positive and negative input terminals of the first integrator OP6, so that the lower half of the waveform of the reference gain signal 2 enters the integrator for integration. Specifically, Figure 3 As shown, it includes a diode D1, the anode of the diode D1 is connected in series with a current source, the cathode is connected in series with a protection resistor, the reference gain signal 2 is connected to the cathode of the diode D1, the anode of the diode D1 is connected to the negative input end of the first integrator OP6, and the positive input end of the first integrator OP6 is also connected to a diode branch with the same structure. A voltage stabilizing capacitor C3 is also connected in parallel between the diode D1 and the protection resistor.
[0045] In a specific embodiment, the current of the current source is 10 nA, so that the diode D1 is in a critical conduction state.
[0046] It should be pointed out that the second-stage amplifier circuit further amplifies the gain signal Vt l_bf and the test gain signal Vt l_bf. Another purpose is to prevent the integrator circuit from affecting the previous stage circuit when extracting noise / ripple. Because the last stage circuit is an asymmetric load, when the amplifier output signal goes in the direction of low voltage, the load impedance is relatively small. When the output voltage of the amplifier goes in the direction of high voltage, the load impedance is relatively large, which will cause the output voltage to be distorted.
[0047] Similarly, reference Figure 3 The second integrator OP7 integrates the lower half waveform of the test gain signal 2 through the diode in the same manner as the first integrator OP6.
[0048] like Figure 3 As shown, the output signals of the first integrator OP6 and the second integrator OP7 are connected to the second subtractor OP8 for subtraction operation to obtain a second difference signal Vdf_noise, and the second difference signal Vdf_noise is input into the test machine for comparison with the second preset interval.
[0049] Further, similar to the first subtractor OP3, the second subtractor OP8 also adds a fixed forward offset voltage at the positive input terminal. Ideally, the noise content included in the reference gain signal Vt l_bf and the test gain signal Vt l_bf is basically the same, and is basically 0 after subtraction. The voltage of the second difference signal Vdf_noise is determined by the forward offset voltage, that is, determined by the T-type resistor network composed of Rx and Ry and vcc and gnd.
[0050] like Figure 3 As shown, the first integrator OP6 and the second integrator OP7 are both provided with switch elements, and closing the switch elements discharges the first integrator OP6 and the second integrator OP7.
[0051] Specifically, the switch element is connected in parallel to the integration capacitor Ci of the first integrator OP6, including a switch S controlled by the control signal st_b. When the switch S is closed, the integration capacitor Ci is short-circuited and the integrator is discharged. When the switch S is opened, the integrator works normally.
[0052] The bandwidths of the first amplifier OP1, the second amplifier OP2, the third amplifier OP4, the fourth amplifier OP5, the first integrator OP6, the second integrator OP7 and the second subtractor OP8 should all exceed the operating frequency of the phase frequency detector of the phase locked loop.
[0053] In another embodiment, the inputs of the third amplifier OP4 and the fourth amplifier OP5 can also directly input the reference signal Vtune1 and the signal to be measured Vtune2. In this embodiment, the amplifier bandwidth of the first amplifier OP1 and the second amplifier OP2 does not need to meet the requirement that the bandwidth is greater than the frequency of the phase frequency detector, but the loop filter characteristics of the phase-locked loop may be affected due to the large input capacitance of the op amp.
[0054] The present invention further provides a high-accuracy charge pump phase-locked loop mass production test method, comprising the following steps:
[0055] S1: Close the switch to discharge the integrator;
[0056] S2: disconnect the switch, disconnect the switch to start the integrator;
[0057] S3: After the test time t, the first difference signal Vdf_vt is read by the test machine to verify whether the voltage of the first difference signal Vdf_vt meets the first preset range. If so, step S4 is performed; if not, the chip to be tested is indicated as an abnormal chip;
[0058] S4: Read the second difference signal Vdf_noi se and verify whether the voltage of the second difference signal Vdf_noi se satisfies a second preset range. If so, it indicates that the chip under test is a normal chip; if not, it indicates that the chip under test is an abnormal chip.
[0059] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A high-accuracy charge pump phase-locked loop mass production test system, characterized in that: include: A signal extraction module, comprising a reference loop and a circuit to be tested, extracting a reference signal (Vtune1) and a signal to be tested (Vtune2) of the reference loop and the circuit to be tested; A signal processing module, comprising a first-stage amplifier circuit, a second-stage amplifier circuit, an integrator circuit, a first subtractor (OP3) and a second subtractor (OP8); after the reference signal (Vtune1) and the signal to be measured (Vtune2) are amplified by the first-stage amplifier circuit, a reference gain signal 1 (Vtl_bf) and a test gain signal 1 (Vtl_bf) are output; the reference gain signal 1 (Vtl_bf) and the test gain signal 1 (Vtl_bf) are connected to the first subtractor (OP3) for subtraction operation, and a first difference signal (Vdf_vt) between the reference signal (Vtune1) and the signal to be measured (Vtune2) is obtained; The reference gain signal (Vtl_bf) and the test gain signal (Vtl_bf) are also connected to the second-stage amplifier circuit, and the output reference gain signal 2 and the test gain signal 2 are used to extract the noise signal through the integrator circuit, and are subtracted through the second subtractor to obtain a second difference signal (Vdf_noise); A tester, the tester is used to read the first difference signal (Vdf_vt) and verify whether the voltage of the first difference signal (Vdf_vt) meets the first preset range; and is also used to read the second difference signal (Vdf_noise) and verify whether the voltage of the second difference signal (Vdf_noise) meets the second preset range.
2. A high accuracy charge pump phase locked loop mass production test system as claimed in claim 1, characterized in that: The signal extraction module includes a circuit to be tested and a reference circuit. The circuit to be tested includes a chip to be tested, a low-pass filter 1 and a voltage-controlled oscillator 1 connected in series to form a circuit; the reference circuit includes a reference chip, a low-pass filter 2 and a voltage-controlled oscillator 2 connected in series to form a circuit; the chip to be tested and the reference chip both include a frequency detector, a charge pump and a frequency divider; the low-pass filter 1 and the low-pass filter 2 respectively output the reference signal (Vtune1) and the signal to be tested (Vtune2).
3. A high accuracy charge pump phase locked loop mass production test system as claimed in claim 1, characterized in that: The first-stage amplifier circuit comprises a first amplifier (OP1) and a second amplifier (OP2); the reference signal (Vtune1) and the signal to be measured (Vtune2) are respectively connected to the positive input ends of the first amplifier (OP1) and the second amplifier (OP2) via a filter capacitor (C1); and a first-order low-pass filter is provided between the first-stage amplifier circuit and the first subtractor (OP3).
4. A high accuracy charge pump phase locked loop mass production test system as claimed in claim 1, characterized in that: The second-stage amplifier circuit comprises a third amplifier OP4 and a fourth amplifier OP5, the reference gain signal 1 (Vtl_bf) and the test gain signal 1 (Vtl_bf) are respectively input into the positive input ends of the third amplifier (OP4) and the fourth amplifier (OP5), and the output signals of the third amplifier (OP4) and the fourth amplifier (OP5) are input into the integrator circuit in a capacitive coupling manner.
5. A high accuracy charge pump phase locked loop mass production test system as claimed in claim 1, characterized in that: The integrator circuit comprises a first integrator (OP6) and a second integrator (OP7), wherein diodes are arranged before the positive and negative input ends of the first integrator (OP6) and the second integrator (OP7), so that the lower half waveforms of the reference gain signal 2 and the test gain signal 2 enter the integrator for integration.
6. A high-accuracy charge pump phase-locked loop mass production test system as claimed in claim 5, characterized in that: The first integrator (OP6) and the second integrator (OP7) are both provided with a switch element, and closing the switch element discharges the first integrator (OP6) and the second integrator (OP7).
7. A high accuracy charge pump phase locked loop mass production test system as claimed in claim 1, characterized in that: A fixed positive offset voltage is input to the positive input terminals of the first subtractor (OP3) and the second subtractor (OP8).
8. A test method using the high-accuracy charge pump phase-locked loop mass production test system as described in any one of claims 1 to 7, characterized in that: The steps include: S1: close the first integrator (OP6) and the second integrator (OP7) to discharge the integrators; S2: disconnect the first integrator (OP6) and the second integrator (OP7) to start the integrator; S3: After the test time t, the test machine reads the first difference signal (Vdf_vt) to verify whether the voltage of the first difference signal (Vdf_vt) satisfies the first preset range. If so, proceed to step S4; if not, indicate the chip to be tested as an abnormal chip. S4: Read the second difference signal (Vdf_noise) and verify whether the voltage of the second difference signal (Vdf_noise) satisfies a second preset range. If so, it indicates that the chip under test is a normal chip; if not, it indicates that the chip under test is an abnormal chip.