Chip clock frequency control system based on voltage change

Abstract

The invention relates to the technical field of chips, in particular to a chip clock frequency control system based on voltage change, which comprises a delay digital converter, a judgment module, a phase-locked loop and a clock gating module, the judgment module comprises a lookup table, and the lookup table comprises a first DDC output value range [a, b], a first adjustment mode corresponding to the first DDC output value range, a second DDC output value range [b, c], a second adjustment mode corresponding to the second DDC output value range, a third DDC output value range [c, + infinity] and a third adjustment mode corresponding to the third DDC output value range; the clock frequency adjustment amplitudes of the first adjustment mode, the second adjustment mode and the third adjustment mode are sequentially increased; the delay digital converter is connected with the judgment module, the judgment module is respectively connected with the phase-locked loop and the clock gating module, and the phase-locked loop is connected with the clock gating module. According to the invention, the clock frequency of the chip is smoothly and effectively adjusted based on voltage change.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip clock frequency control system based on voltage variation. Background Art

[0002] During the operation of the chip, it is necessary to monitor the voltage in real time and adjust the chip clock frequency based on the voltage change to ensure the normal operation of the chip. However, the voltage value cannot be directly read during the operation of the chip. Usually, a delay to digital converter (DDC) is used to obtain the DDC output value corresponding to each clock cycle in real time. The DDC output value and the chip voltage value have a corresponding mapping relationship. Therefore, the voltage change can be monitored by monitoring the DDC output value, and the chip clock frequency can be adjusted accordingly. In the prior art, when the DDC output value is not within the normal range, the clock gating method is usually used to adjust the chip clock frequency directly, specifically: directly using half clock gating (Half Clock Gating) or full clock gating (Full Clock Gating) to reduce the clock frequency. When the DDC output value returns to normal, the clock is restored by turning off the clock gating. The existing clock frequency adjustment method based on voltage changes has a large adjustment range, and the clock adjustment is not smooth enough, which will cause the chip clock frequency to be unstable. It can be seen from this that how to achieve smooth and effective adjustment of the chip clock frequency based on voltage changes has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The object of the present invention is to provide a chip clock frequency control system based on voltage changes, which can achieve smooth and effective adjustment of the chip clock frequency based on voltage changes.

[0004] The present invention provides a chip clock frequency control system based on voltage change, comprising a delay digital converter, a judgment module, a phase-locked loop and a clock gating module, wherein all modules of the system are modules implemented by hardware; the judgment module comprises a lookup table, wherein the lookup table comprises a first DDC output value range [a, b), a first adjustment mode corresponding to the first DDC output value range, a second DDC output value range [b, c), a second adjustment mode corresponding to the second DDC output value range, a third DDC output value range [c, +∞), and a third adjustment mode corresponding to the third DDC output value range; the clock frequency adjustment amplitudes of the first adjustment mode, the second adjustment mode and the third adjustment mode increase in sequence; the delay digital converter outputs a DDC output value in each clock cycle, and the DDC output value is proportional to the chip voltage;

[0005] Wherein, the delay digital converter is connected to the judgment module, the judgment module is respectively connected to a phase-locked loop and a clock gating module, and the phase-locked loop is connected to the clock gating module;

[0006] The delay digital converter is used to transmit the DDC output value corresponding to the chip voltage output to the judgment module;

[0007] The judgment module is used to determine the target adjustment mode based on the received DDC output value and the lookup table, and if the target adjustment mode is the first adjustment mode, send a first frequency adjustment instruction to the phase-locked loop; if the target adjustment mode is the second adjustment mode, send a second frequency adjustment instruction to the clock gating module; if the target adjustment mode is the third adjustment mode, send a third frequency adjustment instruction to the clock gating module;

[0008] The phase-locked loop is used to generate a first clock frequency. In the case where the first frequency adjustment instruction is not received, the phase-locked loop directly sends the first clock frequency to the clock gating module; in the case where the first frequency adjustment instruction is received, the phase-locked loop adjusts the first clock frequency by adjusting the fractional frequency division parameter of the phase-locked loop, and sends the adjusted first clock frequency to the clock gating module;

[0009] The clock gating module is used to directly transmit the received first clock frequency as the target clock frequency to the chip when the second frequency adjustment instruction and the third frequency adjustment instruction are not received; when the clock gating module receives the second frequency adjustment instruction, it turns on the 1 / 2 clock gating, gates the received first clock frequency by half of the clock, and transmits it to the chip as the target clock frequency; when the clock gating module receives the second frequency adjustment instruction, it turns on the full clock gating, gates all the clocks of the first clock frequency, and transmits them to the chip.

[0010] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the chip clock frequency control system based on voltage change provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0011] The present invention determines different chip clock frequency adjustment modes by setting a judgment module, adjusts the chip clock frequency by combining a phase-locked loop and a clock gating module, and realizes smooth and effective adjustment of the chip clock frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of a chip clock frequency control system based on voltage variation provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0015] The embodiment of the present invention provides a chip clock frequency control system based on voltage variation, such as Figure 1 As shown, it includes a delay digital converter, a judgment module, a phase-locked loop and a clock gating module, and all modules of the system are hardware-implemented modules. The judgment module includes a lookup table, and the lookup table includes a first DDC output value range [a, b), a first adjustment mode corresponding to the first DDC output value range, a second DDC output value range [b, c), a second adjustment mode corresponding to the second DDC output value range, a third DDC output value range [c, +∞), and a third adjustment mode corresponding to the third DDC output value range. It can be understood that a, b, and c are all one of the DDC output values. Under normal circumstances, the chip operates within the preset normal DDC output value range, and the chip frequency does not need to be adjusted. When the DDC output value appears in the first DDC output value range, the second DDC output value range, and the third DDC output value range, the chip frequency needs to be adjusted accordingly. The clock frequency adjustment amplitudes of the first adjustment mode, the second adjustment mode, and the third adjustment mode increase in sequence. The delay digital converter outputs a DDC output value in each clock cycle, and the DDC output value is proportional to the chip voltage.

[0016] The delay digital converter is connected to the judgment module, the judgment module is respectively connected to the phase-locked loop and the clock gating module, and the phase-locked loop is connected to the clock gating module. The delay digital converter is used to output the DDC output value corresponding to the chip voltage and transmit it to the judgment module.

[0017] The judgment module is used to determine the target adjustment mode based on the received DDC output value and the lookup table. If the target adjustment mode is the first adjustment mode, a first frequency adjustment instruction is sent to the phase-locked loop; if the target adjustment mode is the second adjustment mode, a second frequency adjustment instruction is sent to the clock gating module; if the target adjustment mode is the third adjustment mode, a third frequency adjustment instruction is sent to the clock gating module. Based on the DDC output value and the lookup table, a suitable target adjustment mode can be selected according to different chip voltage conditions. The problem is first solved by a small adjustment. If the small adjustment cannot solve the problem, the adjustment range is increased to solve the problem. Avoid large adjustments to the chip frequency that result in uneven chip frequency adjustment.

[0018] The phase-locked loop is used to generate a first clock frequency. If the first frequency adjustment instruction is not received, the phase-locked loop directly sends the first clock frequency to the clock gating module. If the first frequency adjustment instruction is received, the phase-locked loop adjusts the first clock frequency by adjusting the fractional frequency division parameter of the phase-locked loop, and sends the adjusted first clock frequency to the clock gating module. By adjusting the fractional frequency division parameter of the phase-locked loop, the chip clock frequency can be slightly adjusted. In some scenarios, the chip voltage can be restored to normal by directly adjusting the fractional frequency division parameter of the phase-locked loop and slightly adjusting the chip clock frequency.

[0019] The clock gating module is used to directly transmit the received first clock frequency as the target clock frequency to the chip when the second frequency adjustment instruction and the third frequency adjustment instruction are not received; when the clock gating module receives the second frequency adjustment instruction, it turns on the 1 / 2 clock gating, gates the received first clock frequency by half, and transmits it to the chip as the target clock frequency; when the clock gating module receives the second frequency adjustment instruction, it turns on the full clock gating, gates all the clocks of the first clock frequency and transmits it to the chip. It should be noted that when the chip voltage cannot be restored to normal by adjusting the fractional frequency division parameters of the phase-locked loop, the chip clock is adjusted by continuing to increase the 1 / 2 clock gating and full clock gating methods.

[0020] During the operation of the chip, voltage drift may occur due to factors such as load and temperature, resulting in inaccurate DDC output values ​​corresponding to a certain voltage. In order to avoid inaccurate values ​​affecting the stability of clock chip adjustment, the present invention implements the system to select an adjustment mode based on the average value to improve the accuracy and reliability of chip clock adjustment. As an example, the judgment module is specifically used to obtain the DDC output value {D1, D2, ..., D i ,…}, and the DDC output average value corresponding to the first M consecutive clock cycles corresponding to each clock cycle {X M ,XM+1 ,…,X j ,…}, D i is the DDC output value corresponding to the i-th clock cycle, i=1,2,…,X j is the average value of the DDC output corresponding to the first M consecutive clock cycles corresponding to the jth clock cycle, j=M,M+1,….

[0021] If X j Within the first DDC output value range, the judgment module sends a first frequency adjustment instruction to the phase-locked loop in the jth clock cycle. j If X is within the second DDC output value range, the judgment module sends a second frequency adjustment instruction to the clock gating module in the jth clock cycle. j If the third DDC output value is within the range, the judgment module sends a third frequency adjustment instruction to the clock gating module in the jth clock cycle. It should be noted that during the operation of the chip, the chip voltage will be continuously changed due to the influence of various factors, thereby causing the DDC output value to continuously change. Therefore, during the chip clock frequency adjustment process, it is not necessarily executed in the order of the first adjustment mode, the second adjustment mode, and the third adjustment mode, nor is it necessarily executed in all three modes. It is possible to select one or more of them and use them interspersed according to the specific situation of the DDC output value.

[0022] In some cases, the chip voltage can be restored to normal by adjusting the phase-locked loop, or after a certain number of adjustments, the chip voltage continues to drop, so that the DDC output value enters the second DDC output value range. However, in some cases, after multiple adjustments, the DDC output value may still be within the first DDC output value range. On the one hand, frequent adjustments to the phase-locked loop may cause the phase-locked loop to be unstable. On the other hand, the phase-locked loop reduces the clock frequency by too much, which is not conducive to the recovery of the clock frequency. In order to avoid the above situation, as an example, the judgment module also includes a first counter for recording the number of times that X continuously meets the first DDC output value range. j When W reaches the preset first quantity threshold U1, the judgment module stops sending the first frequency adjustment instruction to the phase-locked loop. At this time, the difference between the DDC output value and the normal range is relatively small, and there will be no operation problems. When W reaches the preset second quantity threshold U2, the judgment module sends the second frequency adjustment instruction to the clock gating module, U2>U1, U2>M, the initial value of the first counter is 0, if the value of the first counter in the current clock cycle is not 0, and the X corresponding to the current clock cycle j When the value of the first counter is not within the first DDC output value range, the value of the first counter is set to 0.

[0023] As an example, the judgment module further includes a second counter for recording the number of times that X continuously satisfies the second DDC output value range. j When K reaches a preset third quantity threshold value U3, the judgment module suspends sending the second frequency adjustment instruction to the phase-locked loop. When K reaches a preset fourth quantity threshold value U4, the judgment module sends a third frequency adjustment instruction to the clock gating module. U4>U3, U4>M, the initial value of the second counter is 0. If the value of the first counter in the current clock cycle is not 0, and the X corresponding to the current clock cycle is j When the value of the second counter is not within the second DDC output value range, the value of the second counter is set to 0.

[0024] As an example, the phase-locked loop generates the first clock frequency F based on the following formula:

[0025] F=(FBDIV+FRAC / 2 c )*FREF / DIV

[0026] Wherein, FBDIV is an integer frequency multiplication parameter, FRAC is a fractional frequency division parameter, FREF is a fixed reference clock, c is the number of bits of FRAC, and DIV is an integer frequency division parameter, wherein FBDIV, FREF, c and DIV are fixed parameters, and FRAC is an adjustable parameter. When receiving the first frequency adjustment instruction, the phase-locked loop reduces FRAC by a preset first step length.

[0027] As an example, when the phase-locked loop continuously receives the first frequency adjustment instruction, the phase-locked loop first doubles the preset first step length based on the previous clock cycle, updates the preset first step length, and then reduces FRAC by the preset first step length. When the phase-locked loop does not receive the first frequency adjustment instruction, the preset first step length is restored to the initial value, thereby achieving a gradual increase in the adjustment amplitude in the first adjustment mode, making the chip frequency adjustment smoother.

[0028] During the operation of the chip, due to factors such as load and temperature, voltage drift may occur, resulting in inaccurate DDC output values ​​corresponding to a certain voltage. In order to avoid inaccurate values ​​affecting the exit point selection of the chip frequency adjustment process, as an example, the judgment module is specifically used to store the issuance order of the frequency adjustment instructions. When the DDC output values ​​corresponding to the continuous P clock cycles in the g-th clock cycle are all within the preset normal DDC output range, the corresponding recovery instructions are issued in reverse order according to the issuance order of the frequency adjustment instructions, and the frequency adjustment operation is restored in reverse order. P>M, P <U2,P<U3,g=P,P+1,…。

[0029] As an example, U1 is set to 2, M is set to 8, U2 is set to 40, U3 is set to 2, and U4 is set to 60, but it can be understood that the values ​​of U1, M, U2, U3, and U4 can be flexibly adjusted according to specific scenarios.

[0030] As an example, during the execution of the recovery frequency adjustment operation, the judgment module sends a third frequency recovery instruction to the clock module based on the third frequency adjustment instruction; the clock module performs the following operations based on the third frequency recovery instruction: in the tth adjustment cycle, set every G clock cycles to filter out h t clock cycles; the value range of t is 1 to T, T is the total number of preset recovery adjustment cycles, h1>h2>h3…>h T-1 >h T , if the next recovery instruction corresponding to the third frequency recovery instruction is the second frequency recovery instruction, then h T =G / 2, otherwise, h T =G. The above setting can smoothly restore the clock frequency, avoid voltage mutation caused by instantaneous recovery, and enter the frequency modulation process again.

[0031] As an example, during the recovery frequency adjustment operation, the judgment module sends a second frequency recovery instruction to the clock module based on the second frequency adjustment instruction; the clock module performs the following operations based on the second frequency recovery instruction: closing clock gating, and directly transmitting the received first clock frequency as the target clock frequency to the chip. The above settings further improve the adjustment smoothness of the recovery chip clock.

[0032] As an example, during the recovery frequency adjustment operation, the judgment module sends a first frequency recovery instruction to the phase-locked loop module based on the first frequency adjustment instruction; the phase-locked loop module performs the following operations based on the first frequency recovery instruction: the phase-locked loop increases FRAC by a preset second step length, and the preset second step length is less than or equal to the preset first step length. The above settings further improve the adjustment smoothness of the recovery chip clock.

[0033] The present invention determines different chip clock frequency adjustment modes by setting a judgment module, and adjusts the chip clock frequency by combining a phase-locked loop and a clock gating module, thereby achieving smooth and effective adjustment of the chip clock frequency.

[0034] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A chip clock frequency control system based on voltage variation, characterized in that: The system comprises a delay digital converter, a judgment module, a phase-locked loop and a clock gating module, wherein all modules of the system are hardware-implemented modules; the judgment module comprises a lookup table, wherein the lookup table comprises a first DDC output value range [a, b), a first adjustment mode corresponding to the first DDC output value range, a second DDC output value range [b, c), a second adjustment mode corresponding to the second DDC output value range, a third DDC output value range [c, +∞), and a third adjustment mode corresponding to the third DDC output value range; the clock frequency adjustment amplitudes of the first adjustment mode, the second adjustment mode and the third adjustment mode increase in sequence; the delay digital converter outputs a DDC output value in each clock cycle, and the DDC output value is proportional to the chip voltage; Wherein, the delay digital converter is connected to the judgment module, the judgment module is respectively connected to a phase-locked loop and a clock gating module, and the phase-locked loop is connected to the clock gating module; The delay digital converter is used to transmit the DDC output value corresponding to the chip voltage output to the judgment module; The judgment module is used to determine the target adjustment mode based on the received DDC output value and the lookup table, and if the target adjustment mode is the first adjustment mode, send a first frequency adjustment instruction to the phase-locked loop; if the target adjustment mode is the second adjustment mode, send a second frequency adjustment instruction to the clock gating module; if the target adjustment mode is the third adjustment mode, send a third frequency adjustment instruction to the clock gating module; The phase-locked loop is used to generate a first clock frequency. In the case where the first frequency adjustment instruction is not received, the phase-locked loop directly sends the first clock frequency to the clock gating module; in the case where the first frequency adjustment instruction is received, the phase-locked loop adjusts the first clock frequency by adjusting the fractional frequency division parameter of the phase-locked loop, and sends the adjusted first clock frequency to the clock gating module; The clock gating module is used to directly transmit the received first clock frequency as the target clock frequency to the chip when the second frequency adjustment instruction and the third frequency adjustment instruction are not received; when the clock gating module receives the second frequency adjustment instruction, it turns on the 1 / 2 clock gating, gates the received first clock frequency by half of the clock, and transmits it to the chip as the target clock frequency; when the clock gating module receives the second frequency adjustment instruction, it turns on the full clock gating, gates all the clocks of the first clock frequency, and transmits them to the chip.

2. The system according to claim 1, characterized in that The judgment module is specifically used to obtain the DDC output value {D1, D2, ..., D i ,…}, and the DDC output average value corresponding to the first M consecutive clock cycles corresponding to each clock cycle {X M ,X M+1 ,…,X j ,…}, D i is the DDC output value corresponding to the i-th clock cycle, i=1,2,…,X j is the average value of the DDC output corresponding to the first M consecutive clock cycles corresponding to the jth clock cycle, j = M, M + 1, ...; If X j Within the first DDC output value range, the judgment module sends a first frequency adjustment instruction to the phase-locked loop in the jth clock cycle; if X j Within the second DDC output value range, the judgment module sends a second frequency adjustment instruction to the clock gating module in the jth clock cycle; if X j If the value is within the third DDC output value range, the determination module sends a third frequency adjustment instruction to the clock gating module in the jth clock cycle.

3. The system according to claim 2, characterized in that The judgment module further includes a first counter for recording the X values ​​that continuously meet the first DDC output value range. j When W reaches a preset first quantity threshold value U1, the judgment module stops sending a first frequency adjustment instruction to the phase-locked loop. When W reaches a preset second quantity threshold value U2, the judgment module sends a second frequency adjustment instruction to the clock gating module. U2>U1, U2>M, the initial value of the first counter is 0. If the value of the first counter in the current clock cycle is not 0, and the current clock cycle corresponds to X j When the value of the first counter is not within the first DDC output value range, the value of the first counter is set to 0.

4. The system according to claim 3, characterized in that The judgment module further includes a second counter for recording the X values ​​that continuously meet the second DDC output value range. j When K reaches a preset third quantity threshold value U3, the judgment module suspends sending the second frequency adjustment instruction to the phase-locked loop. When K reaches a preset fourth quantity threshold value U4, the judgment module sends a third frequency adjustment instruction to the clock gating module. U4>U3, U4>M, the initial value of the second counter is 0. If the value of the first counter in the current clock cycle is not 0, and the X corresponding to the current clock cycle is j When the value of the second counter is not within the second DDC output value range, the value of the second counter is set to 0.

5. The system according to claim 1, characterized in that The phase-locked loop generates a first clock frequency F based on the following formula: F=(FBDIV+FRAC / 2 c )*FREF / DIV Among them, FBDIV is the integer frequency multiplication parameter, FRAC is the fractional frequency division parameter, FREF is the fixed reference clock, c is the number of bits of FRAC, and DIV is the integer frequency division parameter. Among them, FBDIV, FREF, c and DIV are fixed parameters, and FRAC is an adjustable parameter; When receiving the first frequency adjustment instruction, the phase-locked loop reduces FRAC by a preset first step length.

6. The system according to claim 5, characterized in that When the phase-locked loop continuously receives the first frequency adjustment instruction, the phase-locked loop first doubles the preset first step length based on the previous clock cycle, updates the preset first step length, and then reduces FRAC by the preset first step length. When the phase-locked loop does not receive the first frequency adjustment instruction, the preset first step length is restored to the initial value.

7. The system according to claim 4, characterized in that The judgment module is further used to store the issuing order of the frequency adjustment instructions. When the DDC output values ​​corresponding to the continuous P clock cycles in the g-th clock cycle are all within the preset normal DDC output range, the corresponding recovery instructions are issued in reverse order according to the issuing order of the frequency adjustment instructions to recover the frequency adjustment operation in reverse order. P>M, P <U2,P<U3,g=P,P+1,…。 8. The system according to claim 7, characterized in that During the frequency recovery operation, the judgment module sends a third frequency recovery instruction to the clock module based on the third frequency adjustment instruction; the clock module performs the following operations based on the third frequency recovery instruction: In the tth adjustment cycle, set to filter out h every G clock cycles t clock cycles; the value range of t is 1 to T, T is the total number of preset recovery adjustment cycles, h1>h2>h3…>h T-1 >h T , if the next recovery instruction corresponding to the third frequency recovery instruction is the second frequency recovery instruction, then h T =G / 2, otherwise, h T =G.

9. The system according to claim 7, characterized in that During the frequency recovery operation, the judgment module sends a second frequency recovery instruction to the clock module based on the second frequency adjustment instruction; the clock module performs the following operations based on the second frequency recovery instruction: The clock gating is turned off, and the received first clock frequency is directly transmitted to the chip as the target clock frequency.

10. The system according to claim 7, characterized in that During the frequency recovery operation, the judgment module sends a first frequency recovery instruction to the phase-locked loop module based on the first frequency adjustment instruction; the phase-locked loop module performs the following operations based on the first frequency recovery instruction: The phase-locked loop increases FRAC by a preset second step length, and the preset second step length is less than or equal to the preset first step length.

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