Circuit output parameter acquisition method, delay calculation method, computer equipment and storage medium
By generating a prediction model of the sample integrated circuit network, the circuit output parameters of the measured integrated circuit network in chip design are quickly calculated, which solves the problem of long calculation time of iterative convergence method and improves design efficiency and accuracy.
Patent Information
- Application Number
- CN202411231138.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-03
- Publication Date
- 2025-02-07
AI Technical Summary
In the timing analysis of chip design, when it is used to calculate the stage delay, at least two rounds of iterative calculations are required, resulting in an increase in calculation time and affecting performance.
By generating a prediction model of the sample integrated circuit network, the circuit output parameters are obtained, and the circuit output parameters of the measured integrated circuit network are quickly calculated, and the delay result is calculated.
It improves the efficiency of obtaining circuit output parameters, reduces the number of iterations, significantly speeds up the iteration process of chip design, and ensures calculation accuracy.
Smart Images
Figure CN119397970A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to a circuit output parameter acquisition method, a delay calculation method, a computer device and a storage medium. Background Art
[0002] In the whole process of chip design, timing analysis plays a vital role. In timing analysis, delay calculation is particularly important. The stage delay corresponding to a circuit includes unit delay and line delay.
[0003] For example, in the CCS scenario, when performing stage delay calculations, an iterative convergence method is usually used to determine the receiving capacitance value of the corresponding unit input pin on the receiving model. The judgment of iterative convergence is based on the relative change percentage of the parameters obtained in the current round of iterations and the parameters obtained in the previous round of iterations. This means that there are at least two rounds of iterative calculations, which increases the calculation time and affects the performance of static timing analysis tools. Therefore, it is necessary to propose a circuit output parameter acquisition method and a delay calculation method to improve efficiency. Summary of the invention
[0004] In response to the above technical problems, the present application provides a circuit output parameter acquisition method, a delay calculation method, a computer device and a storage medium. The circuit output parameters are obtained by a prediction model generated by a sample integrated circuit network, which can improve efficiency and thus speed up the iterative process of chip design.
[0005] In order to solve the above technical problems, the present application provides a method for obtaining circuit output parameters, which includes the following steps: obtaining sample circuit input parameters in a sample integrated circuit network, and sample circuit output parameters in the sample integrated circuit network corresponding to the sample circuit input parameters; wherein the sample circuit input parameters include information associated with the sample circuit output parameters on a sample driving model, and / or a sample network model, and / or a sample receiving model of the sample integrated circuit network, and the sample circuit input parameters are used to predict the sample circuit output parameters; generating a parameter prediction model based on the sample circuit input parameters and the sample circuit output parameters; based on the parameter prediction model, obtaining the circuit output parameters of the integrated circuit network under test according to the circuit input parameters of the integrated circuit network under test.
[0006] In one embodiment, before the step of obtaining sample circuit input parameters in a sample integrated circuit network and sample circuit output parameters in the sample integrated circuit network corresponding to the sample circuit input parameters, the method includes: obtaining the sample driving model, the sample network model, and the sample receiving model of the sample integrated circuit network according to scenario requirement information.
[0007] In one implementation, the sample circuit input parameters include parameter information of an input terminal and / or an output terminal of a unit corresponding to the sample driving model.
[0008] In one embodiment, the parameter information of the input end of the unit corresponding to the sample drive model includes at least one of the slew of the input pin of the unit corresponding to the sample drive model and the time when the input waveform exceeds the delay threshold; and / or the parameter information of the output end of the unit corresponding to the sample drive model includes feature information of the unit corresponding to the sample drive model in a feature library, such as at least one of the description information of the current waveform on the output pin of the corresponding unit in the feature library, the unit delay lookup table, and the unit output slew lookup table.
[0009] In one implementation, the sample circuit input parameters include parasitic parameter information on a parasitic parameter file corresponding to the sample network model, and / or information associated with the parasitic parameter information.
[0010] In one embodiment, the parasitic parameter information includes: distribution information and / or numerical information of at least one of the resistance between nodes, capacitance to ground, and coupling capacitance between lines; and / or information associated with the parasitic parameter information includes: at least one of the fan-out coefficient, total capacitance value, and total resistance value of the sample network model.
[0011] In one implementation, the sample circuit input parameters include parameter information of an input terminal and / or an output terminal of a corresponding unit on the sample receiving model.
[0012] In one embodiment, the parameter information of the input end of the corresponding unit on the sample receiving model includes the nonlinear model capacitance information on the input pin of the corresponding unit on the sample receiving model, and the receiving capacitance information on the input pin of the corresponding unit on the sample receiving model; and / or the parameter information of the output end of the corresponding unit on the sample receiving model includes the parameter information on the associated network on the output pin of the corresponding unit on the sample receiving model, such as network load information.
[0013] The present application also provides a method for obtaining circuit output parameters, the method comprising: obtaining a parameter prediction model; wherein the parameter prediction model is generated based on sample circuit input parameters and sample circuit output parameters in a sample integrated circuit network, and specifically, for example, may be generated through machine learning training; the sample circuit input parameters include information on a sample driving model, and / or a sample network model, and / or a sample receiving model of the sample integrated circuit network, and the sample circuit input parameters are associated with the sample circuit output parameters; based on the parameter prediction model, the circuit output parameters of the integrated circuit network under test are obtained according to the circuit input parameters of the integrated circuit network under test.
[0014] The present application also provides a delay calculation method, comprising: obtaining the circuit output parameters based on the above-mentioned circuit output parameter acquisition method; and obtaining the delay result of the integrated circuit network under test according to the circuit output parameters.
[0015] In one embodiment, based on the circuit output parameters of the tested integrated circuit network, obtaining the delay result of the tested integrated circuit network may include but is not limited to: based on the circuit output parameters of the tested integrated circuit network, these circuit output parameters may not include the delay result, and may only include some intermediate prediction results for calculating the delay result, such as the receiving capacitor on the input pin of the corresponding unit of the receiving model, the equivalent PImodel model corresponding to the network model, etc., and then based on the progressive waveform estimation algorithm (also known as the AWP method), Arnoldi (also known as Arnoldi) and other high-precision methods, based on the circuit output parameters of the above-mentioned tested integrated circuit network, only one iteration is used to obtain the delay result of the tested integrated circuit. This method effectively combines the advantages of machine learning and high-precision algorithms, which not only ensures accuracy but also improves performance.
[0016] The present application also provides a computer device, including a storage medium and a controller, characterized in that a computer program is stored on the storage medium, and the computer program implements the steps of the above method when executed by the controller.
[0017] The present application also provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method described above are implemented.
[0018] The circuit output parameter acquisition method, delay calculation method, computer device and storage medium of the present application include acquiring sample circuit input parameters in a sample integrated circuit network, and sample circuit output parameters corresponding to the sample circuit input parameters in the sample integrated circuit network; wherein the sample circuit input parameters include information associated with the sample circuit output parameters on a sample driving model, and / or a sample network model, and / or a sample receiving model of the sample integrated circuit network; and based on a parameter prediction model generated according to the sample circuit input parameters and the sample circuit output parameters, the circuit output parameters of the integrated circuit network under test are acquired according to the circuit input parameters of the integrated circuit network under test. Therefore, the circuit output parameter acquisition method, delay calculation method, computer device and storage medium of the present application can improve efficiency, thereby speeding up the iterative process of chip design. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a flowchart of a method for obtaining circuit output parameters according to an embodiment.
[0020] Figure 2 It is a structural diagram of a calculation model of stage delay of an integrated circuit network according to an embodiment.
[0021] Figure 3 It is a schematic diagram of the structure of a parasitic parameter network of an integrated circuit network according to an embodiment.
[0022] Figure 4 It is a schematic diagram of a partial structure of an integrated circuit network according to an embodiment.
[0023] Figure 5 It is a schematic diagram of the structure of a fully connected neural network according to an embodiment.
[0024] Figure 6 It is a flowchart of another method for obtaining circuit output parameters according to an embodiment.
[0025] Figure 7 It is a flowchart of a delay calculation method according to an embodiment. DETAILED DESCRIPTION
[0026] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thoroughly understood.
[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items. In the present invention, "each" includes one and more than two quantities.
[0028] Figure 1 FIG. 1 is a flow chart of a method for obtaining circuit output parameters according to an embodiment. Figure 1 The circuit output parameter acquisition method shown can be applied to computer devices, such as computers, mobile phones, servers, etc. The method comprises the following steps:
[0029] S10, obtaining sample circuit input parameters in the sample integrated circuit network, and sample circuit output parameters in the sample integrated circuit network corresponding to the sample circuit input parameters;
[0030] Among them, the integrated circuit network is a circuit network with specific functions that integrates a certain number of common electronic components and the connections between these electronic components through semiconductor technology. The integrated circuit network includes a winding network or an interconnection network. Among them, the interconnection network refers to the metal wires that connect the devices in the integrated circuit network to each other for signal transmission.
[0031] Wherein, the sample circuit input parameter includes information on a sample driving model, and / or a sample network model, and / or a sample receiving model of a sample integrated circuit network, and the sample circuit input parameter is associated with a sample circuit output parameter, and is used to predict the sample circuit output parameter. Wherein, the sample circuit input parameter is associated with a sample circuit output parameter, and is used to predict the sample circuit output parameter means that the sample circuit input parameter is a factor that affects the sample circuit output parameter, for example, the size of the sample circuit input parameter can affect the size of the sample circuit output parameter. In one embodiment, the sample circuit input parameter includes information on a sample driving model, and / or a sample network model, and / or a sample receiving model of a sample integrated circuit network, and the size of the sample circuit output parameter is determined by the type, size, distribution, etc. of the sample circuit input parameter.
[0032] Specifically, the sample circuit input parameters may include, but are not limited to, parameter information of the input and / or output of the unit corresponding to the sample drive model, may include, but are not limited to, parasitic parameter information on the parasitic parameter file corresponding to the sample network model, and may include, but are not limited to, parameter information of the input and / or output of the unit corresponding to the sample receiving model. Specifically, for example, it may be the slew of the input pin of the unit corresponding to the sample drive model (also known as cell in pinslew), the fan-out coefficient of the sample network model, etc. Specifically, the sample circuit input parameters may be obtained by parsing the sample unit corresponding to the sample drive model, the characteristic description in the standard cell library file, such as the slew (also known as slew) lookup table, the delay (also known as delay) lookup table, or by parsing the netlist, the parasitic parameter file (also known as spef), etc., or by calculating the parameters in the standard cell library file or the parasitic parameter file.
[0033] Among them, the sample circuit output parameter is different from the sample circuit input parameter, and includes information associated with the sample circuit input parameter on the sample drive model, and / or the sample network model, and / or the sample receiving model. Specifically, the sample circuit output parameter may include, for example, the receiving capacitance on the input pin of the corresponding unit on the sample receiving model, the unit delay (also known as cell delay) of the sample drive model, the network delay (also known as net delay) of the sample network model, etc. The type of the sample circuit output parameter can be preset according to the system, can also be determined according to the user's input, and can also be determined according to the type of the sample circuit input parameter.
[0034] Specifically, the sample driving model (also known as driver model) is generated by equivalently generating the driving circuit unit in the sample integrated circuit network, for example, it can be a Thevenin equivalent voltage source, a nonlinear current source, etc. The sample network model (also known as network model) is generated by equivalently generating the sample interconnection line network in the sample integrated circuit network. The sample receiving model (also known as receiver model) is generated by equivalently generating the sample receiving unit in the sample integrated circuit network. Specifically, in the calculation scenario of the nonlinear delay model (NLDM), the driving model is a voltage source model with a constant internal resistance, the receiving model is a single capacitor model, and the output voltage is a linear function of time. In the calculation scenario of the composite current source (CCS), the driving model is a nonlinear current source based on time and current, the receiving model consists of two capacitors, and allows the capacitance to be dynamically adjusted during the transition period.
[0035] In one embodiment, if Figure 2 As shown, the driving circuit unit in the sample integrated circuit network is equivalent to generate a sample driving model, the sample interconnection network in the sample integrated circuit network is equivalent to generate a sample network model, and the sample receiving unit in the sample integrated circuit network is equivalent to generate a sample receiving model, wherein the sample driving circuit unit is connected to the sample interconnection network, and the sample interconnection network is connected to the sample receiving unit. Since the sample interconnection network can fan out multiple sample receiving units, there can be multiple sample receiving models. In one embodiment, as Figure 2 As shown, there is only one driving model, only one network model, and three receiving models, but the present application is not limited thereto.
[0036] In one embodiment, before step S10, the step of obtaining sample circuit input parameters in the sample integrated circuit network, and sample circuit output parameters corresponding to the sample circuit input parameters in the sample integrated circuit network, the method includes: obtaining a sample driving model, a sample network model, and a sample receiving model of the sample integrated circuit network according to scenario requirement information. The scenario requirement information may be input by the user according to the requirements, or may be preset by the system, and the scenario requirement information is used to determine the corresponding computing model, so as to determine the corresponding driving model, network model, and receiving model according to the computing model. In one embodiment, the scenario requirement information may be, for example, a computing scenario of NLDM or a computing scenario of CCS. In other embodiments, the scenario requirement information may also be other computing scenarios including at least one of a driving model, a network model, and a receiving model.
[0037] The types of sample circuit input parameters can be determined based on the user's selection instructions, the system's preset information, the output dimension of the parameter prediction model to be generated, such as the neural network model (i.e., the type of the output parameter), the sample circuit output parameters, etc. The number of each sample circuit input parameter can be determined based on, but not limited to, the number of layers of the neuron model in the parameter prediction model, such as the neural network model, and / or the number of neurons in each layer of the neuron model, so as to prevent the number of sample circuit input parameters from being too large, which may lead to overfitting and reduce the generalization ability of the parameter prediction model, and to prevent the number of sample circuit input parameters from being too small, which may lead to underfitting and reduce the acquisition accuracy of the parameter prediction model.
[0038] In one embodiment, the sample circuit input parameter includes parameter information of the input and / or output of the unit corresponding to the sample drive model. Specifically, in one embodiment, the parameter information of the input of the unit corresponding to the sample drive model includes: at least one of the slew of the input pin of the unit corresponding to the sample drive model (also known as cell in pin slew), and the time when the input waveform exceeds the delay threshold (also known as reference time); and / or the parameter information of the output of the unit corresponding to the sample drive model includes the feature information of the unit corresponding to the sample drive model in the feature library, such as the description information of the current waveform on the output pin of the corresponding unit in the feature library, the unit delay lookup table, and the unit output slew lookup table. In other embodiments, the sample circuit input parameter may also be other information associated with the sample drive model.
[0039] In one embodiment, the sample circuit input parameters include parasitic parameter information on a parasitic parameter file of a parasitic parameter network corresponding to the sample network model, and / or information associated with the parasitic parameter information. The information associated with the parasitic parameter information may be information that can be indirectly obtained through the parasitic parameter information, or may be other information that can affect the parasitic parameter information. Figure 3 FIG. 1 is a schematic diagram of a parasitic parameter network of an integrated circuit network according to an embodiment. Figure 3 As shown, the parasitic parameter network includes multiple capacitors and multiple resistors. Specifically, in one embodiment, the parasitic parameter information includes distribution information and / or numerical information of at least one of the resistance between nodes, capacitance to ground, and coupling capacitance between lines; and / or the information associated with the parasitic parameter information includes at least one of the fan-out coefficient, total capacitance value, and total resistance value of the sample network model. The fan-out coefficient is the number of sample receiving models driven by the sample driving model. The larger the fan-out coefficient, the larger the load driven by the sample driving model. Figure 4 As shown, the number of sample receiving models driven by the sample driving model is 3, that is, the fan-out coefficient is 3.
[0040] In one embodiment, the sample circuit input parameter includes parameter information of the input end and / or output end of the corresponding unit on the sample receiving model. Specifically, in one embodiment, the parameter information of the input end of the corresponding unit on the sample receiving model includes the nonlinear model (also known as cell in pin NLDM) capacitance information on the input pin of the corresponding unit on the sample receiving model, the receiving capacitance information on the input pin of the corresponding unit on the sample receiving model; and / or the parameter information of the output end of the corresponding unit on the sample receiving model includes the parameter information on the associated network on the output pin of the corresponding unit on the sample receiving model, such as network load (also known as net load) information, etc. Among them, the receiving capacitance information on the input pin of the corresponding unit on the sample receiving model includes the timing arc level (also known as the Timing arc level) and / or the pin level (also known as the pin level) receiving capacitance information. In other embodiments, the sample circuit input parameter may also include other information on the sample receiving model.
[0041] In one embodiment, S10, obtaining sample circuit input parameters in the sample integrated circuit network, and sample circuit output parameters corresponding to the sample circuit input parameters in the sample integrated circuit network, may include: querying or calculating the sample circuit input parameters according to the standard cell library file or parasitic parameter file of the sample integrated circuit network, and obtaining the associated sample circuit output parameters according to the sample circuit input parameters. In other embodiments, S10, obtaining sample circuit input parameters in the sample integrated circuit network, and sample circuit output parameters corresponding to the sample circuit input parameters in the sample integrated circuit network, may also include: querying or calculating the sample circuit input parameters according to the standard cell library file or parasitic parameter file, and the sample circuit output parameters associated with the sample circuit input parameters. For example, S10 may include: querying the time when the input waveform of the unit input pin corresponding to the sample drive model exceeds the delay threshold, and the unit delay of the sample drive model according to the standard cell library file or parasitic parameter file, determining that the sample circuit input parameter includes the time when the input waveform of the unit input pin corresponding to the sample drive model exceeds the delay threshold, and determining that the sample circuit output parameter includes the unit delay of the sample drive model.
[0042] S11, generating a parameter prediction model according to the sample circuit input parameters and the sample circuit output parameters;
[0043] The parameter prediction model is used to store or obtain the corresponding relationship between the circuit input parameters and the circuit output parameters, for example, a mathematical formula or calculation logic that can obtain the circuit output parameters according to the circuit input parameters. In one embodiment, the parameter prediction model can be a neural network model, for example, a fully connected neural network model, a convolutional neural network (CNN) model, etc. In other embodiments, the parameter prediction model can also be other models that can obtain the circuit output parameters of the tested integrated circuit network according to the circuit input parameters of the tested integrated circuit network.
[0044] Among them, in order to enable the neural network model to obtain more accurate prediction capabilities, the neural network model needs to be trained first. Specifically, firstly, the sample data (i.e., sample circuit input parameters and sample circuit output parameters) are input into the neural network model, and the predicted value (i.e., the circuit output parameter of the integrated circuit network under test) is obtained by forward calculation; the error between the predicted value output by the neural network model and the sample circuit output parameter is calculated by the loss function, and then the parameters of the neural network model are modified by back propagation. When the stopping condition is reached, the training of the neural network model stops. In order to improve the accuracy of the prediction, new sample data (i.e., sample circuit input parameters and sample circuit output parameters) can be continuously provided to train the neural network so that the predicted value of the circuit output parameter of the integrated circuit network under test (i.e., the circuit output parameter of the integrated circuit network under test) is as close to the actual value as possible.
[0045] In one embodiment, in order to improve the accuracy of the prediction model, step S11, generating a parameter prediction model according to the sample circuit input parameters and the sample circuit output parameters, may include: iteratively training the parameter prediction model according to the sample circuit input parameters and the sample circuit output parameters until the parameter prediction model converges. Convergence refers to the process in which the parameters (such as weights and biases, etc.) in the neural network are gradually adjusted through training, so that the performance indicators of the neural network such as loss function and accuracy tend to be stable.
[0046] Among them, the fully connected neural network model is composed of layers of neurons. Figure 5 FIG. 1 is a schematic diagram of a fully connected neural network according to an embodiment. Figure 5As shown, a fully connected neural network may include an input layer, a hidden layer (also known as an intermediate layer), and an output layer. Among them, each neuron receives input information from the previous level, and after weighted summation, it is processed using a nonlinear activation function to obtain an output result. For example, the input layer of the fully connected neural network receives the circuit input parameters of the integrated circuit network under test and outputs the circuit output parameters of the integrated circuit network under test. Among them, the nonlinear activation function gives the linear network nonlinear expression capabilities. If the nonlinear activation function is missing, the superposition of multiple layers of linear neural networks is still a linear network, causing the neural network to lose its ability to describe complex scenarios. Among them, commonly used nonlinear activation functions include sigmod, tanh, ReLU, etc.
[0047] S12. Based on the parameter prediction model, circuit output parameters of the integrated circuit network under test are obtained according to circuit input parameters of the integrated circuit network under test.
[0048] The IC under test is an IC network for which circuit output parameters need to be obtained. The IC network under test can be a circuit network including resistors, capacitors, and transistors, which is input by a user through an input device or automatically generated by a system.
[0049] In order to improve the accuracy of circuit output parameter acquisition, in one embodiment, the circuit input parameters of the tested integrated circuit network can be of the same type as the sample circuit input parameters of the sample integrated circuit network, for example, the slew of the input pin of the unit corresponding to the corresponding driving model or the time when the input waveform exceeds the delay threshold. In one embodiment, the circuit output parameters of the tested integrated circuit network are of the same type as the sample circuit output parameters of the sample integrated circuit network, for example, the receiving capacitance on the input pin of the corresponding unit on the corresponding receiving model, or the unit delay (also called cell delay) in the driving model, or the network delay (also called net delay) in the network model. In other embodiments, at least one of the multiple circuit input parameters of the tested integrated circuit network is of the same type as the sample circuit input parameter of the sample integrated circuit network; and / or at least one of the circuit output parameters of the tested integrated circuit network is of the same type as the sample circuit output parameter of the sample integrated circuit network.
[0050] In one embodiment, the circuit output parameters may not include the delay result, but may only include some intermediate prediction results for calculating the delay result, such as the receiving capacitor on the input pin of the corresponding unit of the receiving model, the equivalent PImodel model corresponding to the network model, etc., and may be based on the asymptotic waveform estimation algorithm (also known as the AWP method), Arnoldi (also known as Arnoldi) and other high-precision methods, based on the circuit output parameters of the above-mentioned integrated circuit network under test, and only one iteration is used to obtain the delay result of the integrated circuit under test. This method effectively combines the advantages of machine learning and high-precision algorithms, ensuring accuracy and improving performance.
[0051] The circuit output parameter acquisition method of the present application can obtain the circuit output parameters of the tested integrated circuit network according to the circuit input parameters of the tested integrated circuit network based on the parameter prediction model generated according to the sample circuit input parameters and the sample circuit output parameters. Therefore, the circuit output parameter acquisition method of the present application can improve efficiency, thereby speeding up the iterative process of chip design. Moreover, in one embodiment, the sample circuit input parameters include information on the sample driving model, and / or the sample network model, and / or the sample receiving model of the sample integrated circuit network, which can be applied to various computing scenarios such as linear delay computing scenarios or non-linear delay computing scenarios, etc., and has good applicability. In addition, in one embodiment, the training and reasoning of the neural network model can be separated, the training process of the neural network model does not take up the reasoning time, and can be trained multiple times with the expansion of sample data, so as to continuously improve the accuracy and efficiency of the neural network model.
[0052] Figure 6 FIG. 1 is a flow chart of another method for obtaining circuit output parameters according to an embodiment. Figure 6 As shown, the circuit output parameter acquisition method of this embodiment can be applied to, but not limited to, terminals such as mobile phones and computers, and the method includes:
[0053] S20, responding to the user's request for obtaining circuit output parameters, and obtaining a parameter prediction model corresponding to the request;
[0054] The acquisition request is information used to trigger the acquisition of circuit output parameters of the integrated circuit network under test. For example, a user may input the acquisition request through an input device such as a keyboard, a mouse, or a microphone.
[0055] The parameter prediction model is generated based on the sample circuit input parameters and sample circuit output parameters in the sample integrated circuit network. The parameter prediction model is used to store or obtain the corresponding relationship between the circuit input parameters and the circuit output parameters, such as a mathematical formula or calculation logic that can obtain the circuit output parameters based on the circuit input parameters. In one embodiment, the parameter prediction model can be a neural network model, such as a fully connected neural network model, a convolutional neural network (CNN) model, etc. In other embodiments, the parameter prediction model can also be other models that can obtain the circuit output parameters of the integrated circuit network under test based on the circuit input parameters of the integrated circuit network under test.
[0056] In order to improve the flexibility of circuit output parameter acquisition, in one embodiment, when a user inputs a circuit output parameter acquisition request in a user interface, if there are multiple parameter prediction models corresponding to the acquisition request, the user interface can display multiple parameter prediction models corresponding to the acquisition request for user selection, and when receiving a user's selection instruction for a parameter prediction model, confirm the parameter prediction model corresponding to the parameter prediction model selection instruction, so as to acquire the circuit output parameter based on the selected parameter prediction model. Among them, the multiple parameter prediction models corresponding to the acquisition request may be different in corresponding input dimensions, input information, prediction accuracy, prediction time, etc. In other embodiments, when a user inputs a circuit output parameter acquisition request in a user interface, if there are multiple circuit input parameters corresponding to the acquisition request, the user interface can display multiple circuit input parameters corresponding to the acquisition request for user selection, and when receiving a user's selection instruction for a circuit input parameter, acquire the corresponding parameter prediction model based on the selected circuit input parameter, so as to acquire the circuit output parameter based on the selected parameter prediction model.
[0057] S21. Based on the parameter prediction model, and according to the circuit input parameters of the integrated circuit network under test, obtain the circuit output parameters of the integrated circuit network under test.
[0058] In one implementation, the execution method of step S21 may refer to the description of step S12 and will not be repeated here.
[0059] The circuit output parameter acquisition method of this embodiment can obtain the circuit output parameters of the tested integrated circuit network based on the parameter prediction model generated according to the sample circuit input parameters and the sample circuit output parameters, according to the circuit input parameters of the tested integrated circuit network. Therefore, the circuit output parameter acquisition method of the present application can improve efficiency, thereby speeding up the iteration process of chip design. Moreover, the sample circuit input parameters of the present application include information on the sample driving model, and / or sample network model, and / or sample receiving model of the sample integrated circuit network, and can be applied to various computing scenarios such as linear delay computing scenarios or non-linear delay computing scenarios, etc., and have good applicability. In addition, the corresponding parameter prediction model and / or circuit input parameters can be selected according to the needs of the user, thereby improving the flexibility of circuit output parameter acquisition.
[0060] In one embodiment, the circuit output parameters of the tested integrated circuit network include the delay result of the tested integrated circuit network and / or the intermediate prediction result for obtaining the delay result. If the circuit output parameters of the tested integrated circuit network do not include the delay result of the tested integrated circuit network, but only include the intermediate prediction result for obtaining the delay result, such as the receiving capacitance on the input pin of the corresponding unit on the receiving model, then according to the above intermediate prediction result, the delay results such as the unit delay, unit output slew, network delay, network slew, etc. in the tested integrated circuit network are calculated by precise calculation or the like.
[0061] Figure 7 FIG. 1 is a flow chart of a delay calculation method according to an embodiment. Figure 7 As shown, the delay calculation method includes:
[0062] S30, acquiring sample circuit input parameters in the sample integrated circuit network, and sample circuit output parameters in the sample integrated circuit network corresponding to the sample circuit input parameters;
[0063] S31, generating a parameter prediction model through machine learning training according to the sample circuit input parameters and the sample circuit output parameters;
[0064] S32, based on the parameter prediction model, according to the circuit input parameters of the integrated circuit network under test, obtaining the circuit output parameters of the integrated circuit network under test;
[0065] S33. Obtain a delay result of the tested integrated circuit network based on the circuit output parameters of the tested integrated circuit network.
[0066] The delay result of the tested integrated circuit network refers to the timing relationship between the input and output of the tested integrated circuit network, for example, it can be the time required for the input to change the output. Specifically, the delay result can include, for example, the results of unit delay, the slew of the unit output pin, the network delay, the slew of the input pin of the corresponding unit of the receiving model, etc.
[0067] In one embodiment, S33, based on the circuit output parameters of the tested integrated circuit network, obtaining the delay result of the tested integrated circuit network may include but is not limited to: based on the circuit output parameters of the tested integrated circuit network, these circuit output parameters may not include the delay result, and may only include some intermediate prediction results for calculating the delay result, such as the receiving capacitor on the input pin of the corresponding unit of the receiving model, the equivalent PImodel model corresponding to the network model, etc., and then based on the progressive waveform estimation algorithm (also known as the AWP method), Arnoldi (also known as Arnoldi) and other high-precision methods, based on the circuit output parameters of the above-mentioned tested integrated circuit network, only one iteration is used to obtain the delay result of the tested integrated circuit. This method effectively combines the advantages of machine learning and high-precision algorithms, which not only ensures accuracy but also improves performance.
[0068] The delay calculation method of this embodiment can obtain the circuit output parameters of the tested integrated circuit network based on the parameter prediction model generated according to the sample circuit input parameters and the sample circuit output parameters, and then obtain the delay result according to the circuit input parameters of the tested integrated circuit network. Therefore, the delay calculation method of this application can improve efficiency, thereby speeding up the iteration process of chip design. Moreover, the sample circuit input parameters of this application include information on the sample drive model, and / or sample network model, and / or sample receiving model of the sample integrated circuit network, which can be applied to various calculation scenarios such as linear delay calculation scenarios or non-linear delay calculation scenarios, and has good applicability.
[0069] The present application also provides a computer device, including a storage medium and a controller, wherein a computer program is stored on the storage medium, and when the computer program is executed by the controller, the steps of the method described above are implemented.
[0070] The present application also provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method described above are implemented.
[0071] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A method for obtaining circuit output parameters, characterized in that: The method comprises the following steps: Acquire sample circuit input parameters in a sample integrated circuit network, and sample circuit output parameters in the sample integrated circuit network corresponding to the sample circuit input parameters; wherein the sample circuit input parameters include information on a sample driving model, and / or a sample network model, and / or a sample receiving model of the sample integrated circuit network, and the sample circuit input parameters are associated with the sample circuit output parameters for predicting the sample circuit output parameters; Generate a parameter prediction model according to the sample circuit input parameters and the sample circuit output parameters; Based on the parameter prediction model, circuit output parameters of the integrated circuit network under test are obtained according to circuit input parameters of the integrated circuit network under test.
2. The method according to claim 1, characterized in that Before the step of obtaining sample circuit input parameters in a sample integrated circuit network and sample circuit output parameters in the sample integrated circuit network corresponding to the sample circuit input parameters, the method includes: According to the scenario requirement information, the sample driving model, the sample network model, and the sample receiving model of the sample integrated circuit network are obtained.
3. The method according to claim 1 or 2, characterized in that: The sample circuit input parameters include parameter information of the input end and / or output end of the unit corresponding to the sample driving model; The parameter information of the input end of the unit corresponding to the sample driving model includes: at least one of the slew of the input pin of the unit corresponding to the sample driving model and the time when the input waveform exceeds the delay threshold; and / or The parameter information of the output end of the unit corresponding to the sample driving model includes feature information of the unit corresponding to the sample driving model in the feature library.
4. The method according to claim 1 or 2, characterized in that: The sample circuit input parameters include parasitic parameter information on a parasitic parameter file corresponding to the sample network model, and / or information associated with the parasitic parameter information; The parasitic parameter information includes: distribution information and / or value information of at least one of resistance between nodes, capacitance to ground, and coupling capacitance between lines; and / or The information associated with the parasitic parameter information includes: at least one of a fan-out coefficient, a total capacitance value, and a total resistance value of the sample network model.
5. The method according to claim 1 or 2, characterized in that: The sample circuit input parameters include parameter information of the input end and / or output end of the corresponding unit on the sample receiving model.
6. The method according to claim 5, characterized in that The parameter information of the input end of the corresponding unit on the sample receiving model includes: nonlinear model capacitance information on the input pin of the corresponding unit on the sample receiving model, receiving capacitance information on the input pin of the corresponding unit on the sample receiving model; and / or The parameter information of the output end of the corresponding unit on the sample receiving model includes parameter information on the associated network on the output pin of the corresponding unit on the sample receiving model.
7. The method according to claim 1, characterized in that The step of obtaining sample circuit input parameters in a sample integrated circuit network and sample circuit output parameters in the sample integrated circuit network corresponding to the sample circuit input parameters comprises: Acquiring the sample circuit input parameters according to the standard cell library file or parasitic parameter file corresponding to the sample integrated circuit network; The sample circuit output parameter is obtained according to the sample circuit input parameter.
8. A delay calculation method, characterized in that: include: Based on the circuit output parameter acquisition method according to any one of claims 1 to 7, acquiring the circuit output parameter; Obtain a delay result of the integrated circuit network under test according to the circuit output parameter.
9. A computer device, comprising a storage medium and a controller, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the controller, the steps of the circuit output parameter acquisition method according to any one of claims 1 to 7 are implemented.
10. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the circuit output parameter acquisition method according to any one of claims 1 to 7 are implemented.