Package structure and manufacturing method thereof

Abstract

The packaging structure comprises a packaging substrate; an interposer module; a packaging cover; and a heat dissipation structure between the interposer module and the package cover, the heat dissipation structure including: a thermal interface material (TIM) layer; and a metal barrier layer between the TIM layer and at least one of the interposer module or the package cover, and configured to suppress formation of an intermetallic compound (IMC) layer. A method of manufacturing a package structure includes: forming a metal barrier layer including Cu (111) on at least one of an interposer module or a package cover; attaching an interposer module; forming a thermal interface material (TIM) layer over the interposer module; and attaching the package cover to the package substrate such that the interposer module, the TIM layer, and the metal barrier layer are disposed between the package cover and the package substrate, and the metal barrier layer contacts the TIM layer. The embodiment of the invention also relates to a method for manufacturing the packaging structure.

Description

Technical Field

[0001] Embodiments of the present application relate to a packaging structure and a method for manufacturing the same. Background Art

[0002] In electronic devices and other semiconductor components, heat may be generated during operation. Effectively dissipating the generated heat can help maintain the performance of the electronic device and prevent overheating. Otherwise, overheating may cause performance degradation or even permanent damage.

[0003] A packaging structure (e.g., a semiconductor package) can sometimes include a thermal interface material (TIM) layer to help dissipate heat generated in the packaging structure. The TIM layer can enhance heat transfer between two surfaces with different thermal characteristics. The TIM layer can be located, for example, between an interposer module (e.g., a packaging module) and a package cover (e.g., a heat sink). The TIM layer can improve thermal contact by filling small gaps and irregularities between the interposer module and the package cover. Summary of the invention

[0004] Some embodiments of the present application provide a packaging structure, including: a packaging substrate; an interposer module located on the packaging substrate; a packaging cover located on the interposer module; and a heat dissipation structure located between the interposer module and the packaging cover, the heat dissipation structure including: a thermal interface material (TIM) layer; and a metal barrier layer located between the thermal interface material layer and at least one of the interposer module or the packaging cover, and configured to inhibit the formation of an intermetallic compound (IMC) layer.

[0005] Some other embodiments of the present application provide a method for manufacturing a packaging structure, the method comprising: forming a metal barrier layer including Cu (111) on at least one of an interposer module or a packaging cover; attaching the interposer module to a packaging substrate; forming a thermal interface material (TIM) layer above the interposer module; and attaching the packaging cover to the packaging substrate above the interposer module, so that the interposer module, the thermal interface material layer and the metal barrier layer are arranged between the packaging cover and the packaging substrate, and the metal barrier layer is in direct contact with the thermal interface material layer.

[0006] Some other embodiments of the present application provide a packaging structure, including: a packaging substrate; an interposer module located on the packaging substrate; a packaging cover located above the interposer module; and a heat dissipation structure located between the interposer module and the packaging cover, the heat dissipation structure including: a thermal interface material (TIM) layer; and a metal barrier layer directly in contact with the thermal interface material layer and including highly textured copper. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1A is a vertical cross-sectional view of a package structure according to one or more embodiments.

[0009] Figure 1B is a plan view (eg, top view) of a package structure according to one or more embodiments.

[0010] Figure 1C is a detailed vertical cross-sectional view of a portion of a package structure according to one or more embodiments.

[0011] Figure 1D is a detailed vertical cross-sectional view of portions of an interposer module metal barrier layer and a package lid metal barrier layer in a package structure according to one or more embodiments.

[0012] Figure 2A is a vertical cross-sectional view of an intermediate structure including a package substrate having a package substrate upper bonding pad and a package substrate lower bonding pad according to one or more embodiments.

[0013] Figure 2B A vertical cross-sectional view of an intermediate structure in which an interposer module may be mounted on a package substrate is shown in accordance with one or more embodiments.

[0014] Figure 2C A vertical cross-sectional view of an intermediate structure including an interposer module during a flux cleaning process (eg, a flux jetting process) is shown according to one or more embodiments.

[0015] Figure 2D A vertical cross-sectional view of an intermediate structure in which a package underfill layer may be formed on a package substrate according to one or more embodiments is illustrated.

[0016] Figure 2E A vertical cross-sectional view of an intermediate structure in which a TIM layer may be formed on (eg, attached to) an interposer module metal barrier layer according to one or more embodiments is shown.

[0017] Figure 2F A vertical cross-sectional view of an intermediate structure is shown in which an adhesive layer may be applied to a package substrate according to one or more embodiments.

[0018] Figure 2G A vertical cross-sectional view of an intermediate structure is shown in which a package cover may be attached to (eg, mounted on) a package substrate according to one or more embodiments.

[0019] Figure 2H A vertical cross-sectional view of an intermediate structure is shown in which a plurality of solder balls c may be formed on a package substrate according to one or more embodiments.

[0020] Figure 3 is a flow chart illustrating a method of manufacturing a package structure according to one or more embodiments.

[0021] Figure 4A is a vertical cross-sectional view of a package structure having a first alternative design according to one or more embodiments.

[0022] Figure 4B is a detailed vertical cross-sectional view of portions of an interposer module metal barrier layer and a package lid metal barrier layer in a package structure having a first alternative design according to one or more embodiments.

[0023] Figure 5A is a vertical cross-sectional view of a package structure having a second alternative design according to one or more embodiments.

[0024] Figure 5B is a detailed vertical cross-sectional view of portions of an interposer module metal barrier layer and a package lid metal barrier layer in a package structure having a second alternative design according to one or more embodiments.

[0025] Figure 6 is a vertical cross-sectional view of a package structure having a third alternative design according to one or more embodiments.

[0026] Fig. 7A is a vertical cross-sectional view of a package structure having a fourth alternative design according to one or more embodiments.

[0027] Figure 7B is a plan view (eg, top view) of a package structure having a fourth alternative design according to one or more embodiments.

[0028] Figure 8 is a flow chart illustrating an alternative method of manufacturing a package structure according to one or more embodiments.

[0029] Fig. 9 is a vertical cross-sectional view of a package structure having a fifth alternative design according to one or more embodiments.

[0030] Fig.10 is a vertical cross-sectional view of a package structure having a sixth alternative design according to one or more embodiments.

[0031] Fig.11 is a vertical cross-sectional view of a package structure having a seventh alternative design according to one or more embodiments.

[0032] Fig.12 is a vertical cross-sectional view of a package structure having an eighth alternative design according to one or more embodiments.

[0033] Fig.13 is a vertical cross-sectional view of a package structure having a ninth alternative design according to one or more embodiments.

[0034] Fig.14 is a vertical cross-sectional view of a package structure having a tenth alternative design according to one or more embodiments.

[0035] Fig.15 is a vertical cross-sectional view of a package structure having an eleventh alternative design according to one or more embodiments. DETAILED DESCRIPTION

[0036] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0037] In addition, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless expressly stated otherwise, each element having the same reference numeral is assumed to be of the same material composition and is assumed to have a thickness within the same thickness range.

[0038] The TIM layer may include, for example, a gel TIM layer. In at least one embodiment, the TIM layer may include a thermal grease or paste, including a mixture of metal particles suspended in a silicone or hydrocarbon-based grease or paste. The TIM layer may include a thermal adhesive, which includes metal particles mixed with an adhesive resin that cures after application. The TIM layer may include a thermal pad, including metal particles or a metal foil or film. The TIM layer may also include a graphite sheet infused with metal. Metal TIM layers including, for example, In, Sn, Ga, and their alloys may be a good choice for heat dissipation due to their excellent thermal conductivity. The TIM layer may include one or more metal materials.

[0039] The metal barrier layer (e.g., metallization layer) on the back side of the interposer module can be used to enhance the adhesion between the metal TIM layer, the interposer module (e.g., semiconductor chip, system on chip (SOC), etc.), and the package cover. However, the formation of an intermetallic compound (IMC) layer between the metal barrier layer and the metal TIM layer may cause Kirkendall voids, which may increase thermal resistance.

[0040] One or more embodiments of the present disclosure may include a packaging structure (e.g., a flip chip multi-chip module (FC-MCM)) including an innovative metal barrier layer on an interposer module (e.g., including semiconductor, silicon, etc.) and a packaging cover of the packaging structure for better heat dissipation. In at least one embodiment, the packaging structure may include a packaging substrate, an interposer module on the packaging substrate, a packaging cover on the interposer module, and a heat dissipation structure between the interposer module and the packaging cover. The heat dissipation structure may include, for example, a thermal interface material (TIM) layer and a metal barrier layer adjacent to the TIM layer and including a textured (e.g., highly textured) structure. In at least one embodiment, the metal barrier layer may include a Cu(111) layer.

[0041] The Cu(111) layer may include a textured structure. The Cu(111) may be referred to as a "textured structure", "textured copper", "highly textured structure" or "highly textured copper". The surface of the Cu(111) may be highly textured (e.g., having a high roughness). However, the roughness of the surface may be modified (e.g., by adjusting the parameters of the plating process) to be close to the roughness of the Cu(100) layer (e.g., a non-textured structure), and the Cu(100) layer may have a higher amount of random copper than the Cu(111) layer.

[0042] A metal barrier layer (e.g., a Cu(111) layer) having a textured structure can provide several advantages and benefits to a packaging structure. In particular, the metal barrier layer can inhibit the interdiffusion of the metallization (e.g., copper) and the metal TIM layer. Therefore, the metallization can inhibit the IMC layer formed at the interface between the metal barrier layer and the metal TIM layer, resulting in fewer Kirkendall voids at the interface. In addition, the metal barrier layer (e.g., a Cu(111) layer) can have a high thermal conductivity. Therefore, a metal barrier layer (e.g., a highly textured Cu(111) layer) having a textured structure can be used to improve the heat dissipation efficiency in a packaging structure.

[0043] In addition, the composition and grain orientation of the textured metal barrier layer (e.g., Cu(111) metallization layer) can be analyzed by electron die sorting (EDS) process and electron backscatter diffraction (EBSD), respectively. In addition, the length, width and thickness of the metal barrier layer can be detected from the microstructure.

[0044] In at least one embodiment, the package structure may include: a package substrate including a ball grid array (BGA); an interposer module (e.g., SOC) located on the package substrate and including a textured metal barrier layer (e.g., a highly textured Cu(111) metallization layer); a package cover attached to the package substrate above the interposer module and including a textured metal barrier layer (e.g., a highly textured Cu(111) metallization layer); an adhesive layer attaching the package cover to the package substrate; a metal TIM layer located between the interposer module and the package cover; a metal interconnect structure (e.g., copper pillars, solder bumps, etc.) connecting the interposer module to the package substrate; and a package bottom fill layer located between the interposer module and the package substrate. In at least one embodiment, the metal barrier layer of the interposer module or the metal barrier layer of the package cover may include a non-textured structure (e.g., a non-textured metallization layer). The non-textured structure may include, for example, a Cu(100) layer.

[0045] It should be noted that the term "textured" (or high textured) may be understood to refer to a structure (e.g., surface) consisting of columnar copper having a (111) orientation. In particular, the term "textured" may refer to a structure in which the amount of columnar grains (e.g., Cu (111) or columnar copper having a (111) orientation) is greater than 95% (preferably greater than 97%). In contrast, the term "non-textured" (or non-high textured) may be understood to refer to a structure (e.g., surface) that includes a significant amount of copper other than Cu (111), such as Cu (100) or randomly arranged copper. In particular, the term "non-textured" may refer to a structure in which the amount of columnar grains (e.g., Cu (111) or columnar copper having a (111) orientation) is 95% or less.

[0046] The package structure may also include one or more memory devices on a package substrate adjacent to the package cap. The memory device may include, for example, a dynamic random access memory (DRAM). The memory device may be mounted on a memory substrate (DRAM substrate) that is attached to the package substrate via a memory solder (DRAM solder, a memory underfill layer (DRAM underfill) between the memory substrate and the package substrate.

[0047] Figure 1A is a vertical cross-sectional view of a package structure 100 according to one or more embodiments. Figure 1B is a plan view (eg, top view) of a package structure 100 according to one or more embodiments. Figure 1A A vertical cross-section along Figure 1B Line A-A' in. Figure 1C is a detailed vertical cross-sectional view of a portion of the package structure 100 according to one or more embodiments. Figure 1D is a detailed vertical cross-sectional view of portions of the interposer module metal barrier layer 151 and the package cap metal barrier layer 152 in the package structure 100 according to one or more embodiments.

[0048] like Figure 1A As shown in , the package structure 100 may include a package substrate 110 and an interposer module 120 on the package substrate 110. The package structure 100 may also include a package cover 130 on the interposer module 120. The package cover 130 may include a package cover foot portion 130a attached to the package substrate 110. The package cover 130 may also include a package cover plate portion 130p connected to the package cover foot portion 130a.

[0049] The package structure 100 may also include a heat dissipation structure 300 between the interposer module 120 and the package cover 130. The heat dissipation structure 300 may include a TIM layer 170 and a metal barrier layer 150 adjacent to the TIM layer 170 and including a textured structure. The metal barrier layer 150 may include an interposer module metal barrier layer 151 between the TIM layer 170 and the interposer module 120 and a package cover metal barrier layer 152 between the package cover 130 and the TIM layer 170. The textured structure may be included on the interposer module metal barrier layer 151 and the package cover metal barrier layer 152. That is, each of the interposer module metal barrier layer 151 and the package cover metal barrier layer 152 may include a textured metal barrier layer. In at least one embodiment, in each of the interposer module metal barrier layer 151 and the package cover metal barrier layer 152, the amount of columnar grains (e.g., Cu (111) or columnar copper with a (111) orientation) may be greater than 95%.

[0050] The package substrate 110 may include a cored or coreless substrate. In at least one embodiment, for example, the package substrate 110 may include a core 112, a package substrate upper dielectric layer 114 formed on the core 112 (e.g., a first side or chip side of the package substrate 110), and a package substrate lower dielectric layer 116 formed on the core 112 (e.g., a second side or board side of the package substrate 110). In particular, the package substrate 110 may include an accumulation film substrate, such as an Ajinomoto accumulation film (ABF) substrate. That is, in at least one embodiment, each of the package substrate upper dielectric layer 114 and the package substrate lower dielectric layer 116 may be described as an ABF layer.

[0051] The core 112 can help provide rigidity to the package substrate 110. The core 112 can include, for example, an epoxy resin, such as bismaleimide triazine epoxy (BT epoxy) and / or a woven glass laminate. The core 112 can alternatively or additionally include an organic material, such as a polymer material. In particular, the core 112 can include a dielectric polymer material, such as a polyimide (PI), a benzocyclobutene (BCB) polymer, or a polybenzobisazole (PBO). Other suitable dielectric materials are within the contemplation of the embodiments of the present disclosure.

[0052] The core 112 may include one or more through holes 112a. The through holes 112a may extend from the lower surface of the core 112 to the upper surface of the core 112. The through holes 112a may allow electrical connection between the upper dielectric layer 114 of the package substrate and the lower dielectric layer 116 of the package substrate. The through holes 112a may include, for example, one or more layers and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the contemplation of the embodiments of the present disclosure.

[0053] The upper dielectric layer 114 of the package substrate may be formed on the upper surface of the core 112. The upper dielectric layer 114 of the package substrate may include a plurality of layers, and in particular, may include an accumulation film (e.g., ABF). The upper dielectric layer 114 of the package substrate may also include an organic material, such as a polymer material. In particular, the upper dielectric layer 114 of the package substrate may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisazole (PBO). Other suitable dielectric materials are within the contemplation of the embodiments of the present disclosure.

[0054] The upper dielectric layer 114 of the package substrate may include one or more upper bonding pads 114a of the package substrate on the chip side surface of the upper dielectric layer 114 of the package substrate. The upper bonding pads 114a of the package substrate may be exposed on the chip side surface of the upper dielectric layer 114 of the package substrate. The upper dielectric layer 114 of the package substrate may also include one or more metal interconnect structures 114b. The metal interconnect structure 114b may electrically couple the upper bonding pads 114a of the package substrate to the through-holes 112a in the core 112. The metal interconnect structure 114b may include a metal layer (e.g., a copper trace) and a metal through-hole connecting the metal layer. The upper bonding pads 114a of the package substrate and the metal interconnect structure 114b may include, for example, one or more layers, and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the contemplation of the embodiments of the present disclosure.

[0055] A package substrate upper passivation layer 110a may be formed on the chip side surface of the package substrate upper dielectric layer 114. The package substrate upper passivation layer 110a may at least partially cover the package substrate upper bonding pad 114a. The upper passivation layer 110a may include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0056] The package substrate lower dielectric layer 116 may be formed on the lower surface of the core 112. The package substrate lower dielectric layer 116 may also include multiple layers, and in particular, may include an accumulation film (e.g., ABF). The package substrate lower dielectric layer 116 may also include an organic material, such as a polymer material. In particular, the package substrate lower dielectric layer 116 may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisazole (PBO). Other suitable dielectric materials are within the contemplation of the embodiments of the present disclosure.

[0057] The package substrate lower dielectric layer 116 may include one or more package substrate lower bonding pads 116a on the board side surface of the package substrate lower dielectric layer 116. The package substrate lower dielectric layer 116 may also include one or more metal interconnect structures 116b. The metal interconnect structure 116b may electrically couple the package substrate lower bonding pad 116a to the through hole 112a in the core 112. The metal interconnect structure 116b may include a metal layer (e.g., a copper trace) and a metal through hole connecting the metal layer. The package substrate lower bonding pad 116a and the metal interconnect structure 116b may include, for example, one or more layers, and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the contemplation of the embodiments of the present disclosure.

[0058] A package substrate lower passivation layer 110b may be formed on the board side surface of the package substrate lower dielectric layer 116. The package substrate lower passivation layer 110b may at least partially cover the package substrate lower bonding pad 116a. The package substrate lower passivation layer 110b may include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0059] A ball grid array (BGA) including a plurality of solder balls 110c may be formed on the board side surface of the package substrate 110. The solder balls 110c may allow the package structure 100 to be securely mounted on a substrate such as a printed circuit board (PCB) and electrically coupled to the PCB substrate. The solder balls 110c may contact the lower bonding pads 116a of the package substrate, respectively. Therefore, the solder balls 110c may be electrically connected to the upper bonding pads 114a of the package substrate through the metal interconnect structure 116b, the through-holes 112a, and the metal interconnect structure 114b. The solder balls 110c of the BGA may be formed on the board side surface of the package substrate 110 in a two-dimensional array. The solder balls 110c may be located, for example, below the package cover foot portion 130a and below the interposer module 120.

[0060] like Figure 1A As shown in , the package substrate 110 may have a width in the x-direction that is greater than the width of the interposer module 120 in the x-direction. The package substrate 110 may also have a length in the y-direction that is greater than the length of the interposer module 120 in the y-direction. The interposer module 120 may be located in a central portion of the package substrate 110. The interposer module 120 may include an interposer 200 and one or more dies 140 (e.g., a semiconductor die, a top die, etc.; see Figure 1B). The interposer module 120 may be attached to the package substrate upper bonding pad 114a in the package substrate 110 via a C4 bump 121. The C4 bump 121 may include a metal post (not shown) and a solder bump (e.g., a SnAg solder bump) on the metal post. The solder bump may collapse to connect the metal post of the C4 bump 121 to the package substrate upper bonding pad 114a.

[0061] A package underfill layer 119 may be formed on the package substrate 110 below and around the interposer module 120. The package underfill layer 119 may also be formed around the C4 bumps 121. The package underfill layer 119 may thereby securely fix the interposer module 120 to the package substrate 110. The package underfill layer 119 may be formed of an epoxy-based polymer material. Other suitable materials may be used for the package underfill layer 119.

[0062] The interposer module 120 is not limited to any particular configuration. The interposer module 120 may include, for example, a flip chip chip-scale package design, a chip-on-wafer-on-substrate design, an integrated fan-out design, etc. In at least one embodiment, the interposer 200 may be omitted from the interposer module 120. In such an embodiment, the die 140 may be directly attached to the package substrate 110.

[0063] The interposer 200 of the interposer module 120 may include an inorganic interposer. The interposer 200 may include a semiconductor material layer 202. In at least one embodiment, the semiconductor material layer 202 may include a silicon-based semiconductor material. The semiconductor material layer 202 may include single crystal silicon or polycrystalline silicon. The semiconductor material layer 202 may be undoped or doped with an electrical dopant, such as a p-type dopant or an n-type dopant.

[0064] The interposer 200 may include a plurality of through-hole cavities 201 in the semiconductor material layer 202. The through-hole cavities 201 may extend through the entire thickness of the semiconductor material layer 202 in the z-direction. The lateral dimensions (such as diameter) of the through-hole cavities 201 may be in a range from 0.5 microns to 10 microns, such as from 1 micron to 6 microns, although smaller or larger lateral dimensions may also be used. In at least one embodiment, the pattern of the array of through-hole cavities 201 may have a two-dimensional periodicity over the interposer 200.

[0065] An insulating liner 203 may be formed in the peripheral portion of the via cavity 201 and on the upper surface of the semiconductor material layer 202. The insulating liner 203 may include, for example, silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials. The insulating liner 203 may have a thickness in the range of from 1% to 20% (such as from 2% to 5%) of the lateral dimension of the via cavity 201.

[0066] A plurality of through silicon vias (TSVs) 204 may be respectively located in the plurality of via cavities 201. The TSVs 204 may include at least one conductive material, such as at least one metal material, in a central portion of the via cavity 201. The TSVs 204 and the front insulating liner 203 may substantially fill the via cavity 201. The TSVs 204 may include, for example, a combination of a metal barrier material (such as TiN, TaN, WN, MoN, TiC, TaC, WC, etc.) and a metal filling material (such as Cu, Co, Ru, Mo, W, etc.). Other suitable metal barrier materials and metal filling materials are within the contemplation of the embodiments of the present disclosure.

[0067] The interposer 200 may also include a lower insulating layer 205 on the bottom surface of the semiconductor material layer 202. The lower insulating layer 205 may connect the insulating liner 203 in the via cavity 201. The lower insulating layer 205 may include a material that is the same as or similar to the material of the insulating liner 203. The lower insulating layer 205 may include, for example, silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, combinations thereof, or other suitable materials.

[0068] The interposer 200 may further include an interposer lower bonding pad 206 on the TSV 204 on the board side surface of the interposer 200. The interposer 200 may further include a lower passivation layer 207 on the board side surface of the interposer 200. The lower passivation layer 207 may at least partially cover the interposer lower bonding pad 206. The C4 bumps 121 may be connected to the interposer lower bonding pads 206 on the board side surface of the interposer 200, respectively. In at least one embodiment, the C4 bumps 121 may include an under bump metallization (UBM) layer on the interposer lower bonding pad 206. The C4 bumps 121 may be at least partially located on the lower insulating layer 205. The lower insulating layer 205 may be used to electrically insulate the C4 bumps 121 from the semiconductor material layer 202.

[0069] The interposer 200 may further include an interposer upper bonding pad 208 on the TSV 204 on the chip side surface of the interposer 200. The interposer 200 may further include an upper passivation layer 209 on the board side surface of the interposer 200. The upper passivation layer 209 may at least partially cover the interposer upper bonding pad 208. The interposer lower bonding pad 206 and the interposer upper bonding pad 208 may be substantially similar to the package substrate lower bonding pad 116a and the package substrate upper bonding pad 114a. The lower passivation layer 207 and the upper passivation layer 209 may be substantially similar to the package substrate lower passivation layer 110b and the package substrate upper passivation layer 110a.

[0070] In at least one embodiment, the interposer module 120 may include a redistribution layer (RDL) structure (not shown) located on the chip side surface of the interposer 200. The RDL structure may include a plurality of polymer layers and a plurality of redistribution layers stacked alternately. The redistribution layer may include a metal, such as copper, aluminum, nickel, titanium, a combination thereof, or other suitable metals. The redistribution layer may include a metal connection structure, i.e., a metal structure that provides electrical connections between nodes in the structure. In at least one embodiment, the redistribution layer may include a plurality of traces (lines) and a plurality of through holes that connect the plurality of traces to each other. The traces may be located on the polymer layer, respectively, and may extend in the x-direction (first horizontal direction) and the y-direction (second horizontal direction) on the upper surface of the polymer layer. The redistribution layer may interconnect the die 140 and / or connect the die 140 to the TSV 204 in the interposer 200.

[0071] The die 140 may be attached to the chip-side surface of the interposer 200 (or, alternatively, to the RDL structure in an embodiment where there is one). In particular, the die 140 may be a flip chip mounted on the upper surface of the interposer 200. That is, the active region of the die 140 may face the interposer 200, and the bulk semiconductor region of the die 140 may be opposite to the active region.

[0072] The die 140 may include a substantially coplanar upper surface 140 a (eg, an upper surface of a bulk semiconductor region). In particular, the upper surfaces 140 a of the die 140 may be located at the same height measured from the upper surface of the upper passivation layer 209 .

[0073] In at least one embodiment, the die 140 may be bonded to the upper interposer bonding pad 208 on the chip side surface of the interposer 200 via microbumps 128. The microbumps 128 may each include a copper rod and a solder bump on the copper rod. In at least one embodiment, the die 140 may include one or more die bonding pads 155 electrically coupled to the active area of ​​the die 140. The microbumps 128 may contact the die bonding pads 155 of the die 140. The die bonding pads 155 may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the contemplation of the embodiments of the present disclosure.

[0074] An interposer module underfill layer 129 may be formed (e.g., individually or collectively) under and around each of the dies 140. The interposer module underfill layer 129 may also be formed around the microbumps 128. The interposer module underfill layer 129 may thereby secure each of the dies 140 to the interposer 200. The interposer module underfill layer 129 may be formed of an epoxy-based polymeric material. Other suitable metal materials are within the contemplation of the embodiments of the present disclosure.

[0075] Instead of utilizing microbumps 128 and interposer module bottom fill layer 129, die 140 may optionally be bonded to interposer 200 by hybrid bonding, which may also be referred to as direct bonding or wafer-to-wafer bonding. Hybrid bonding may include a metal portion and a dielectric portion. In at least one embodiment, hybrid bonding may include metal-metal bonding and oxide-oxide bonding. In particular, hybrid bonding may include bonding between die bonding pad 155 and interposer upper bonding pad 209 and bonding between a dielectric layer (e.g., an oxide layer) on die 140 and a dielectric layer (e.g., an oxide layer) on interposer 200.

[0076] The die 140 may include a first die 141 and a second die 142 adjacent to the first die 141. Each of the dies 140 may include, for example, a single semiconductor die structure, a system-on-chip die, or an integrated system-on-chip die, and may be implemented by a chip-on-wafer-on-substrate technology or an integrated fan-out technology on a substrate. In particular, each of the semiconductor dies 140 may include, for example, a semiconductor chip or chiplet for high-performance computing (HPC) applications, artificial intelligence (AI) applications, and 5G cellular network applications, a logic die (e.g., a mobile application processor, a microcontroller, etc.), or a memory die (e.g., a high-bandwidth memory (HBM) die, a hybrid memory cube (HMC), a dynamic random access memory (DRAM) die, a wide I / O die, an M-RAM die, an R-RAM die, a NAND die, a static random access memory (SRAM), etc.), a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a modern Field Programmable Gate Array (FPGA) chips, networking chips, application specific integrated circuit (ASIC) chips, artificial intelligence / deep neural network (AI / DNN) accelerator chips, etc., coprocessors, accelerators, on-chip memory buffers, high data rate transceiver tube cores, I / O interface tube cores, IPD tube cores, power management tube cores (e.g., power management integrated circuit (PMIC) tube cores), radio frequency (RF) tube cores, sensor tube cores, micro-electromechanical systems (MEMS) tube cores, signal processing tube cores (e.g., digital signal processing (DSP) tube cores), front-end tube cores (e.g., analog front-end (AFE) tube cores), monolithic 3D heterogeneous chiplet stacking tube cores, etc. Other tube cores are within the scope of consideration of the embodiments of the present disclosure. In at least one embodiment, the first tube core 141 may include a main tube core (e.g., a system-on-chip tube core), and the second tube core 142 may include an auxiliary tube core (e.g., a DRAM tube core, an HBM tube core, etc.) that supports the operation of the main tube core.

[0077] The sidewalls of die 140 (eg, die sidewalls) may include one or more metal layers (not shown). The metal layers may include, for example, adhesion layers, diffusion barrier layers, and anti-oxidation layers (eg, layers including gold).

[0078] The interposer module 120 may also include a molding material layer 127 on the interposer 200, on and around the die 140, and between the die 140. The molding material layer 127 may be formed on (e.g., cover) and bonded to one or more of the die sidewalls (e.g., all of the die sidewalls) on the die 140. In at least one embodiment, the die 140 may be substantially "embedded" within the molding material layer 127. The molding material layer 127 may also be formed on and bonded to a surface of an upper passivation layer 209 of the interposer 200 (or RDL structure, if present).

[0079] The upper surface of the molding material layer 127 may be substantially uniform (e.g., flat). The upper surface of the molding material layer 127 may also be substantially coplanar with the upper surface 140a of the die 140. The outer sidewall of the molding material layer 127a may be substantially aligned with the outer sidewall of the interposer 200. In at least one embodiment, the outer sidewall of the interposer module 120 may be at least partially composed of the outer sidewall of the molding material layer 127a and at least partially composed of the outer sidewall of the interposer 200.

[0080] In at least one embodiment, the molding material layer 127 can be formed of a curable material that can be cured to form a hard, solid structure. The molding material layer 127 can include, for example, an epoxy molding compound (EMC). In at least one embodiment, the molding material layer 127 can include a polymeric material, and in particular, an epoxy-based polymeric material. Other suitable molding materials can be used.

[0081] In at least one embodiment, the molding material layer 127 may have a coefficient of thermal expansion (CTE) substantially similar to the CTE of the interposer 200 (e.g., the CTE of silicon). In at least one embodiment, the molding material layer 127 may include an additive material (e.g., a filler material) for improving the properties (e.g., thermal conductivity, CTE, etc.) of the molding material layer 127. The additive material may include, for example, metal powder, metal oxide powder, etc. Other materials in the molding material layer 127 are within the contemplation of the embodiments of the present disclosure.

[0082] The package structure 100 may also include a heat dissipation structure 300 on the interposer module 120 . The heat dissipation structure 300 may include an interposer module metal barrier layer 151 , a TIM layer 170 on the interposer module metal barrier layer 151 , and a package cap metal barrier layer 152 on the TIM layer 170 .

[0083] The interposer module metal barrier 151 may contact the upper surface 140a of the die 140. The interposer module metal barrier 151 may also contact the upper surface of the molding material layer 127. The sidewalls of the interposer module metal barrier 151 may be substantially aligned with the sidewalls 127a of the molding material layer 127 around the entire periphery of the interposer module metal barrier 151. The interposer module metal barrier 151 may include a Cu (111) layer. Other materials such as silver, graphite, etc. may be optionally or additionally included in the interposer module metal barrier 151.

[0084] refer to Figure 1D For example, the interposer module metal barrier layer 151 may have a textured structure (e.g., a Cu (111) layer). The interaction (e.g., reaction) between the interposer module metal barrier layer 151 and the TIM layer 170 may form a lower IMC layer 191 at the interface between the interposer module metal barrier layer 151 and the TIM layer 170. The lower IMC layer 191 may be defined, for example, by a surface 151s of the interposer module metal barrier layer 151 and a lower surface 170s-1 of the TIM layer 170.

[0085] The textured structure of the interposer module metal barrier layer 151 can provide several advantages and benefits to the package structure 100. In particular, the interposer module metal barrier layer 151 can inhibit the interdiffusion of metallization (e.g., copper) and the TIM layer 170 (e.g., metal TIM layer). Therefore, the interposer module metal barrier layer 151 can inhibit the formation of the lower IMC layer 191 at the interface between the interposer module metal barrier layer 151 and the TIM layer 170, resulting in fewer Kirkendall gaps at the interface. The interposer module metal barrier layer 151 can produce fewer Kirkendall gaps by reducing the thickness of the lower IMC layer 191 formed at the interface.

[0086] In addition, the interposer module metal barrier layer 151 (e.g., Cu (111) layer) may have high thermal conductivity. In at least one embodiment, the interposer module metal barrier layer 151 may have a thermal conductivity of 390 W / (m·K) or greater. Therefore, the interposer module metal barrier layer 151 (e.g., highly textured Cu (111)) may be used to improve the heat dissipation efficiency in the package structure 100.

[0087] The TIM layer 170 may be located on the interposer module metal barrier layer 151. The TIM layer 170 may include one or more layers. In at least one embodiment, the center of the TIM layer 170 may be substantially aligned with the center of the interposer module 120 and the center of the interposer module metal barrier layer 151. In at least one embodiment, the TIM layer 170 may extend laterally (e.g., in the xy plane) beyond the outer sidewall of the interposer module metal barrier layer 151 and beyond the outer sidewall 127a of the molding material layer 127.

[0088] TIM layer 170 may have low bulk thermal resistance and high thermal conductivity. TIM layer 170 may cover the entire area of ​​the upper surface of interposer module metal barrier layer 151. TIM layer 170 may be attached to the upper surface of interposer module metal barrier layer 151 by a thermally conductive adhesive.

[0089] In at least one embodiment, the TIM layer 170 may include one or more metals. The TIM layer 170 may include, for example, a low melting point (LMT) metal TIM or a liquid metal TIM. The TIM layer 170 may include one or more metals, such as indium, tin, gallium, silver, etc. The TIM layer 170 may include, for example, a gallium substrate, an indium substrate, a silver substrate, a solder substrate, etc. The solder substrate may include tin and one or more other elements, such as copper, silver, bismuth, indium, zinc, antimony, etc. Other metals in the TIM layer 170 are within the contemplation of the embodiments of the present disclosure.

[0090] The TIM layer 170 may alternatively or additionally include thermal grease, thermal paste, thermal film, thermal adhesive, thermal gap filler, thermal pad (e.g., silicone), thermal tape or gel-type TIM (e.g., cross-linked polymer film). In at least one embodiment, the TIM layer 170 may include graphite, carbon nanotubes (CNT), phase change material (PCM), etc. The PCM may include, for example, a polymer-based PCM. In at least one embodiment, the PCM may change its phase from a solid to a high viscosity semi-liquid at around 60°C. Other materials in the TIM layer 170 are within the contemplation of the embodiments of the present disclosure.

[0091] The package cap metal barrier layer 152 may be located on the upper surface of the TIM layer 170. The package cap metal barrier layer 152 may contact the entire upper surface of the TIM layer 170. The package cap metal barrier layer 152 may extend laterally (eg, in the xy plane) beyond the sidewalls of the TIM layer 170 around the entire periphery of the TIM layer 170.

[0092] The material of the package cover metal barrier layer 152 may be substantially the same as that of the interposer module metal barrier layer 151. The package cover metal barrier layer 152 may include a Cu (111) layer. Other materials such as silver, graphite, etc. may be optionally or additionally included in the package cover metal barrier layer 152.

[0093] The package cover metal barrier layer 152 may also have a textured structure (e.g., a Cu (111) layer). The interaction (e.g., reaction) between the package cover metal barrier layer 152 and the TIM layer 170 may form an upper IMC layer 192 at the interface between the package cover metal barrier layer 152 and the TIM layer 170. The upper IMC layer 192 may be defined, for example, by a surface 152s of the package cover metal barrier layer 152 and an upper surface 170s-2 of the TIM layer 170.

[0094] The textured structure of the package cover metal barrier layer 152 can provide several advantages and benefits for the package structure 100. In particular, the package cover metal barrier layer 152 can inhibit the interdiffusion of metallization (e.g., copper) and the TIM layer 170 (e.g., metal TIM layer). Therefore, the package cover metal barrier layer 152 can inhibit the formation of the upper IMC layer 192 at the interface between the package cover metal barrier layer 152 and the TIM layer 170, resulting in fewer Kirkendall voids at the interface. The package cover metal barrier layer 152 can produce fewer Kirkendall voids by reducing the thickness of the upper IMC layer 192 formed at the interface.

[0095] In addition, the package cover metal barrier layer 152 (e.g., Cu (111) layer) may have high thermal conductivity. In at least one embodiment, the package cover metal barrier layer 152 may have a thermal conductivity of 390 W / (m·K) or greater. Therefore, the package cover metal barrier layer 152 (e.g., highly textured Cu (111)) may be used to improve the heat dissipation efficiency in the package structure 100.

[0096] like Figure 1A As further shown in FIG. 1 , package cover 130 may be located on TIM layer 170 and may provide a cover for interposer module 120 . Package cover 130 may be formed, for example, of a metal, ceramic, or polymer material. Other suitable materials for package cover 130 may be used.

[0097] The package cover foot portion 130a of the package cover 130 can be attached to the package substrate 110. The package cover foot portion 130a can extend from the package cover plate portion 130p in a substantially vertical direction. The package cover foot portion 130a can be connected to the package substrate 110 by an adhesive layer 160. The adhesive layer 160 can include, for example, an epoxy resin adhesive or a silicone adhesive. Other adhesives are within the contemplation of the embodiments of the present disclosure.

[0098] The package cover portion 130p (e.g., the body of the package cover 130) can be connected to the package cover foot portion 130a (e.g., the upper end of the package cover foot portion 130a). In at least one embodiment, the package cover portion 130p can be formed as a unit with the package cover foot portion 130a. The package cover portion 130p can be optionally formed to be separated from the package cover foot portion 130a and attached to the package cover foot portion 130a by an adhesive (not shown). The adhesive can be substantially similar to the adhesive layer 160 described above.

[0099] The package cover portion 130p may have, for example, Figure 1A The package cover portion 130p may be substantially aligned with the outer periphery of the package foot portion 130a. The package cover portion 130p may be substantially parallel to the upper surface of the package substrate 110. The package cover portion 130p may include a central area formed above the interposer module 120. In at least one embodiment, the center point of the central area (in the xy plane) may be substantially aligned with the center point of the interposer module 120 and / or with the center point of the TIM layer 170.

[0100] The package cover portion 130p may include a bottom surface S 130p . Bottom S 130p The bottom surface S may extend across the underside of the package cover portion 130p. 130p The bottom surface S may extend from the package foot portion 130a on one side of the package structure 100 to the package foot portion 130a on the opposite side of the package structure 100. 130p The package cover plate portion 130p may substantially constitute the entire lower side.

[0101] The bottom surface S of the package cover portion 130p 130p The bottom surface S may contact the package cover metal barrier layer 152. 130p The package cover metal barrier layer 152 may directly contact the entire upper surface of the package cover metal barrier layer 152. The package cover metal barrier layer 152 may cover the entire bottom surface S of the package cover plate portion 130p. 130p The package cover metal barrier layer 152 may be bonded to the bottom surface S of the package cover plate portion 130p. 130p The package cover metal barrier layer 152, the TIM layer 170 and the interposer module metal barrier layer 151 may be located on the bottom surface S of the package cover plate portion 130p. 130p and an upper surface of the interposer module 120 .

[0102] Reference again Figure 1B , for ease of understanding, in Figure 1BIn the top view of the package structure 100, the package cover plate portion 130p, the package cover metal barrier layer 152 and the portion of the TIM layer 170 are made transparent. In particular, Figure 1B , the arrangement of the package cover metal barrier layer 152 , the TIM layer 170 , the interposer module metal barrier layer 151 , and the interposer module 120 is shown.

[0103] like Figure 1B As shown in the plan view of FIG. 1 , the package cover 130 may have a width W substantially similar to (eg, slightly smaller than) the width and length of the package substrate 110, respectively. 130 and length L 130 The package cover 130 (eg, the package cover foot portion 130 a ) may be formed around the entire periphery of the interposer module 120 . The package cover 130 may alternatively be formed only around a portion of the interposer module 120 .

[0104] The outer boundary of the package cover metal barrier layer 152 may be aligned with the bottom surface S 130p That is, the area of ​​the package cover metal barrier layer 152 may be the same as the bottom surface S of the package cover plate portion 130p. 130p In addition, the area of ​​the TIM layer 170 may be smaller than the area of ​​the package cover metal barrier layer 152, but larger than the area of ​​the interposer module metal barrier layer 151. The outer boundary of the interposer module metal barrier layer 151 may be coextensive with the outer boundary of the interposer module 120. In other words, the area of ​​the interposer module metal barrier layer 151 may be substantially the same as the area of ​​the interposer module 120.

[0105] In at least one embodiment, the length L of the interposer module metal barrier layer 151 is 151 The length L of the package cover metal barrier layer 152 152 The ratio L 151 / L 152 The length L of the TIM layer 170 may be greater than or equal to zero. 170 The length L of the package cover metal barrier layer 152 152 The ratio L 170 / L 152 may be less than or equal to one (1) and greater than or equal to the ratio L 151 / L 152 (For example, 1 ≥ L 170 / L 152 ≥L 151 / L 152 ≥0).

[0106] In at least one embodiment, the width W of the interposer module metal barrier layer 151 is 151 The width W of the package cover metal barrier layer 152152 The ratio W 151 / W 152 The width W of the TIM layer 170 may be greater than or equal to zero. 170 The width W of the package cover metal barrier layer 152 152 The ratio W 170 / W 152 may be less than or equal to one (1) and greater than or equal to the ratio W 151 / W 152 (For example, 1 ≥ W 170 / W 152 ≥W 151 / W 152 ≥0).

[0107] like Figure 1B As further shown in FIG. 1 , the package substrate 110 may have a substantially rectangular shape with a length in the x-direction greater than a width in the y-direction. The package substrate 110 may optionally have a substantially square shape. Each of the package cover foot portion 130a and the interposer module 120 may have an outer shape substantially the same as the outer shape of the package substrate 110. Other shapes of the package substrate 110, the package cover 130, and the interposer module 120 are within the contemplation of the embodiments of the present disclosure.

[0108] The interposer module 120 may be arranged in the central portion of the package substrate 110 such that the spacing between the interposer module 120 and the package foot portion 130a is substantially uniform around the periphery of the interposer module 120. Figure 1B The package structure 100 is shown as including one (1) first die 141 and four (4) second dies 142 having a specific arrangement, but the number and arrangement of the first die 141 and the second die 142 are not limited to Figure 1B The quantity and arrangement of

[0109] The die 140 may have a substantially rectangular shape or alternatively a substantially square shape. Other shapes of the die 140 are within the contemplated disclosure. The die 140 may have a die length in the x-direction and a die width in the y-direction that is greater than the die length. Figure 1B 140 is shown as including two dies 140 having a specific arrangement, but the number of dies 140 and the arrangement of dies 140 are not limited to Figure 1B The number and arrangement of

[0110] Reference again Figure 1C For ease of understanding, the lower IMC layer 191 and the upper IMC layer 192 are Figure 1C Not shown. Figure 1C As shown in FIG. 1 , the package cover portion 130 p may have a thickness T 130pThe package cover metal barrier layer 152 may have a thickness T 152 , the TIM layer 170 may have a thickness T 170 , and the interposer module metal barrier layer 151 may have a thickness T 151 The thickness T of the package cover portion 130p is 130p The entire package cover portion 130p may be substantially uniform.

[0111] In at least one embodiment, the thickness T of the package cover metal barrier layer 152 is 152 The thickness T of the TIM layer 170 170 The ratio T 152 / T 170 The thickness T of the metal barrier layer 151 of the interposer module may be greater than or equal to zero. 151 The thickness T of the TIM layer 170 170 The ratio T 151 / T 170 may be less than or equal to one (1) and greater than or equal to the ratio T 152 / T 170 (For example, 1 ≥ T 151 / T 170 ≥T 152 / T 170 ≥0). In at least one embodiment, the thickness T of the package cover metal barrier layer 152 is 152 The thickness T of the metal barrier layer 151 of the interposer module may be substantially equal to 151 .

[0112] In at least one embodiment, the thickness T of the TIM layer 170 is 170 The thickness T of the interposer module metal barrier layer 151 may be in the range of 50 μm to 400 μm. 151 The thickness T of the package cover metal barrier layer 152 may be greater than 152 In at least one embodiment, the thickness T of the metal barrier layer 151 of the interposer module is 151 and the thickness T of the package cover metal barrier layer 152 152 Each of the above may be smaller than the thickness T of the TIM layer 170 170 In at least one embodiment, the thickness T of the metal barrier layer 151 of the interposer module is 151 and the thickness T of the package cover metal barrier layer 152 152 Each of may be in the range from 10 μm to 150 μm.

[0113] Reference again Figure 1D, a lower IMC layer 191 is shown at the interface between the surface 151s of the interposer module metal barrier layer 151 and the lower surface 170s-1 of the TIM layer 170. It should be noted that due to the reduced thickness of the lower IMC layer 191, the interface can be substantially free of voids. An upper IMC layer 192 is also shown at the interface between the surface 152s of the package lid metal barrier layer 152 and the upper surface 170s-2 of the TIM layer 170. It should be noted that due to the reduced thickness of the upper IMC layer 192, the interface can also be substantially free of voids.

[0114] The surface 151s of the interposer module metal barrier layer 151 and the surface 152s of the package cover metal barrier layer 152 may have substantially similar configurations. In particular, in each of the surface 151s of the interposer module metal barrier layer 151 and the surface 152s of the package cover metal barrier layer 152, the amount of columnar grains (e.g., Cu (111) or columnar copper having a (111) orientation) may be greater than 95%.

[0115] In at least one embodiment, the surface 151s of the interposer module metal barrier layer 151 and the surface 152s of the package cap metal barrier layer 152 may include a rough surface. In at least one embodiment, the surface 151s of the interposer module metal barrier layer 151 may have a roughness greater than the roughness of the lower surface 170s-1 of the TIM layer 170. In at least one embodiment, the surface 152s of the package cap metal barrier layer 152 may have a roughness greater than the roughness of the upper surface 170s-2 of the TIM layer 170.

[0116] The TIM layer 170 may also be more deformable (e.g., softer, more ductile, etc.) than the interposer module metal barrier layer 151, and more deformable than the package lid metal barrier layer 152. Thus, the shape of the surface 151s of the interposer module metal barrier layer 151 may be imparted to the lower surface 170s-1 of the TIM layer 170, and the shape of the surface 152s of the package lid metal barrier layer 152 may be imparted to the upper surface 170s-2 of the TIM layer 170.

[0117] In at least one embodiment, each of the surface 151s of the interposer module metal barrier layer 151 and the surface 152s of the package cover metal barrier layer 152 may have a roughness Rz of at least 1 μm. In at least one embodiment, the roughness of the surface 151s of the interposer module metal barrier layer 151 may be substantially the same as the roughness of the surface 152s of the package cover metal barrier layer 152. In at least one embodiment, the surface 151s of the interposer module metal barrier layer 151 and the surface 152s of the package cover metal barrier layer 152 may be formed by controlling one or more parameters during the formation of the interposer module metal barrier layer 151 and the package cover metal barrier layer 152. After the surfaces 152s of the interposer module metal barrier layer 151 and the package cover metal barrier layer 152 are formed, the surface 151s may be provided additionally or alternatively by other means. Other means may include, for example, chemical etching, grinding, stamping, etc.

[0118] FIG. 2A to FIG. 2H Various intermediate structures in a method of forming package structure 100 according to one or more embodiments are shown. Figure 2A 1 is a vertical cross-sectional view of an intermediate structure including a package substrate 110 having a package substrate upper bonding pad 114a and a package substrate lower bonding pad 116a according to one or more embodiments. A package substrate 110 including a core 112, a package substrate upper dielectric layer 114, and a package substrate lower dielectric layer 116 may be provided.

[0119] The package substrate upper bonding pad 114a may be formed, for example, on the uppermost dielectric layer of the package substrate upper dielectric layer 114. The package substrate upper bonding pad 114a may be formed to contact the metal interconnect structure 114b. The package substrate upper bonding pad 114a may be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive material) on the upper surface of the package substrate upper dielectric layer 114. The metal layer may then be patterned by etching (e.g., by wet etching, dry etching, etc.) to form the package substrate upper bonding pad 114a. Other suitable metal layer materials and etching processes may be within the contemplation of the embodiments of the present disclosure.

[0120] The package substrate lower bonding pad 116a may be formed, for example, on the lowermost dielectric layer of the package substrate lower dielectric layer 116. The package substrate lower bonding pad 116a may be formed to contact the metal interconnect structure 116b. The package substrate lower bonding pad 116a may be formed in a manner similar to the formation of the package substrate upper bonding pad 114a (e.g., depositing a metal layer, patterning the metal layer by etching, etc.).

[0121] After formation, the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a may optionally undergo a surface roughening treatment (e.g., copper azobenzene (CZ) treatment). In the surface roughening treatment, the surface (e.g., copper surface) of the package substrate upper bonding pad 114a and the surface (e.g., copper surface) of the package substrate lower bonding pad 116a may be etched by an organic acid-based micro-etching solution to create an ultra-rough surface (e.g., copper surface). The unique rough copper surface morphology of the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a may help achieve high copper-to-resin adhesion.

[0122] Then, the package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b may be formed on the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively. In at least one embodiment, the package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b may each include a solder resist layer (e.g., a polymer material), also referred to as a solder mask. The package substrate upper passivation layer 110a may also be referred to as an upper solder resist layer 110a, and the package substrate lower passivation layer 110b may also be referred to as a lower solder resist layer 110b.

[0123] The package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b can be applied simultaneously. The package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b can be applied, for example, as a liquid photoimageable film. The liquid photoimageable film can be applied, for example, by screen printing or spraying the liquid photoimageable film onto the surface of the package substrate 110. The liquid photoimageable film can be applied over the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a. The package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b can optionally be applied as a dry film photoimageable film, which can be vacuum laminated onto the surface of the package substrate 110 and over the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively. The package substrate upper passivation layer 110 a and the package substrate lower passivation layer 110 b may alternatively or additionally be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination or other suitable deposition techniques.

[0124] The package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b may be applied to have a thickness slightly greater than the thickness of the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively. Alternatively, the package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b may be applied to have upper surfaces substantially coplanar with upper surfaces of the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively.

[0125] Then, an opening O may be formed in the upper passivation layer 110a of the package substrate. 110a , so as to expose the upper surface of the upper bonding pad 114a of the package substrate. An opening O may be formed in the lower passivation layer 110b of the package substrate. 110b , to expose the upper surface of the lower bonding pad 116a of the package substrate. 110a and opening O 110b It can be formed, for example, by using a photolithography process. In at least one embodiment, the opening O 110a and opening O 110b It can be formed in different photolithography processes.

[0126] To form the opening O 110a The photolithography process (e.g., process) may include: forming a patterned photoresist mask (not shown) on the upper passivation layer 110a of the package substrate; and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the upper passivation layer 110a of the package substrate through the opening in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0127] To form the opening O 110b The photolithography process (e.g., process) may include: forming a patterned photoresist mask (not shown) on the package substrate lower passivation layer 110b; and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the package substrate lower passivation layer 110b through the opening in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0128] In the opening O 110a The upper passivation layer 110a of the package substrate is formed with an opening O 110b After being formed in the package substrate lower passivation layer 110b, the package substrate upper passivation layer 110a (upper solder resist layer) and the package substrate lower passivation layer 110b (lower solder resist layer) may be cured, such as by thermal curing or ultraviolet (UV) curing.

[0129] Figure 2BA vertical cross-sectional view of an intermediate structure in which an interposer module 120 may be mounted on a package substrate 110 according to one or more embodiments is shown. The interposer module 120 may be formed, for example, in a wafer-level process, in which multiple interposer modules 120 are formed simultaneously and in the same series of steps on one wafer (e.g., a silicon wafer). As part of the wafer-level process, after the molding material layer 127 is formed around the die 140 and cured, a wafer grinding step may be performed on the back side of the wafer including the molding material layer 127. The wafer grinding step may expose the upper surface 140a of the die 140.

[0130] After the wafer grinding step, the wafer may be cleaned and polished. Then, the interposer module metal barrier layer 151 may be formed on the back side of the wafer. The interposer module metal barrier layer 151 may be formed, for example, by an electrochemical plating process (also referred to as ECP or electroplating process). Other methods of forming the interposer module metal barrier layer 151 on the interposer module 120 (e.g., deposition, lamination, etc.) are within the contemplation of the embodiments of the present disclosure.

[0131] In an electrochemical plating process, the silicon wafer may be thoroughly cleaned to remove any contaminants or particles that may interfere with the plating process. A plating solution (e.g., an electrochemical plating solution, an ECP solution, or an electrolyte solution) containing metal ions (e.g., copper ions) is then prepared. During the plating process, the plating solution may allow copper ions to transfer from the anode to the cathode (silicon wafer). It typically contains a metal salt (e.g., a copper salt) dissolved in a suitable solvent. The silicon wafer (cathode) may be connected to the negative terminal of a direct current (DC) power supply. A metal sheet such as copper (e.g., an anode) may be connected to the positive terminal of the power supply. Both the cathode and the anode may be immersed in the plating solution. In an example where the power supply is turned on, metal ions (e.g., copper ions) from the plating solution may be attracted to the silicon wafer (cathode) due to the potential difference. The metal ions may obtain electrons at the cathode and deposit on the silicon wafer to form the interposer module metal barrier layer 151. After achieving the desired thickness of the interposer module metal barrier layer 151, the wafer may be removed from the plating solution, thoroughly rinsed to remove any residual electrolyte, and dried.

[0132] Typically, electrochemical plating processes can be used to form different types of copper, including randomly arranged crystalline copper, copper (111), and amorphous copper, by changing process parameters. In particular, a textured structure (e.g., the interposer module metal barrier layer 151) or a non-textured structure can be formed by changing process parameters, such as additives, the pH value of the plating solution, and the electrochemical plating mode (e.g., DC mode or pulse mode). For example, in order to form a textured structure (e.g., Cu (111)), the electrochemical plating process can utilize a DC mode and a pulse mode, a small amount of additives, and a plating solution with an acidic pH. Alternatively, in order to form a non-textured structure (e.g., Cu (100) or amorphous copper), the electrochemical plating process can utilize a DC mode, a large amount of additives, and a plating solution with an acidic pH.

[0133] In at least one embodiment, the electrochemical plating process for forming the interposer module metal barrier layer 151 may utilize a plating solution including high purity CuSO4, hydrochloric acid, sulfuric acid, and additives. The additives may include, for example, di(3-sulfopropyl) disulfide (SPS), polyethylene glycol (PEG), gelatin, Janus Green B (JGB), mercaptopropanesulfonic acid (MPS), and sodium dodecyl sulfate (SDS). Process parameters in the electrochemical plating process may be set to provide a surface 151s on the interposer module metal barrier layer 151. For example, in order to form the surface 151s (e.g., Cu(111)), the electrochemical plating process may utilize a DC mode and a pulse mode, a small amount of additives, and a plating solution having an acidic pH.

[0134] The surface 151s of the interposer module metal barrier layer 151 may be formed alternatively or additionally by applying a surface roughening treatment (e.g., a CZ treatment). In the surface roughening treatment, the surface 151s (e.g., a copper surface) of the interposer module metal barrier layer 151 may be etched by an organic acid-based micro-etching solution to create an ultra-rough surface. The unique rough copper surface morphology of the interposer module metal barrier layer 151 and the package cover metal barrier layer 152 may help achieve high heat dissipation in the package structure 100.

[0135] After forming the interposer module metal barrier layer 151, a singulation process may be performed to separate the interposer module 120 from the wafer. First, a laser grooving step may be performed on the wafer (e.g., on the interposer module metal barrier layer 151). Then, a dicing saw may be used to singulate each of the independent interposer modules 120 included in the wafer.

[0136] Then, the interposer module 120 can be mounted on the package substrate 110, for example, by a flip chip bonding (FCB) process. The interposer module 120 can be positioned above the package substrate 110, for example, by an electromechanical pick and place (PNP) machine. Then, the C4 bumps 121 (e.g., solder bumps) on the interposer module 120 can be passed through the openings in the upper passivation layer 110a of the package substrate. 110a (See Figure 2A ) is lowered onto the package substrate upper bonding pad 114a. Then, the intermediate structure including the interposer module 120 and the package substrate 110 can be heated to collapse the C4 bump 121 and bond the C4 bump 121 to the package substrate upper bonding pad 114a. In at least one embodiment, laser assisted bonding (LAB) can be used to reflow the C4 bump 121 so that the interposer module 120 can be attached to the package substrate upper bonding pad 114a.

[0137] Figure 2C A vertical cross-sectional view of an intermediate structure including an interposer module 120 in a flux cleaning process (e.g., a flux jetting process) according to one or more embodiments is shown. After the interposer module 120 is attached to the package substrate 110, one or more processes may be used to clean the interposer module metal barrier layer 151 and the package substrate 110 and maintain the surface of the interposer module metal barrier layer 151 and the surface of the package substrate 110. Such processes may include, for example, flux cleaning, pre-baking, and plasma processes.

[0138] like Figure 2C As shown in , in a first flux cleaning process, a flux 510 may be applied to an intermediate structure including an interposer module 120. The flux 510 may be used to clean the upper surface of the interposer module 120 (e.g., the interposer module metal barrier layer 151) and the upper surface of the package substrate 110. The flux 510 may help promote the formation of a joint between the interposer module metal barrier layer 151 and the TIM layer 170 (e.g., a TIM layer including a metal such as indium or gallium). The flux 510 may remove impurities (e.g., oxides) from the surface of the interposer module metal barrier layer 151 and the upper surface of the package substrate 110. The flux 510 may also inhibit reoxidation of the interposer module metal barrier layer 151 during the soldering process and reduce the surface tension and viscosity of the metal (e.g., indium in the TIM layer 170). The flux 510 may also improve the attachment of the package bottom fill layer 119 subsequently formed on the package substrate 110.

[0139] The soldering flux 510 may include, for example, rosin soldering flux, organic acid soldering flux, or inorganic acid soldering flux. Other suitable soldering flux materials are within the contemplation of the embodiments of the present disclosure. The soldering flux may be applied, for example, as a liquid. Figure 2CAs shown in FIG. 1 , a pressurized sprayer 500 may spray liquid solder flux 510 onto an upper surface of the interposer module metal barrier layer 151 and an upper surface of the package substrate 110 .

[0140] Figure 2D 1 shows a vertical cross-sectional view of an intermediate structure in which a package underfill layer 119 may be formed on a package substrate 110 according to one or more embodiments. After performing a cleaning process, the package underfill layer 119 may be formed on the package substrate 110. The package underfill layer 119 is formed by applying a liquid material such as an epoxy-based polymer material to a surface of the package substrate 110. Figure 2C As shown in FIG, a package underfill layer 119 may be formed (e.g., injected) under and around the interposer module 120 and the C4 bumps 121 and on the package substrate 110. The package underfill layer 119 may then be cured, for example, in a box furnace at a temperature in a range of 120° C. to 740° C. for a duration in a range of 60 minutes to 120 minutes to provide the package underfill layer 119 with sufficient stiffness and mechanical strength.

[0141] After curing the package underfill layer 119, a test process (FT1) may be performed to test the intermediate structure (e.g., the interposer module 120 and the package substrate 110). After completing the test process, optional surface mount devices (SMDs) (not shown) such as DRAM devices and multilayer ceramic capacitor (MLCC) devices may be mounted on the surface of the package substrate 110 adjacent to the interposer module 120. In an embodiment, a 3D template may be used to define which area may be covered by solder paste, and the DRAM devices and MLCC devices may be attached to the package substrate 110 via solder bumps (e.g., a reflow process). The process for attaching the DRAM devices and MLCC devices may be substantially similar to the process described above for attaching the interposer module 120 to the package substrate 110.

[0142] After the optional SMD is mounted on the package substrate 110, additional processes may be used to clean the interposer module metal barrier layer 151 and the package substrate 110 and maintain the surface of the interposer module metal barrier layer 151 and the surface of the package substrate 110. Such processes may include, for example, flux cleaning, pre-baking, and plasma processes. In particular, the processes may include the above-mentioned Figure 2C Describe the flux cleaning process.

[0143] Then, the SMD underfill layer can be applied to the package substrate 110 and under and around the SMD. The SMD underfill layer can include a material substantially the same as that of the package underfill layer 119. The SMD underfill layer can also be applied and cured in a manner substantially similar to the above-described application and curing of the package underfill layer 119.

[0144] After curing the optional SMD underfill layer, the package cover 130 may be subjected to one or more pre-treatment processes for preparing the bottom surface S of the package cover plate portion 130p. 130p The pre-treatment process may include, for example, 130p Pre-plasma process to remove impurities.

[0145] Then, the package cover metal barrier layer 152 may be formed on the bottom surface S of the package cover plate portion 130p. 130p The package cover metal barrier layer 152 may be formed on the bottom surface S, for example, by a process similar to the process described above for forming the interposer module metal barrier layer 151 on the interposer module 120 (eg, an electrochemical plating process). 130p superior.

[0146] Other methods of forming the package cover metal barrier layer 152 are within the contemplation of the embodiments of the present disclosure. It should be noted that the package cover metal barrier layer 152 is not necessarily formed after curing the SMD underfill layer, but can be formed on the bottom surface S of the package cover plate portion 130p at any time before attaching the package cover 130 to the package substrate 110. 130p superior.

[0147] Figure 2E 1 shows a vertical cross-sectional view of an intermediate structure in which a TIM layer 170 may be formed on (eg, attached to) an interposer module metal barrier layer 151 according to one or more embodiments. Figure 2E As shown in , the TIM layer 170 may be applied to have a width in the x direction and a length in the y direction that are less than the full width and length of the TIM layer 170 , because pressing the package cover 130 will cause deformation of the TIM layer 170 and lateral expansion of the TIM layer 170 in the x direction and the y direction.

[0148] In at least one embodiment, a thermally conductive adhesive may or may not be applied to the upper surface of the interposer module 120, depending on the type of TIM layer 170 to be used. The material of the TIM layer 170 may be dispensed in the form of a liquid (e.g., grease, gel, paste, etc.) onto the upper surface of the interposer module metal barrier layer 151 (or onto the thermally conductive adhesive, if present). In embodiments where the TIM layer 170 comprises a solid material, the TIM layer 170 may be pressed onto the interposer module metal barrier layer 151, or onto the adhesive, if present.

[0149] After the TIM layer 170 is formed on the interposer module metal barrier layer 151, additional processes may be performed to prepare for attaching the package cap 130 to the package substrate. Such processes may include, for example, flux cleaning, pre-baking, and plasma processes. In particular, the processes may include the above-mentioned Figure 2C Describe the flux cleaning process.

[0150] Figure 2F A vertical cross-sectional view of an intermediate structure in which an adhesive layer 160 can be applied to a packaging substrate 110 according to one or more embodiments is shown. The adhesive layer 160 can be dispensed onto the packaging substrate 110 using a dispensing tool (e.g., an automatic dispensing tool). The dispensing tool can dispense the adhesive layer 160 in a frame shape around the interposer module 120. When applied, the adhesive layer 160 can be rigid enough to form a semi-solid bead on the surface of the packaging substrate 110. In at least one embodiment, the viscosity of the adhesive layer 160 when applied can be 50,000 centipoise (cp) or greater. The shape of the semi-solid bead can remain substantially unchanged between the time it is applied by the dispensing tool and a later time when the packaging cover 130 is attached. The position of the frame shape of the adhesive layer 160 can correspond to the position of the foot portion 130a of the packaging cover 130 (e.g., see Figure 1B ). Pressing the encapsulation cover 130 onto the adhesive layer 160 may cause the adhesive layer 160 to deform.

[0151] Figure 2GA vertical cross-sectional view of an intermediate structure of a package substrate 110 is shown in which a package cap 130 can be attached to (e.g., mounted on) the package substrate 110 according to one or more embodiments. After the package cap metal barrier layer 152 has been formed on the package cap 130, the package cap 130 can be attached to the package substrate 110. In at least one embodiment, the package substrate 110 with the interposer module 120 can be placed on a surface. The package cap 130 can then be positioned above the package substrate 110, for example, by an electromechanical pick and place (PNP) machine. The package cap 130 can then be lowered down above the interposer module 120 and onto the package substrate 110. The foot portion 130a of the package cap 130 can then be aligned with the adhesive layer 160 formed on the package substrate 110.

[0152] Then, by applying downward pressure on the package cover 130, the package cover 130 can be pressed down onto the TIM layer 170 so that the foot portion 130a of the package cover 130 can be attached to the package substrate 110 through the adhesive layer 160. The pressure can also cause the package cover metal barrier layer 152 to contact the TIM layer 170. In at least one embodiment, the pressure can cause the package cover metal barrier layer 152 to compress the TIM layer 170.

[0153] Then, the package cover 130 can be clamped to the package substrate 110 for a period of time sufficient to allow the adhesive layer 160 to cure and form a secure bond between the package substrate 110 and the package cover 130. In at least one embodiment, the adhesive layer 160 is a fast-curing adhesive that can be cured by exposure to ultraviolet (UV) light.

[0154] The clamping of the package cover 130 to the package substrate 110 may be additionally or alternatively implemented, for example, by using a thermal clamping module. The thermal clamping module may apply a uniform force across the upper surface of the package cover 130. In one or more embodiments, the thermal clamping module may apply pressure to the package cover 130. The adhesive layer 160 may be additionally or alternatively cured, for example, in a box furnace, to provide the adhesive layer 160 with sufficient rigidity and mechanical strength.

[0155] Figure 2H FIG. 1 shows a vertical cross-sectional view of an intermediate structure in which a plurality of solder balls 110c may be formed on a package substrate 110 according to one or more embodiments. The plurality of solder balls 110c may pass through openings 100 in a lower passivation layer 110b of the package substrate. 110b (See Figure 2A) is formed on the lower bonding pad 116a of the package substrate. The solder ball 110c can be formed, for example, by an electroplating process. For example, the solder ball 110c can be formed to be located below the foot portion 130a and below the interposer module 120 and between them. A plurality of solder balls 110c can constitute a ball grid array (BGA), which can allow the package structure 100 to be securely mounted (for example, by surface mounting technology (SMT)) on a substrate such as a printed circuit board and electrically coupled to the substrate.

[0156] At this point, one or more optional integrated passive devices (IPDs) (e.g., passive components) may be mounted on the board side surface of the package substrate 110. The optional IPDs may be mounted in a process similar to the mounting process for the SMD described above. In particular, the mounting process may include a solder reflow process for electrically coupling the IPD to the package substrate 110.

[0157] After the optional IPD is mounted on the package substrate 110, additional processes may be used to clean the package substrate 110 and maintain the surface of the package substrate 110. Such processes may include, for example, flux cleaning, pre-baking, and plasma processes. In particular, the processes may include the above-mentioned Figure 2C Describe the flux cleaning process.

[0158] Then, an IPD underfill layer (e.g., a passive component underfill) can be applied to the package substrate 110 and under and around the IPD. The IPD underfill layer can include a material substantially the same as the material of the package underfill layer 119. The IPD underfill layer can also be applied and cured in a manner substantially similar to the application and curing of the package underfill layer 119 described above.

[0159] After curing the optional IPD underfill layer, one or more processes may be performed before final testing (FT2). The process may include, for example, one or more inspections, such as inspection by an optical inspection system (e.g., ICOS, HEXA, etc.) and final visual inspection. These inspections may provide a soundness check of the completed package structure 100 (e.g., checking z height, package appearance, etc.). The final test process may then be performed on the package structure 100.

[0160] Figure 31 is a flow chart illustrating a method of manufacturing a package structure 100 according to one or more embodiments. Step 310 includes forming an interposer module metal barrier layer on the interposer module. Step 320 includes attaching the interposer module to a package substrate. Step 330 includes forming a package cover metal barrier layer on a package cover, wherein at least one of the interposer module metal barrier layer or the package cover metal barrier layer includes a textured structure. Step 340 includes forming a thermal interface material (TIM) layer on the interposer module metal barrier layer. Step 350 includes attaching the package cover to the package substrate over the interposer module.

[0161] The method of manufacturing the package structure 100 is not limited to Figure 3 The steps are listed in the flowchart. In addition, Figure 3 The method shown in is not intended to limit the method to a specific order of steps. For example, forming the package cover metal barrier layer 152 on the package cover 130 in step 330 can occur at any time before attaching the package cover 130 to the package substrate 110. Forming the package cover metal barrier layer 152 on the package cover 130 in step 330 does not necessarily occur after attaching the interposer module 120 to the package substrate 110 and / or forming the TIM layer 170 on the interposer module metal barrier layer 151.

[0162] FIG. 4A to FIG. 4B is a diagram of a package structure 100 having a first optional design according to one or more embodiments. In particular, Figure 4A is a vertical cross-sectional view of a package structure 100 having a first alternative design according to one or more embodiments. Figure 4B is a detailed vertical cross-sectional view of portions of an interposer module metal barrier layer 151 and a package cap metal barrier layer 152 in a package structure 100 having a first alternative design according to one or more embodiments.

[0163] like Figure 4A As shown in , a first alternative design can be substantially similar to Figure 1A and Figure 1D In particular, the interaction (e.g., reaction) between the package cover metal barrier layer 152 (e.g., Cu (111)) and the TIM layer 170 may cause the formation of an upper IMC layer 192 at the interface between the package cover metal barrier layer 152 and the TIM layer 170. The upper IMC layer 192 may be defined, for example, by a surface 152s of the package cover metal barrier layer 152 and an upper surface 170s-2 of the TIM layer 170.

[0164] However, in a first alternative design, the interposer module metal barrier layer 151 may be Figure 1A The metal barrier layer 151 of the interposer module in the original design is different. Figure 4BAs shown in more detail in FIG. 4 , the interposer module metal barrier layer 151 in the first alternative design may include a non-textured metal barrier layer having a surface 451s. In at least one embodiment, the interposer module metal barrier layer 151 may include Cu(100).

[0165] The interaction (e.g., reaction) between the interposer module metal barrier layer 151 (e.g., Cu (100)) and the TIM layer 170 may cause the formation of a lower IMC layer 491 at the interface between the interposer module metal barrier layer 151 and the TIM layer 170. The lower IMC layer 491 may be defined, for example, by a surface 451s of the interposer module metal barrier layer 151 and a lower surface 470s-1 of the TIM layer 170. Figure 4B As shown in , the thickness of the lower IMC layer 491 may be greater than the thickness of the upper IMC layer 192 .

[0166] In at least one embodiment, the surface 451s may be less textured than the surface 152s of the package cap metal barrier layer 152. In at least one embodiment, the surface 451s may have a roughness less than the roughness of the surface 152s of the package cap metal barrier layer 152. In at least one embodiment, the surface 451s may have a roughness Rz less than 1 μm.

[0167] In at least one embodiment, the interposer module metal barrier layer 151 may include a Cu(111) layer. In such an embodiment, the surface 451s may include a surface of the Cu(111) layer. The surface 451s may include a significant amount of copper other than Cu(111), such as randomly arranged copper. In particular, the amount of columnar grains (e.g., Cu(111) or columnar copper with a (111) orientation) in the surface 451s may be 95% or less.

[0168] The surface 451s may be provided, for example, by controlling one or more process parameters in forming the interposer module metal barrier layer 151. In at least one embodiment, the surface 451s may be formed by an electrochemical plating process using a DC mode, a large amount of additives, and a plating solution having an acidic pH. The surface 451s of the interposer module metal barrier layer 151 may be formed, alternatively or additionally, by processing (e.g., by chemical mechanical polishing (CMP)) the surface 451s after forming the interposer module metal barrier layer 151.

[0169] The CMP process can be applied not only to the Cu(100) layer but also to the Cu(111) layer. Such a process can reduce the roughness of the surface of those copper layers, and because the surface area is reduced, the formation of the IMC layer at the surface can be suppressed, so that the thickness of the IMC layer is reduced.

[0170] FIG. 5A to FIG. 5B is a view of a package structure 100 having a second alternative design according to one or more embodiments. In particular, Figure 5A is a vertical cross-sectional view of a package structure 100 having a second alternative design according to one or more embodiments. Figure 5B is a detailed vertical cross-sectional view of portions of an interposer module metal barrier layer 151 and a package cap metal barrier layer 152 in a package structure 100 having a second alternative design according to one or more embodiments.

[0171] like Figure 5A As shown in , the second alternative design can be basically similar to Figure 1A In particular, the interaction (e.g., reaction) between the interposer module metal barrier layer 151 (e.g., Cu (111)) and the TIM layer 170 may result in the formation of a lower IMC layer 191 at the interface between the interposer module metal barrier layer 151 and the TIM layer 170. The lower IMC layer 191 may be defined, for example, by a surface 151s of the interposer module metal barrier layer 151 and a lower surface 170s-1 of the TIM layer 170.

[0172] However, in a second alternative design, the package cover metal barrier layer 152 may be Figure 1A The package cover metal barrier layer 152 in the original design is different. Figure 5B As shown in more detail in FIG. 4 , the package lid metal barrier layer 152 in the second alternative design may include a non-textured metal barrier layer having a surface 452s. In at least one embodiment, the package lid metal barrier layer 152 may include Cu(100).

[0173] The interaction (e.g., reaction) between the package cover metal barrier layer 152 (e.g., Cu (100)) and the TIM layer 170 may cause an upper IMC layer 492 to be formed at the interface between the package cover metal barrier layer 152 and the TIM layer 170. The upper IMC layer 492 may be defined, for example, by a surface 452s of the package cover metal barrier layer 152 and an upper surface 470s-2 of the TIM layer 170. Figure 5B As shown in , the thickness of the upper IMC layer 492 may be greater than the thickness of the lower IMC layer 191 .

[0174] In at least one embodiment, surface 452s may be less textured than surface 151s of interposer module metal barrier layer 151. In at least one embodiment, surface 452s may have a roughness less than the roughness of surface 151s of interposer module metal barrier layer 151. In at least one embodiment, surface 452s may have a roughness Rz less than 1 μm.

[0175] In at least one embodiment, the package cover metal barrier layer 152 may include a Cu(111) layer. In such an embodiment, the surface 452s may include a non-textured structure of the Cu(111) layer. The surface 452s may include a significant amount of copper other than Cu(111), such as randomly arranged copper. In particular, the amount of columnar grains (e.g., Cu(111) or columnar copper with a (111) orientation) in the surface 452s may be 95% or less.

[0176] The surface 452s may be provided, for example, by controlling one or more process parameters in forming the package cover metal barrier layer 152. In at least one embodiment, the surface 452s may be formed by an electrochemical plating process using a DC mode, a large amount of additives, and a plating solution having an acidic pH. The surface 452s of the package cover metal barrier layer 152 may be formed alternatively or additionally by processing (e.g., by chemical mechanical polishing (CMP)) the surface 452s after forming the package cover metal barrier layer 152.

[0177] Figure 6 is a vertical cross-sectional view of a package structure 100 having a third optional design according to one or more embodiments. Figure 6 As shown in , the third alternative design can be basically similar to Figure 1A However, in a third alternative design, the TIM layer 170 may be Figure 1A The TIM layer 170 in the original design is different.

[0178] In particular, the TIM layer 170 in the third optional design may include a hybrid TIM layer. The TIM layer 170 in the third optional design may also be referred to as a hybrid TIM layer 170. The hybrid TIM layer 170 may include a first TIM layer 170a adjacent to the interposer module metal barrier layer 151 and a second TIM layer 170b adjacent to the package cover metal barrier layer 152. The hybrid TIM layer 170 may also include an internal TIM layer 170c between the first TIM layer 170a and the second TIM layer 170b. The internal TIM layer 170c may have a thermal conductivity greater than that of the first TIM layer and greater than that of the second TIM layer. In at least one embodiment, the first TIM layer 170a and the second TIM layer 170b may each include a metal TIM layer, including indium, tin, gallium, silver, etc. The internal TIM layer 170c may include, for example, a graphite film.

[0179] In at least one embodiment, the length in the x-direction and the width in the y-direction of each of the first TIM layer 170a, the second TIM layer 170b, and the inner TIM layer 170c may be substantially the same. In at least one embodiment, the thickness of the first TIM layer 170a may be substantially the same as the thickness of the second TIM layer 170b. In at least one embodiment, the thickness of the inner TIM layer 170c may be less than the thickness of the first TIM layer 170a and less than the thickness of the second TIM layer 170b. In at least one embodiment, the thickness of the inner TIM layer 170c may be less than 50% of the total thickness of the hybrid TIM layer 170.

[0180] FIG. 7A to FIG. 7B is a view of a package structure 100 having a fourth alternative design according to one or more embodiments. In particular, Fig. 7A is a vertical cross-sectional view of a package structure 100 having a fourth alternative design according to one or more embodiments. Figure 7B is a plan view (eg, top view) of a package structure 100 having a fourth alternative design according to one or more embodiments. Fig. 7A A vertical cross-section along Figure 7B Line B-B' in.

[0181] like Fig. 7A As shown in , in a fourth optional design, the package structure 100 may include one or more SMDs 740 on the chip side surface of the package substrate 110 adjacent to the package cover 130. The SMDs 740 may include, for example, semiconductor dies, such as the dies 140 described above. In at least one embodiment, the SMDs 740 may include memory dies, such as DRAM dies, HBM dies, etc. The SMDs 740 may be electrically coupled to the interposer module 120 (and the dies 140 in the interposer module 120) through the package substrate 110. The SMDs 740 may also include non-functional dies (e.g., dummy dies) that may provide structural support for the package structure 100.

[0182] SMD 740 may also include, for example, MLCC devices, integrated circuits, passive components such as resistors, capacitors, and inductors, active components such as two-terminal devices, diodes, and three-terminal devices, and electromechanical devices such as switches / relays, connectors, and micromotors. In at least one embodiment, SMD 740 may include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs)), rectifiers, and voltage regulators for power management applications.

[0183] The SMD 740 may be attached to the package substrate 110 by surface mount technology (SMT). Like the interposer module 120, the SMD 740 may be mounted on the package substrate upper bonding pad 114a. Thus, the SMD 740 may be electrically connected to the metal interconnect structure 114b in the package substrate upper dielectric layer 114. Thus, the SMD 740 may be electrically coupled to the semiconductor die 140 through the package substrate 110 and the interposer 200.

[0184] The SMD 740 may include, for example, an SMD substrate 710. The SMD substrate may include, for example, an organic or inorganic substrate (e.g., a silicon wafer). The SMD 740 may be attached to the package substrate 110 via a plurality of C4 bumps 721. The C4 bumps 721 may have a structure and function substantially similar to that of the C4 bumps 121 described above. Similar to the C4 bumps 121, the C4 bumps 721 may be bonded to the package substrate upper bonding pads 114a, respectively. The SMD 740 may be electrically coupled to the package substrate 110 via the C4 bumps 721. Other suitable means (e.g., adhesive) for attaching the SMD 740 to the package substrate 110 may be used.

[0185] An SMD underfill layer 719 may be formed on the package substrate 110 under and around the SMD 740 and around the C4 bumps 721. The SMD underfill layer 719 may help to securely fix the SMD 740 to the package substrate 110. The SMD underfill layer 719 may be substantially the same as the package underfill layer 129 described above. In particular, the SMD underfill layer 719 may be formed of an epoxy-based polymer material.

[0186] like Figure 7B As shown in FIG. 1 , the SMD 740 may be located on a longitudinal side of the package cover 130. It should be noted that the SMD 740 may have other locations on the package substrate 110 (e.g., located on a short side of the package cover 130). The package substrate 110 may have a substantially square shape that accommodates the package cover 130 and the SMD 740. The length of the SMD 740 in the y direction may be less than the width W of the package cover 130. 130 (See Figure 1B ). Each of the SMDs 740 may have a size (eg, an area in a plan view) that is smaller than a size of the interposer module 120. In at least one embodiment, the distance D between the SMDs 740 and the package cover 130 is 740 It can be less than 1000μm.

[0187] Figure 88 is a flow chart illustrating an optional method of manufacturing a package structure 100 according to one or more embodiments. Step 810 includes forming a metal barrier layer including Cu(111) on at least one of an interposer module or a package cover. Step 820 includes attaching the interposer module to a package substrate. Step 830 includes forming a thermal interface material (TIM) layer above the interposer module. Step 840 includes attaching the package cover to the package substrate above the interposer module, such that the interposer module, the TIM layer, and the metal barrier layer are disposed between the package cover and the package substrate, and the metal barrier layer is in direct contact with the TIM layer.

[0188] Fig. 9 is a vertical cross-sectional view of a package structure 100 having a fifth alternative design according to one or more embodiments. Fig. 9 As shown in FIG. 1 , in a fifth alternative design, the package lid 130 may include a plurality of fins 130 f extending from the package lid portion 130 p to the TIM layer 170 above the interposer module 120 . The package lid metal barrier layer 152 may be formed on the plurality of fins 130 f. The plurality of fins 130 f may form an innovative fin heat sink in the package structure 100 .

[0189] like Fig. 9 As shown in FIG. 1 , a plurality of fins 130f may be formed from the bottom surface S of the package cover portion 130p. 130p The fins 130f extend into the TIM layer 170 above the interposer module 120. The plurality of fins 130f can enhance heat dissipation in the package structure 100 while also enhancing the mechanical structure of the TIM layer 170. The fins 130f can be separated, for example, by gaps G, and at least a portion of the TIM layer 170 can be located in the gaps G. In at least one embodiment, each of the fins 130f can be located above the interposer module 120. In at least one embodiment, the fins 130f can be located above the die 140 in the interposer module 120. In at least one embodiment, each of the fins 130f can extend into the TIM layer 170 to some extent.

[0190] The fin 130f of the package cover 130 can be formed from the bottom surface S of the package cover plate portion. 130p The fin 130f may extend in the form of a cylinder. The fin 130f may be formed as a cylinder, in which case the fin 130f may have a circular cross-section. The arc-shaped end portion of the fin 130f may be formed in the TIM layer 170. The fin 130f may optionally be formed as a square cylinder, in which case the fin 130f may have a square cross-section. Other shapes of the fin 130f are within the contemplation of the embodiments of the present disclosure. For example, an elliptical cross-section, a triangular cross-section, and other polygonal cross-sections may be used.

[0191] The fins 130f of the package cover 130 may have a pitch P in both the x-direction and the y-direction. 130f(eg, the distance between centers). The fins 130f of the package cover 130 may optionally have a pitch in the x-direction that is different from the pitch in the y-direction. In at least one embodiment, the pitch P 130f It can be in the range from 1 mm to 5 mm. 130f The spacing P may be substantially uniform throughout the entire fin 130f. 130f The pitch P in the x-direction may optionally vary between the fins 130f in the x-direction and / or the y-direction. 130f The spacing P in the y direction can be 130f Same or different.

[0192] The fins 130f of the package cover 130 may be formed over the die 140 in the interposer module 120. In at least one embodiment, the location of the fins 130f may correspond to a semiconductor (e.g., silicon) region (e.g., a die region, a system-on-chip region, an HBM region, etc.) of the interposer module 120. In at least one embodiment, one or more of the fins 130f may include at least a portion over the molding material layer 127 in the interposer module 120. In at least one embodiment, the fins 130f may be formed as an array of rows and columns on the die 140.

[0193] Fig.10 is a vertical cross-sectional view of a package structure 100 having a sixth optional design according to one or more embodiments. Fig.10 As shown in FIG. 1 , in a sixth alternative design, the TIM layer 170 may include a TIM layer extension portion 170x located outside the interposer module 120. In at least one embodiment, the TIM layer extension portion 170x may be formed around the entire periphery of the interposer module 120. The TIM layer extension portion 170x may help promote heat dissipation in the package structure 100.

[0194] The TIM layer extension portion 170x may be formed of the same material as the rest of the TIM layer 170 (e.g., the portion of the TIM layer 170 located between the interposer module 120 and the package cover portion 130p). The TIM layer extension portion 170x may be formed integrally with the rest of the TIM layer 170. The TIM layer extension portion 170x may be formed simultaneously with the formation of the rest of the TIM layer 170 and using the same process as that used in the formation of the rest of the TIM layer 170. The TIM layer extension portion 170x may have a thickness substantially similar to that of the rest of the TIM layer 170.

[0195] like Fig.10 As shown in FIG. 1 , in a sixth alternative design, the TIM layer extension portion 170x may protrude outwardly and downwardly from the remainder of the TIM layer 170 (eg, from Figure 1AThe TIM layer extension portion 170x may protrude downward at an angle θ relative to the outer sidewall 127a of the molding material layer 127 and relative to the outer sidewall of the interposer module metal barrier layer 151. The TIM layer extension portion 170x may not contact the inner sidewall of the interposer module metal barrier layer 151 or the foot portion 130a. In at least one embodiment, the angle θ between the bottom surface of the TIM layer extension portion 170x and the outer sidewall 127a of the molding material layer 127 (e.g., between the bottom surface of the TIM layer extension portion 170x and the outer sidewall of the interposer module metal barrier layer 151) may be less than 90°.

[0196] Fig.11 1 is a vertical cross-sectional view of a package structure 100 having a seventh alternative design according to one or more embodiments. The seventh alternative design may be substantially similar to the above description of Fig.10 For example, the TIM layer 170 may include a TIM layer extension portion 170 x located outside the interposer module 120 , the TIM layer extension portion 170 x may be formed around the entire periphery of the interposer module 120 , and so on.

[0197] However, the TIM layer extension portion 170x in the seventh optional design may be different from the TIM layer extension portion 170x in the sixth optional design in terms of the protruding direction of the TIM layer extension portion 170x. In particular, in the seventh optional design, the TIM layer extension portion 170x may protrude downward toward the package substrate 110 in a direction along the sidewall of the interposer module 120 (e.g., along the outer sidewall 127a of the molding material layer 127). The length of the TIM layer extension portion 170x may be such that the height of the end of the TIM layer extension portion 170x may be approximately the same as the height of the uppermost surface of the molding material layer 127. The TIM layer extension portion 170x may contact the sidewall of the interposer module metal barrier layer 151. In at least one embodiment, the TIM layer extension portion 170x may contact the outer sidewall 127a of the molding material layer 127.

[0198] Fig.12 1 is a vertical cross-sectional view of a package structure 100 having an eighth alternative design according to one or more embodiments. The eighth alternative design may also be substantially similar to the above description of Fig.10The sixth optional design described above. However, the TIM layer extension portion 170x in the eighth optional design may be different from the TIM layer extension portion 170x in the sixth optional design in terms of the protruding direction of the TIM layer extension portion 170x. In particular, in the eighth optional design, the TIM layer extension portion 170x may protrude laterally and contact the inner side wall of the foot portion 130a of the package cover 130. That is, in the eighth optional design, the TIM layer extension portion 170x may not protrude downward to any extent. With this design, the TIM layer extension portion 170x may be particularly helpful in promoting heat dissipation in the package structure 100.

[0199] Fig.13 is a vertical cross-sectional view of a package structure 100 having a ninth optional design according to one or more embodiments. Fig.13 As shown in FIG. 1 , in a ninth alternative design, the package cover 130 may include a bottom surface S of the plate portion 130 p of the package cover 130. 130p A protruding dam structure 130pd. The dam structure 130pd may protrude downward between the TIM layer 170 and the foot portion 130a of the package cover 130. In at least one embodiment, the dam structure 130pd may protrude in a direction substantially parallel to the inner sidewall of the foot portion 130a. In at least one embodiment, the dam structure 130pd may be continuously formed around the entire periphery of the interposer module 120. The dam structure 130pd may help control the lateral expansion of the TIM layer 170. In particular, the dam structure 130pd may prevent the TIM layer 170 (especially if the TIM layer 170 includes a gel-type TIM) from dripping onto the interposer 200 or a device mounted on the interposer 200.

[0200] The dam structure 130pd may be formed of the same material as the package cover portion 130p. The dam structure 130pd may be formed integrally with the package cover portion 130p. The dam structure 130pd may be formed simultaneously with the formation of the package cover 130. For example, the dam structure 130pd may be formed by the same computer numerical control (CNC) machining process used to form the package cover 130. The dam structure 130pd may have a width in the range from 1 mm to 20 mm (e.g., in the x-direction). The length of the dam structure 130pd in the z-direction may be such that the height of the end of the dam structure 130pd may be substantially the same as the height of the interposer module metal barrier layer 151. As Fig.13 As shown in , the inner sidewall of the dam structure 130 pd may contact the package cap metal barrier layer 152 and the TIM layer 170 .

[0201] Fig.14 is a vertical cross-sectional view of a package structure 100 having a tenth alternative design according to one or more embodiments. Fig.14As shown in FIG. 10 , in a tenth alternative design, the package cover 130 may include a substantially similar Fig.13 The dam structure 130pd of the ninth optional design in the embodiment of the present invention is a dam structure 130pd of the dam structure 130pd of the ninth optional design in the embodiment of the present invention. However, compared to the ninth optional design, in the tenth optional design, a package cover metal barrier layer 152 (e.g., Cu(111)) can be formed along the inner sidewall of the dam structure 130pd. The package cover metal barrier layer 152 can contact the end of the TIM layer 170. In at least one embodiment, the package cover metal barrier layer 152 can separate the end of the TIM layer 170 from the inner sidewall of the dam structure 130pd. The length of the package cover metal barrier layer 152 in the z direction can be such that the height of the end of the package cover metal barrier layer 152 can be greater than the height of the end of the dam structure 130pd. The package cover metal barrier layer 152 can be formed on the inner sidewall of the dam structure 130pd by the same plating process used to form the package cover metal barrier layer 152 on the package cover plate portion 130p. This design can help enhance the heat dissipation effect while inhibiting the formation of an IMC layer (e.g., between the package cover metal barrier layer 152 and the TIM layer 170). The thickness of the package cover metal barrier layer 152 on the inner sidewall of the dam structure 130pd can be substantially the same as the thickness of the rest of the package cover metal barrier layer 152.

[0202] Fig.15 is a vertical cross-sectional view of a package structure 100 having an eleventh alternative design according to one or more embodiments. Fig.15 As shown in FIG. 1 , in an eleventh alternative design, the package cover 130 may include a substantially similar Fig.13 The ninth optional design and Fig.14 However, compared with the ninth and tenth optional designs, in the eleventh optional design, a package cover metal barrier layer 152 (e.g., Cu(111)) may be formed over substantially the entire surface of the dam structure 130pd.

[0203] The package cover metal barrier layer 152 may also be formed, for example, by the same plating process used to form the package cover metal barrier layer 152 on the package cover plate portion 130p. This design of the eleventh optional design may also help to enhance the heat dissipation effect while suppressing the formation of an IMC layer (e.g., between the package cover metal barrier layer 152 and the TIM layer 170).

[0204] Reference now Figures 1A to 8The packaging structure 100 may include: a packaging substrate 110; an interposer module 120, located on the packaging substrate 110; a packaging cover 130, located on the interposer module 120; and a heat dissipation structure 300, located between the interposer module 120 and the packaging cover 130, the heat dissipation structure 300 including: a thermal interface material (TIM) layer 170: and metal barrier layers 151, 152, located between the TIM layer 170 and at least one of the interposer module 120 or the packaging cover 130, and configured to inhibit the formation of intermetallic compound (IMC) layers 191, 192.

[0205] In one embodiment, the metal barrier layers 151, 152 may include Cu(111). In one embodiment, the TIM layer 170 may include a metal TIM layer 170 including at least one of indium, tin, gallium, or silver. In one embodiment, the metal barrier layers 151, 152 may include: an interposer module metal barrier layer 151 located between the TIM layer 170 and the interposer module 120; and a package cover metal barrier layer 152 located between the package cover 130 and the TIM layer 170. In one embodiment, at least one of the interposer module metal barrier layer 151 or the package cover metal barrier layer 152 may include a textured structure. In one embodiment, the IMC layers 191, 192 may include a lower IMC layer 191 located between the TIM layer 170 and the interposer module metal barrier layer 151 and an upper IMC layer 192 located between the TIM layer 170 and the package cover metal barrier layer 152. In one embodiment, the area of ​​the TIM layer 170 may be greater than or equal to the area of ​​the interposer module metal barrier layer 151. In one embodiment, the area of ​​the package cover metal barrier layer 152 may be greater than or equal to the area of ​​the TIM layer 170. In one embodiment, the thickness T of the interposer module metal barrier layer 151 may be greater than or equal to the area of ​​the TIM layer 170. 151 The thickness T of the package cover metal barrier layer 152 may be greater than or equal to 152 In one embodiment, the thickness T of the TIM layer 170 is 170 The thickness T of the metal barrier layer 151 of the interposer module may be greater than or equal to 151 In one embodiment, at least one of a first interface between the interposer module metal barrier layer 151 and the TIM layer 170 or a second interface between the package cap metal barrier layer 152 and the TIM layer 170 is substantially void-free.

[0206] Reference again Figures 1A to 8, a method for manufacturing a packaging structure 100 may include: forming a metal barrier layer 151, 152 including Cu (111) on at least one of an interposer module 120 or a packaging cover 130; attaching the interposer module 120 to a packaging substrate 110; forming a thermal interface material (TIM) layer 170 above the interposer module 120; and attaching the packaging cover 130 to the packaging substrate 110 above the interposer module 120, so that the interposer module 120, the TIM layer 170 and the metal barrier layers 151, 152 are disposed between the packaging cover 130 and the packaging substrate 120, and the metal barrier layers 151, 152 are in direct contact with the TIM layer 170. In one embodiment, forming the metal barrier layers 151, 152 may include: forming the interposer module metal barrier layer 151 on the interposer module 120, wherein the interposer module metal barrier layer 151 may include Cu (111); and forming the package cover metal barrier layer 152 on the package cover 130, wherein the package cover metal barrier layer 152 may include Cu (111). In one embodiment, forming the interposer module metal barrier layer 151 may include forming the interposer module metal barrier layer 151 to include a textured structure, and forming the package cover metal barrier layer 152 may include forming the package cover metal barrier layer 152 to include a textured structure. In one embodiment, forming the TIM layer 170 may include forming the TIM layer 170 to have an area greater than or equal to the area of ​​the interposer module metal barrier layer 151 and a thickness T greater than or equal to the thickness T of the interposer module metal barrier layer 151. 151 Thickness T 170 In one embodiment, forming the package cover metal barrier layer 152 may include forming the package cover metal barrier layer 152 to have an area greater than or equal to the area of ​​the TIM layer 170 and a thickness T less than or equal to the interposer module metal barrier layer 151. 151 Thickness T 152 In one embodiment, forming the TIM layer 170 may include forming a hybrid TIM layer 170 including: a first metal TIM layer 170 ; a graphite film on the first metal TIM layer 170 ; and a second metal TIM layer 170 on the graphite film.

[0207] Reference again Figures 1A to 8, the package structure 100 may include: a package substrate 110; an interposer module 120, located on the package substrate 110; a package cover 130, located on the interposer module 120; and a heat dissipation structure 300, between the interposer module 120 and the package cover 130, the heat dissipation structure 300 including: a thermal interface material (TIM) layer; and metal barrier layers 151, 152, directly contacting the TIM layer 170 and including highly textured copper. In at least one embodiment, the TIM layer 170 may be located outside the interposer module 120 and an extension portion 170x protruding in one of the following ways: downward at an angle relative to the sidewall of the interposer module 120; downward in a direction along the sidewall of the interposer module 120 toward the package substrate 110; or laterally and contacting the inner sidewall of the foot portion 130a of the package cover 130. In at least one embodiment, the package cover 130 may include: a plate portion 130p located above the interposer module 120; a foot portion 130a attached to the plate portion 130p and to the package substrate 110; and a dam structure 130pd extending from the bottom surface S of the plate portion 130p between the TIM layer 170 and the foot portion 130a. 130p protrude.

[0208] Some embodiments of the present application provide a packaging structure, including: a packaging substrate; an interposer module located on the packaging substrate; a packaging cover located on the interposer module; and a heat dissipation structure located between the interposer module and the packaging cover, the heat dissipation structure including: a thermal interface material (TIM) layer; and a metal barrier layer located between the thermal interface material layer and at least one of the interposer module or the packaging cover, and configured to inhibit the formation of an intermetallic compound (IMC) layer.

[0209] In some embodiments, the metal barrier layer includes Cu (111). In some embodiments, the thermal interface material layer includes a metal thermal interface material layer, and the metal thermal interface material layer includes at least one of indium, tin, gallium or silver. In some embodiments, the metal barrier layer includes: an interposer module metal barrier layer, located between the thermal interface material layer and the interposer module; and a package cover metal barrier layer, located between the package cover and the thermal interface material layer. In some embodiments, at least one of the interposer module metal barrier layer or the package cover metal barrier layer includes a textured structure. In some embodiments, the intermetallic compound layer includes a lower intermetallic compound layer located between the thermal interface material layer and the interposer module metal barrier layer and an upper intermetallic compound layer located between the thermal interface material layer and the package cover metal barrier layer. In some embodiments, the area of ​​the thermal interface material layer is greater than or equal to the area of ​​the interposer module metal barrier layer. In some embodiments, the area of ​​the package cover metal barrier layer is greater than or equal to the area of ​​the thermal interface material layer. In some embodiments, the thickness of the interposer module metal barrier layer is greater than or equal to the thickness of the package cover metal barrier layer. In some embodiments, the thickness of the thermal interface material layer is greater than or equal to the thickness of the interposer module metal barrier layer. In some embodiments, at least one of a first interface between the interposer module metal barrier layer and the thermal interface material layer or a second interface between the package lid metal barrier layer and the thermal interface material layer is substantially free of voids.

[0210] Some other embodiments of the present application provide a method for manufacturing a packaging structure, the method comprising: forming a metal barrier layer including Cu (111) on at least one of an interposer module or a packaging cover; attaching the interposer module to a packaging substrate; forming a thermal interface material (TIM) layer above the interposer module; and attaching the packaging cover to the packaging substrate above the interposer module, so that the interposer module, the thermal interface material layer and the metal barrier layer are arranged between the packaging cover and the packaging substrate, and the metal barrier layer is in direct contact with the thermal interface material layer.

[0211] In some embodiments, forming the metal barrier layer includes: forming an interposer module metal barrier layer on the interposer module, wherein the interposer module metal barrier layer includes Cu (111); and forming a package cover metal barrier layer on the package cover, wherein the package cover metal barrier layer includes Cu (111). In some embodiments, forming the interposer module metal barrier layer includes forming the interposer module metal barrier layer to include a textured structure, and forming the package cover metal barrier layer includes forming the package cover metal barrier layer to include a textured structure. In some embodiments, forming the thermal interface material layer includes forming the thermal interface material layer to have an area greater than or equal to an area of ​​the interposer module metal barrier layer and a thickness greater than or equal to a thickness of the interposer module metal barrier layer. In some embodiments, forming the package cover metal barrier layer includes forming the package cover metal barrier layer to have an area greater than or equal to an area of ​​the thermal interface material layer and a thickness less than or equal to a thickness of the interposer module metal barrier layer. In some embodiments, forming the thermal interface material layer includes forming a hybrid thermal interface material layer, the hybrid thermal interface material layer including: a first metal thermal interface material layer; a graphite film located on the first metal thermal interface material layer; and a second metal thermal interface material layer located on the graphite film.

[0212] Some other embodiments of the present application provide a packaging structure, including: a packaging substrate; an interposer module located on the packaging substrate; a packaging cover located above the interposer module; and a heat dissipation structure located between the interposer module and the packaging cover, the heat dissipation structure including: a thermal interface material (TIM) layer; and a metal barrier layer directly in contact with the thermal interface material layer and including highly textured copper.

[0213] In some embodiments, the thermal interface material layer includes an extension portion located outside the interposer module and protruding in one of the following ways: downward at an angle relative to the sidewall of the interposer module; downward in a direction along the sidewall of the interposer module toward the package substrate; or laterally and contacting the inner sidewall of the foot portion of the package cover. In some embodiments, the package cover includes: a plate portion located above the interposer module; a foot portion attached to the plate portion and to the package substrate; and a dam structure protruding from the bottom surface of the plate portion between the thermal interface material layer and the foot portion.

[0214] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent configurations do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A packaging structure, comprising: Package substrate; An interposer module, located on the packaging substrate; A packaging cover, located on the interposer module; as well as A heat dissipation structure is located between the interposer module and the packaging cover, and the heat dissipation structure includes: Thermal interface material (TIM) layer; as well as A metal barrier layer is located between the thermal interface material layer and at least one of the interposer module or the package lid and is configured to inhibit the formation of an intermetallic compound (IMC) layer.

2. The packaging structure according to claim 1, wherein: The metal barrier layer includes Cu(111).

3. The packaging structure according to claim 1, wherein: The thermal interface material layer comprises a metal thermal interface material layer, and the metal thermal interface material layer comprises at least one of indium, tin, gallium or silver.

4. The packaging structure according to claim 1, wherein: The metal barrier layer comprises: an interposer module metal barrier layer, located between the thermal interface material layer and the interposer module; and The package cover metal barrier layer is located between the package cover and the thermal interface material layer.

5. The packaging structure according to claim 4, wherein: At least one of the interposer module metal barrier layer or the package lid metal barrier layer includes a textured structure.

6. The packaging structure according to claim 4, wherein: The intermetallic compound layer includes a lower intermetallic compound layer located between the thermal interface material layer and the interposer module metal barrier layer and an upper intermetallic compound layer located between the thermal interface material layer and the package cover metal barrier layer.

7. The packaging structure according to claim 4, wherein: The area of ​​the thermal interface material layer is greater than or equal to the area of ​​the metal barrier layer of the intermediate layer module.

8. The packaging structure according to claim 4, wherein: The area of ​​the package cover metal barrier layer is greater than or equal to the area of ​​the thermal interface material layer.

9. A method for manufacturing a packaging structure, the method comprising: forming a metal barrier layer including Cu (111) on at least one of the interposer module or the package cover; attaching the interposer module to a package substrate; forming a thermal interface material (TIM) layer over the interposer module; as well as The package lid is attached to the package substrate over the interposer module such that the interposer module, the thermal interface material layer, and the metal barrier layer are disposed between the package lid and the package substrate, and the metal barrier layer is in direct contact with the thermal interface material layer.

10. A packaging structure, comprising: Package substrate; An interposer module, located on the packaging substrate; A packaging cover, located above the interposer module; as well as A heat dissipation structure is located between the interposer module and the packaging cover, and the heat dissipation structure includes: Thermal interface material (TIM) layer; as well as A metal barrier layer is in direct contact with the thermal interface material layer and includes highly textured copper.

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