Multi-chip substrate packaging structure and preparation method thereof

Abstract

According to the multi-chip substrate packaging structure and the preparation method thereof, the front face of a first chip set is in bonding connection with the upper end face of a first circuit layer, one end of a first metal column is electrically connected with the upper end face of the first circuit layer, and the first metal column and the first chip set are plastically packaged in a first plastic packaging structure; the other end of the first metal column is exposed on the upper end surface of the first plastic package structure; the front surface of the second chip group is in bonding connection with the lower end surface of the second circuit layer, one end of the second metal column is electrically connected with the lower end surface of the second circuit layer, the second metal and the second chip group are plastically packaged in a second plastic packaging structure, and the other end of the second metal column is exposed on the lower end surface of the second plastic packaging structure; the other end of the first metal column is electrically connected with the other end of the second metal column, and the upper end face of the first plastic package structure is bonded with the lower end face of the second plastic package structure. According to the invention, more chips can be installed in a packaging space with a specific size, and the processing difficulty is low.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a multi-chip substrate packaging structure and a preparation method thereof. Background Art

[0002] In a traditional chip packaging structure, only a single-layer chip can be set between the upper and lower circuit layers in a packaging structure. However, as the market demand for the number of chips installed in the chip packaging structure increases, the traditional chip packaging structure can no longer meet the needs of installing more chips in a packaging space of a specific size.

[0003] Therefore, a multi-chip substrate packaging structure is developed to solve the above problems. Summary of the invention

[0004] The present invention provides a multi-chip substrate packaging structure to solve the problem that the existing chip packaging structure cannot meet the requirement of installing more chips in a packaging space of a specific size.

[0005] The present invention achieves the above-mentioned purpose through the following technical solutions: A multi-chip substrate packaging structure, comprising: A first packaging structure, wherein the first packaging structure includes a first circuit layer, a plurality of first metal pillars, a first chipset, and a first plastic packaging structure, wherein a front surface of the first chipset is bonded to an upper end surface of the first circuit layer, one end of the first metal pillar is electrically connected to an upper end surface of the first circuit layer, the first metal pillar and the first chipset are plastic-sealed in the first plastic packaging structure, and the other end of the first metal pillar is exposed and arranged on an upper end surface of the first plastic packaging structure; A second packaging structure, wherein the second packaging structure includes a second circuit layer, a plurality of second metal pillars, a second chipset, and a second plastic packaging structure, wherein the front surface of the second chipset is bonded to the lower end surface of the second circuit layer, one end of the second metal pillar is electrically connected to the lower end surface of the second circuit layer, the second metal and the second chipset are plastic-sealed in the second plastic packaging structure, and the other end of the second metal pillar is exposed and arranged on the lower end surface of the second plastic packaging structure; The other end of the first metal column is electrically connected to the other end of the second metal column, and the upper end surface of the first plastic packaging structure is bonded to the lower end surface of the second plastic packaging structure.

[0006] Furthermore, the other ends of several of the first metal pillars are connected to a first BGA packaging device, the other ends of several of the second metal pillars are connected to a second BGA packaging device, and the first BGA packaging device is connected to the corresponding second BGA packaging device.

[0007] Furthermore, the arrangement positions of the plurality of first metal pillars correspond one-to-one to the arrangement positions of the plurality of second metal pillars.

[0008] Furthermore, the first chipset includes at least a first chip and a second chip, the front side of the first chip is connected to the first circuit layer by flip chip bonding, and the front side of the second chip is connected to the first circuit layer by wire bonding.

[0009] Furthermore, the upper end surface of the first plastic packaging structure and the lower end surface of the second plastic packaging structure are bonded via a sealant layer or an ACF layer.

[0010] Furthermore, a plurality of BGA packaging components are connected to the lower end surface of the first packaging structure.

[0011] Furthermore, a base layer is connected underneath a plurality of the BGA packaged components.

[0012] Furthermore, a layer of bare chips is electrically connected to the upper end surface of the second circuit layer.

[0013] Furthermore, the upper end surface of the second circuit layer is electrically connected to a layer of packaging chips, the packaging chip is a computing chip, and the first chipset and the second chipset are functional chips.

[0014] The present invention also provides a method for preparing a multi-chip substrate packaging structure, comprising: Processing a first circuit layer on the first substrate by a redistribution layer process or a substrate bonding process; A plurality of first metal pillars having one end electrically connected to the first circuit layer are processed on the upper surface of the first circuit layer by through-molding via technology; Connecting the front surface of the first chipset to the upper surface of the first circuit layer through a chip bonding process on the first circuit layer; The first circuit layer, the first metal column, and the first chipset are packaged using an epoxy resin molding packaging process to obtain a first plastic packaging structure; Grinding the upper surface of the first plastic package structure until the other end of the first metal column is exposed to obtain a first packaging structure; Processing a second circuit layer on the second substrate by a redistribution layer process or a substrate bonding process; A plurality of second metal pillars having one end electrically connected to the second circuit layer are processed on the upper surface of the second circuit layer by through-molding via technology; Connecting the front surface of the second chipset to the upper surface of the second circuit layer through a chip bonding process on the second circuit layer; The second circuit layer, the second metal column and the second chipset are packaged by using an epoxy resin molding packaging process to obtain a second plastic packaging structure; Grinding the upper surface of the second plastic package structure until the other end of the second metal column is exposed, removing the second base substrate, and obtaining a second packaging structure; Invert the second packaging structure directly above the first packaging structure, electrically connect the other end of the first metal column and the other end of the second metal column, and bond the lower end surface of the second packaging structure to the upper end surface of the first packaging structure, then remove the first substrate to obtain a multi-chip substrate packaging structure.

[0015] The beneficial effects of the present invention are: The chip packaging structure proposed in the present invention can install more chips in a packaging space of a specific size, thereby meeting the market demand for the number of chips installed in the chip packaging structure, and is particularly suitable for functional chips with low heat generation and large installation quantity requirements. In addition, the specific structure in the present invention has a smaller flatness requirement for the first packaging structure and the second packaging structure, making the preparation and processing of the multi-chip substrate packaging structure easier. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is one of the structural diagrams of a multi-chip substrate packaging structure in an embodiment of the present application; Figure 2 This is a second structural diagram of a multi-chip substrate packaging structure in an embodiment of the present application; Figure 3 This is a third structural diagram of a multi-chip substrate packaging structure in an embodiment of the present application; Figure 4 This is a fourth structural diagram of a multi-chip substrate packaging structure in an embodiment of the present application; Figure 5 This is a fifth structural diagram of a multi-chip substrate packaging structure in an embodiment of the present application; Figure 6 This is a sixth structural diagram of a multi-chip substrate packaging structure in an embodiment of the present application; Figure 7 A method flow chart of a method for preparing a multi-chip substrate packaging structure in an embodiment of the present application; Figure 8 This is the seventh structural diagram of a multi-chip substrate packaging structure in the embodiment of the present application.

[0017] In the figure: 1-first circuit layer; 2-first metal column; 3-first chip; 4-first plastic packaging structure; 5-second circuit layer; 6-second metal column; 7-second chip; 8-second plastic packaging structure; 9-first BGA packaging device; 10-second BGA packaging device; 11-BGA packaging device; 12-base layer; 13-bare chip; 14-packaged chip. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0021] In the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. These directions or positional relationships are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0022] Furthermore, the terms “first”, “second”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0023] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, terms such as "setting" and "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. The front side of the chip mentioned in this application refers to the circuit side or BGA side on the chip. The front side of the chip is generally connected to a metal column / BGA packaging device.

[0024] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings.

[0025] like Figure 1 As shown, a multi-chip substrate packaging structure includes: A multi-chip substrate packaging structure, comprising: A first packaging structure, wherein the first packaging structure comprises a first circuit layer 1, a plurality of first metal pillars 2, a first chipset, and a first plastic packaging structure 4, wherein the front surface of the first chipset is bonded to the upper end surface of the first circuit layer 1, one end of the first metal pillar 2 is electrically connected to the upper end surface of the first circuit layer 1, the first metal pillar 2 and the first chipset are plastic-sealed in the first plastic packaging structure 4, and the other end of the first metal pillar 2 is exposed and arranged on the upper end surface of the first plastic packaging structure 4; A second packaging structure, wherein the second packaging structure includes a second circuit layer 5, a plurality of second metal pillars 6, a second chipset, and a second plastic packaging structure 8, wherein the front surface of the second chipset is bonded to the lower end surface of the second circuit layer 5, one end of the second metal pillar 6 is electrically connected to the lower end surface of the second circuit layer 5, the second metal and the second chipset are plastic-sealed in the second plastic packaging structure 8, and the other end of the second metal pillar 6 is exposed and arranged on the lower end surface of the second plastic packaging structure 8; The other end of the first metal column 2 is electrically connected to the other end of the second metal column 6 , and the upper end surface of the first plastic packaging structure 4 is bonded to the lower end surface of the second plastic packaging structure 8 .

[0026] like Figure 8As shown, in some embodiments, the other ends of several first metal pillars 2 are connected to first BGA package devices 9, the other ends of several second metal pillars 6 are connected to second BGA package devices 10, and the first BGA package devices 9 are connected to the corresponding second BGA package devices 10. In addition to connection through BGA package devices, the first metal pillars 2 and the second metal pillars 6 can also be connected through Plated SolderBumps, Cu Pillar Bumps, and BGA Rules processes.

[0027] like Figure 1 As shown, in some embodiments, the arrangement positions of a plurality of first metal pillars 2 correspond one to one with the arrangement positions of a plurality of second metal pillars 6 .

[0028] like Figure 1 As shown, in some embodiments, the first chipset includes at least a first chip 3 and a second chip 7, the front side of the first chip 3 is connected to the first circuit layer 1 by flip chip bonding, and the front side of the second chip 7 is connected to the first circuit layer 1 by wire bonding.

[0029] like Figure 1 As shown, in some embodiments, the upper end surface of the first plastic packaging structure 4 and the lower end surface of the second plastic packaging structure 8 are bonded by a sealing adhesive layer or an ACF adhesive layer.

[0030] like Figure 2 As shown, in some embodiments, a plurality of BGA package components 11 are connected to the lower end surface of the first package structure.

[0031] like Figure 3 As shown, in some embodiments, a base layer 12 is connected underneath a plurality of the BGA packaged devices 11 .

[0032] like Figure 4 As shown, in some embodiments, the upper end surface of the second circuit layer 5 is electrically connected to a layer of bare chips 13 .

[0033] like Figure 5 As shown, in some embodiments, the upper end surface of the second circuit layer 5 is electrically connected with a layer of packaged chip 14, the packaged chip 14 is a computing chip, and the first chipset and the second chipset are functional chips. The functional chips, such as MCU chips and CIS chips, are different from chips that rely on integration to improve computing power. They generate less heat and require a large number of installations, so they are more suitable for packaging in the present invention. For some computing chips that generate a lot of heat, it is more suitable to be externally mounted on the outer surface of the second circuit layer 2. This makes the layout of the entire chip packaging structure more optimized.

[0034] like Figure 6As shown, in some embodiments, the upper end surface of the second circuit layer 5 is electrically connected to a layer of bare chips 13, and at the same time, the lower end surface of the first packaging structure is connected to a plurality of BGA packaging devices 11.

[0035] like Figure 7 As shown, a method for preparing a multi-chip substrate packaging structure comprises: Processing a first circuit layer 1 on a first substrate by a redistribution layer process or a substrate bonding process; A plurality of first metal pillars 2 having one end electrically connected to the first circuit layer 1 are processed on the upper surface of the first circuit layer 1 by through-molding via technology; Connecting the front surface of the first chipset to the upper surface of the first circuit layer 1 through a chip bonding process on the first circuit layer 1; The first circuit layer 1, the first metal pillar 2, and the first chipset are packaged using an epoxy resin molding packaging process to obtain a first plastic packaging structure 4; Grinding the upper surface of the first plastic package structure 4 until the other end of the first metal column 2 is exposed to obtain a first packaging structure; Processing a second circuit layer 5 on the second substrate by a redistribution layer process or a substrate bonding process; A plurality of second metal pillars 6 having one end electrically connected to the second circuit layer 5 are processed on the upper surface of the second circuit layer 5 by through-molding via technology; Connecting the front surface of the second chipset to the upper surface of the second circuit layer 5 through a chip bonding process on the second circuit layer 5; The second circuit layer 5, the second metal pillar 6, and the second chipset are packaged by using an epoxy resin molding packaging process, and the second substrate is removed to obtain a second plastic packaging structure 8; Grinding the upper surface of the second plastic package structure 8 until the other end of the second metal column 6 is exposed to obtain a second packaging structure; Invert the second packaging structure directly above the first packaging structure, electrically connect the other end of the first metal column 2 and the other end of the second metal column 6, and bond the lower end surface of the second packaging structure to the upper end surface of the first packaging structure, then remove the first substrate to obtain a multi-chip substrate packaging structure.

[0036] The chip packaging structure proposed in the present invention can install more chips in a packaging space of a specific size, thereby meeting the market demand for the number of chips installed in the chip packaging structure, and is particularly suitable for functional chips with low heat generation and large installation quantity requirements. In addition, the specific structure in the present invention has a smaller flatness requirement for the first packaging structure and the second packaging structure, making the preparation and processing of the multi-chip substrate packaging structure easier.

[0037] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A multi-chip substrate packaging structure, characterized in that: include: A first packaging structure, wherein the first packaging structure includes a first circuit layer, a plurality of first metal pillars, a first chipset, and a first plastic packaging structure, wherein a front surface of the first chipset is bonded to an upper end surface of the first circuit layer, one end of the first metal pillar is electrically connected to an upper end surface of the first circuit layer, the first metal pillar and the first chipset are plastic-sealed in the first plastic packaging structure, and the other end of the first metal pillar is exposed and arranged on an upper end surface of the first plastic packaging structure; A second packaging structure, wherein the second packaging structure includes a second circuit layer, a plurality of second metal pillars, a second chipset, and a second plastic packaging structure, wherein the front surface of the second chipset is bonded to the lower end surface of the second circuit layer, one end of the second metal pillar is electrically connected to the lower end surface of the second circuit layer, the second metal and the second chipset are plastic-sealed in the second plastic packaging structure, and the other end of the second metal pillar is exposed and arranged on the lower end surface of the second plastic packaging structure; The other end of the first metal column is electrically connected to the other end of the second metal column, and the upper end surface of the first plastic packaging structure is bonded to the lower end surface of the second plastic packaging structure.

2. The multi-chip substrate packaging structure according to claim 1, characterized in that: The other ends of several of the first metal pillars are connected to a first BGA packaging device, the other ends of several of the second metal pillars are connected to a second BGA packaging device, and the first BGA packaging device is connected to the corresponding second BGA packaging device.

3. The multi-chip substrate packaging structure according to claim 1, characterized in that: The arrangement positions of the plurality of first metal pillars correspond one-to-one to the arrangement positions of the plurality of second metal pillars.

4. The multi-chip substrate packaging structure according to claim 1, characterized in that: The first chipset includes at least a first chip and a second chip. The front side of the first chip is connected to the first circuit layer by flip chip bonding, and the front side of the second chip is connected to the first circuit layer by wire bonding.

5. The multi-chip substrate packaging structure according to claim 1, characterized in that: The upper end surface of the first plastic packaging structure and the lower end surface of the second plastic packaging structure are bonded by a sealing adhesive layer or an ACF adhesive layer.

6. The multi-chip substrate packaging structure according to claim 1, characterized in that: A plurality of BGA packaging components are connected to the lower end surface of the first packaging structure.

7. The multi-chip substrate packaging structure according to claim 6, characterized in that: A base layer is connected below a plurality of the BGA packaged components.

8. A multi-chip substrate packaging structure according to claim 1 or 6, characterized in that: The upper end surface of the second circuit layer is electrically connected to a layer of bare chips.

9. A multi-chip substrate packaging structure according to claim 1 or 6, characterized in that: The upper end surface of the second circuit layer is electrically connected to a layer of packaging chips, the packaging chip is a computing chip, and the first chipset and the second chipset are functional chips.

10. A method for preparing a multi-chip substrate packaging structure, characterized in that: include: Processing a first circuit layer on the first substrate by a redistribution layer process or a substrate bonding process; A plurality of first metal pillars having one end electrically connected to the first circuit layer are processed on the upper surface of the first circuit layer by through-molding via technology; Connecting the front surface of the first chipset to the upper surface of the first circuit layer through a chip bonding process on the first circuit layer; The first circuit layer, the first metal column, and the first chipset are packaged using an epoxy resin molding packaging process to obtain a first plastic packaging structure; Grinding the upper surface of the first plastic package structure until the other end of the first metal column is exposed to obtain a first packaging structure; Processing a second circuit layer on the second substrate by a redistribution layer process or a substrate bonding process; A plurality of second metal pillars having one end electrically connected to the second circuit layer are processed on the upper surface of the second circuit layer by through-molding via technology; Connecting the front surface of the second chipset to the upper surface of the second circuit layer through a chip bonding process on the second circuit layer; The second circuit layer, the second metal column and the second chipset are packaged by using an epoxy resin molding packaging process to obtain a second plastic packaging structure; Grinding the upper surface of the second plastic package structure until the other end of the second metal column is exposed, removing the second base substrate, and obtaining a second packaging structure; Invert the second packaging structure directly above the first packaging structure, electrically connect the other end of the first metal column and the other end of the second metal column, and bond the lower end surface of the second packaging structure to the upper end surface of the first packaging structure, then remove the first substrate to obtain a multi-chip substrate packaging structure.

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