Hybrid bonding structure based on interlocking structure and bonding method

Abstract

The invention provides a hybrid bonding structure and bonding method based on an interlocking structure, and the structure comprises a first chip to be bonded, which is provided with a first silicon oxide layer and a first copper connecting piece protruding out of the first silicon oxide layer; the second chip to be bonded is provided with a second silicon dioxide layer, a recess arranged in the second silicon dioxide layer and a second copper connecting piece arranged at the bottom of the recess, and the surface of the second copper connecting piece is provided with a first adhesion layer; the first chip to be bonded and the second chip to be bonded are configured as follows: before bonding, the height difference of the first copper connecting piece protruding out of the first silicon oxide layer is smaller than the height difference of the top surface of the first adhesion layer and the top surface of the second silicon oxide layer; the first silicon oxide layer is connected with the second silicon oxide layer, and the first copper connecting piece extends into the recess and is connected with the second copper connecting piece through the first adhesion layer to form an interlocking structure. The method is used for optimizing the performance of the hybrid bonding process and the bonding structure.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a hybrid bonding structure and a bonding method based on an interlocking structure. Background Art

[0002] As people's requirements for electronic products develop towards miniaturization, multi-function, and environmental protection, many new technologies, new materials, and new designs have emerged. Planar semiconductor devices are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of semiconductor devices approaches the physical limit, planar processes and manufacturing technologies become challenging and expensive. Three-dimensional stacked semiconductor device architectures can solve the density limitations in some planar semiconductor devices.

[0003] Among the various technologies used to stack semiconductor substrates, hybrid bonding (heterogeneous bonding) has become the focus of current three-dimensional integration technology research and development because it simultaneously connects circuit leads during the bonding process. For the hybrid bonding process, since the electrical connection between wafers must be achieved while completing wafer bonding, extremely high requirements are placed on the surface morphology of the bonded wafers, especially on the uniformity and consistency of the bonding interface process.

[0004] Taking the heterogeneous bonding process involving copper as an example, after preparing the Cu Pad for bonding, the surface Cu needs to be polished using the CMP process. However, according to the current industry requirements, the surface roughness of the dielectric layer after the CMP process polishing needs to be less than 0.5nm to facilitate the bonding of the dielectric layer, and there are also high requirements for the degree of concavity of the Cu Pad. Therefore, the above bonding method not only requires CMP equipment, but also has extremely high requirements for CMP equipment, which will greatly increase the difficulty of the entire preparation process. If the conditions of the above CMP process are not met, it will seriously affect the bonding yield, the performance and reliability of the bonded product. Summary of the invention

[0005] The object of the present invention is to provide a hybrid bonding structure and a bonding method based on an interlocking structure, so as to optimize the performance of the hybrid bonding process and the bonding structure.

[0006] In order to solve the above technical problems, the present invention provides a hybrid bonding structure based on an interlocking structure, comprising:

[0007] A first chip to be bonded, having a first silicon oxide layer and a first copper connector protruding from the first silicon oxide layer;

[0008] A second chip to be bonded has a second silicon oxide layer, a recess in the second silicon oxide layer, and a second copper connector at the bottom of the recess, and a first adhesion layer is provided on the surface of the second copper connector;

[0009] The first chip to be bonded and the second chip to be bonded are configured as follows: before bonding, the height difference of the first copper connector protruding from the first silicon oxide layer is smaller than the height difference between the top surface of the first adhesion layer and the top surface of the second silicon oxide layer; after bonding, the first silicon oxide layer is connected to the second silicon oxide layer and the first copper connector extends into the recess and is connected to the second copper connector via the first adhesion layer to form an interlocking structure.

[0010] Optionally, the recess matches the cross-sectional shape of the first copper connector, and before bonding, the cross-sectional dimension of the recess is larger than the cross-sectional dimension of the first copper connector.

[0011] Optionally, the material of the first adhesion layer includes titanium, and a titanium nitride layer and / or a titanium tungsten layer is further included between the first adhesion layer barrier layer and the second copper connector.

[0012] Optionally, the first chip to be bonded and / or the second chip to be bonded include a wafer to be bonded or a chip to be bonded.

[0013] According to another aspect of the present invention, a hybrid bonding method based on an interlocking structure is also provided, comprising:

[0014] Providing a first chip to be bonded, with a first silicon oxide layer on the surface of the first chip;

[0015] forming a plurality of protruding first copper connectors on the first silicon oxide layer;

[0016] providing a second chip to be bonded;

[0017] Forming a second silicon oxide layer having a recess on the second chip to be bonded, and forming a second copper connector and a first adhesion layer in the bottom of the recess, wherein the first adhesion layer covers the surface of the second copper connector, wherein the height difference of the first copper connector protruding from the first silicon oxide layer is smaller than the height difference between the top surface of the first adhesion layer and the top surface of the second silicon oxide layer;

[0018] Performing surface treatment on the first chip to be bonded and the second chip to be bonded, and performing thermocompression bonding on the first chip to be bonded and the second chip to be bonded at a first temperature, so that the first silicon oxide layer is connected to the second silicon oxide layer, and the first copper connector extends into the recess and retains a preset gap with the second copper connector;

[0019] The first chip to be bonded and the second chip to be bonded are annealed at a second temperature to connect the first copper connector to the second copper connector in the recess to form an interlocking structure, and the second temperature is greater than the first temperature.

[0020] Optionally, the step of forming a plurality of protruding first copper connectors on the first silicon oxide layer includes:

[0021] forming a second adhesion layer and a copper seed layer in sequence on the first silicon oxide layer;

[0022] forming a first patterned mask layer on the copper seed layer, the mask layer having a first opening exposing a portion of the copper seed layer;

[0023] Performing a chemical electroplating process to fill the first opening with a first copper layer;

[0024] The first patterned mask layer is removed, and a dry etching process is performed to remove the exposed copper seed layer and the second adhesion layer thereunder, with the remaining second adhesion layer, the copper seed layer and the first copper layer serving as the first copper connector.

[0025] Optionally, the step of forming the second silicon oxide layer, the second copper connector and the first adhesion layer includes:

[0026] forming a second silicon oxide layer on the surface of the second chip to be bonded;

[0027] forming a second patterned mask layer on the second silicon oxide layer, the second patterned mask layer having a second opening exposing a portion of the second silicon oxide layer, wherein the width of the second opening is greater than the width of the first opening;

[0028] Performing a dry etching process to expose a recess on the surface of the second chip to be bonded in the second silicon oxide layer;

[0029] Performing a physical vapor deposition process to sequentially form a second copper layer and a first adhesion layer in the recess;

[0030] The second patterned mask layer is removed, and the second copper layer in the recess is used as the second copper connector, wherein the height difference of the first copper connector protruding from the first silicon oxide layer is smaller than the height difference between the top surface of the first adhesion layer and the top surface of the second silicon oxide layer.

[0031] Optionally, the step of performing surface treatment on the first chip to be bonded and the second chip to be bonded includes:

[0032] Cleaning the first chip to be bonded and the second chip to be bonded with a weak acid to improve their hydrophilicity;

[0033] Plasma bombardment and / or ammonia soaking are used to remove the surface oxide of the first copper connector and the first adhesion layer and to improve the surface activity of the first silicon oxide layer and the second silicon oxide layer.

[0034] Optionally, the process parameters of the hot pressing bonding include: the first temperature is 100° C. to 150° C., the hot pressing time is 10 minutes to 30 minutes, and the hot pressing pressure is 300 Newtons to 700 Newtons.

[0035] Optionally, the process parameters of the annealing treatment include: the second temperature is 300° C. to 500° C., and the annealing time is 2.5 hours to 4 hours.

[0036] In summary, the present invention provides a hybrid bonding structure and bonding method based on an interlocking structure, wherein the hybrid bonding structure includes a first chip to be bonded and a second chip, wherein the first chip to be bonded has a first silicon oxide layer and a first copper connector protruding from the first silicon oxide layer, and the second chip to be bonded has a second silicon oxide layer, a recess provided in the second silicon oxide layer, and a second copper connector provided at the bottom of the recess, and the surface of the second copper connector is provided with a first adhesion layer, wherein the first chip to be bonded and the second chip to be bonded are configured as follows: before bonding, the height difference of the first copper connector protruding from the first silicon oxide layer is less than the height difference between the top surface of the first adhesion layer and the top surface of the second silicon oxide layer, and after bonding, the first silicon oxide layer is connected to the second silicon oxide layer and the first copper connector extends into the recess and is connected to the second copper connector using the first adhesion layer to form an interlocking structure. In the present invention, the first copper connector of the first chip is extended into the corresponding recess of the second chip to conveniently achieve non-misaligned alignment of the first chip and the second chip. Compared with direct copper-to-copper bonding, the present invention uses the first adhesive layer to connect the first copper connector and the second copper connector, which can reduce the bonding temperature and the requirements for copper surface flatness. Considering that the thermal expansion coefficient of copper is greater than the expansion coefficient of silicon oxide, a gap is reserved between the first copper connector and the first adhesive layer in the recess before bonding (the difference between the height difference of the first copper connector protruding from the first silicon oxide layer and the height difference between the top surface of the first adhesive layer and the top surface of the second silicon oxide layer). During hot pressing bonding and annealing, the first copper connector gradually expands to contact and connect with the first adhesive layer and the second copper connector, and basically fills the gap reserved between the first copper connector and the side wall and bottom of the recess before bonding to form an interlocking structure, which can improve the mechanical stability (mechanical strength) after bonding annealing, reduce bonding interface defects, prevent leakage current and other reliability problems caused by bonding interface defects, and thus reduce the stress of the first chip and the second chip after bonding annealing. Furthermore, no CMP step is required when preparing the connecting members for bonding on the first chip and the second chip, thereby completely avoiding the need for high-precision CMP equipment and CMP processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0038] Figure 1 It is a flow chart of a hybrid bonding method based on an interlocking structure provided by one embodiment of the present invention.

[0039] Figure 2a to Figure 2l A schematic structural diagram corresponding to corresponding steps of a hybrid bonding method based on an interlocking structure provided in one embodiment of the present invention.

[0040] In the accompanying drawings: 10-first chip; 11-first silicon oxide layer; 12-second adhesion layer; 13-copper seed layer; 14-first patterned mask layer; 15-first opening; 16-first copper layer; 17-first copper connector; H1-first height difference; 21-second chip; 22-second silicon oxide layer; 23-second patterned mask layer; 24-second opening; 25-recess; 26-second copper connector; 27-first adhesion layer; H2-second height difference. DETAILED DESCRIPTION

[0041] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0042] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0043] An embodiment of the present invention provides a hybrid bonding method based on an interlocking structure.

[0044] Figure 1 It is a flow chart of the hybrid bonding method based on the interlocking structure provided in this embodiment.

[0045] like Figure 1 As shown, the hybrid bonding method based on the interlocking structure provided in this embodiment includes:

[0046] S01: providing a first chip to be bonded, with a first silicon oxide layer disposed on the surface of the first chip;

[0047] S02: forming a plurality of protruding first copper connectors on the first silicon oxide layer;

[0048] S03: providing a second chip to be bonded;

[0049] S04: forming a second silicon oxide layer having a recess on the second chip to be bonded, and forming a second copper connector and a first adhesion layer in the bottom of the recess, wherein the first adhesion layer covers the surface of the second copper connector, wherein the height difference of the first copper connector protruding from the first silicon oxide layer is smaller than the height difference between the top surface of the first adhesion layer and the top surface of the second silicon oxide layer;

[0050] S05: performing surface treatment on the first chip to be bonded and the second chip to be bonded, and performing thermocompression bonding on the first chip to be bonded and the second chip to be bonded at a first temperature, so that the first silicon oxide layer is connected to the second silicon oxide layer, and the first copper connector extends into the recess and retains a preset gap with the second copper connector;

[0051] S06: performing an annealing treatment on the first chip to be bonded and the second chip to be bonded at a second temperature to connect the first copper connector to the second copper connector in the recess to form an interlocking structure, wherein the second temperature is greater than the first temperature.

[0052] Figure 2a to Figure 2i The schematic diagram of the structure corresponding to the corresponding steps of the hybrid bonding method based on the interlocking structure provided in this embodiment, and then Figure 2a to Figure 2i The hybrid bonding method based on the interlocking structure is described in detail.

[0053] First, please refer to Figure 2a , perform step S01, provide a first chip 10 to be bonded, and a first silicon oxide layer 11 is provided on the surface of the first chip 10.

[0054] The first chip 10 to be bonded can be a semiconductor structure to be bonded in a broad sense, such as a wafer to be bonded, an interposer with through-silicon vias, a semi-finished chip to be bonded, or a finished chip to be bonded. The first chip 10 has an area to be bonded (an area for bonding), the surface of which is a first silicon oxide layer 11, and the first silicon oxide layer 11 exposes an interconnection structure to be bonded (such as a plug or an interconnection line, not shown in the figure). Of course, if the material of the surface of the bonding area of ​​the first chip 10 is not silicon oxide, a vapor deposition process can be used to form the first silicon oxide layer 11 on its surface, and the interconnection structure to be bonded is exposed.

[0055] Next, step S02 is performed to form a plurality of protruding first copper connecting members 17 on the first silicon oxide layer 11 .

[0056] Please refer to Figure 2b , a second adhesion layer 12 and a copper seed layer 13 are sequentially formed on the first silicon oxide layer 11. The second adhesion layer 12 and the copper seed layer 13 can be sequentially formed on the surface of the first silicon oxide layer 11 by a physical vapor deposition process, the material of the second adhesion layer 12 can be metallic titanium, and a second barrier layer can be preferably formed between the second adhesion layer 12 and the copper seed layer 13, and the material of the second barrier layer can include titanium nitride and / or titanium tungsten.

[0057] Please refer to Figure 2c , a first patterned mask layer 14 is formed on the copper seed layer 13, and the first opening 15 exposes a portion of the copper seed layer 13. The first patterned mask layer 14 can be a patterned photoresist layer, and the first opening 15 exposes the copper seed layer 13 in the area corresponding to the interconnect structure to be bonded. The thickness of the first patterned mask layer 14 can be determined according to the height of the subsequent first copper connector 17, and the thickness of the first patterned mask layer 14 = the height of the first copper connector 17 - the thickness of the second adhesion layer 12 - the thickness of the copper seed layer 13.

[0058] Please refer to Figure 2d , a chemical plating process is performed to fill the first opening 15 with a first copper layer 16. The top surface of the first copper layer 16 may be substantially flush with or slightly exceed the thickness of the first patterned mask layer 14.

[0059] Please refer to Figure 2e , remove the first patterned mask layer 14, and perform a dry etching process to remove the exposed copper seed layer 13 and the second adhesion layer 12 thereunder, exposing the surface of the first silicon oxide layer 11, and use the remaining second adhesion layer 12, copper seed layer 13 and first copper layer 16 as the first copper connector 17, which electrically leads to the interconnection structure to be bonded to the first chip 10. The height difference of the first copper connector 17 protruding from the first silicon oxide layer 11 can be the first height difference H1.

[0060] Next, please refer to Figure 2f , execute step S03 to provide a second chip 21 to be bonded.

[0061] The second chip 21 may be a semiconductor structure that matches and is bonded to the first chip 10. The second chip 21 has a region to be bonded (region for bonding), the surface of which is an insulating dielectric layer, and an interconnection structure to be bonded (such as a plug or an interconnection line, not shown in the figure) is exposed in the insulating dielectric layer.

[0062] Next, step S04 is performed to form a second silicon oxide layer 22 having a recess 25 on the second chip 21 to be bonded, and a second copper connector 26 and a first adhesion layer 27 are formed at the bottom of the recess 25, wherein the first adhesion layer 27 covers the surface of the second copper connector 26, wherein the height difference of the first copper connector 17 protruding from the first silicon oxide layer 11 is smaller than the height difference between the top surface of the first adhesion layer 27 and the top surface of the second silicon oxide layer 22.

[0063] Please refer to Figure 2g , a second silicon oxide layer 22 is formed on the surface of the second chip 21 to be bonded. The second silicon oxide layer 22 can be formed on the surface of the to-be-bonded region of the second chip 21 by, for example, a vapor deposition process, and its thickness determines the depth of the subsequent recess 25 and can match the protruding height of the first copper connector 17. In this embodiment, under the premise that the sum of the thickness of the second copper connector 26 and the first adhesion layer 27 is substantially the same as the sum of the thickness of the second adhesion layer 12 and the copper seed layer 13, the thickness of the second silicon oxide layer 22 can be slightly greater than the thickness of the first patterned mask layer 14, for example, 50 nanometers to 500 nanometers greater.

[0064] Please refer to Figure 2h , a second patterned mask layer 23 is formed on the second silicon oxide layer 22, which has a second opening 24 exposing a partial area of ​​the second silicon oxide layer 22, and the width of the second opening 24 is greater than the width of the first opening 15, and a dry etching process is performed to expose a recess 25 on the surface of the second chip 21 to be bonded in the second silicon oxide layer 22. The shape and size of the recess 25 are the same as the shape and size of the second opening 24, and the bottom of the recess 25 exposes the interconnection structure of the second chip 21 to be bonded. It should be noted that the cross-sectional shape of the second opening 24 matches the cross-sectional shape of the first opening 15, for example, both are rectangular, but the size (width) of the second opening 24 is slightly larger than the size (width) of the first opening 15.

[0065] Please refer to Figure 2i, perform a physical vapor deposition process, and sequentially form a second copper layer and a first adhesion layer 27 at the bottom of the recess 25. The second copper layer and the first adhesion layer 27 may be sequentially formed by a physical vapor deposition process, and the material of the first adhesion layer 27 may be metal titanium. A first barrier layer may be preferably formed between the second copper layer and the first adhesion layer 27, and the material of the first barrier layer may include titanium nitride and / or titanium tungsten. Of course, it is also feasible to form a very small amount of the second copper layer and the first adhesion layer 27 on the sidewall of the recess 25.

[0066] Please refer to Figure 2j , remove the second patterned mask layer 23, expose the surface of the second silicon oxide layer 22, and use the second copper layer in the recess 25 as the second copper connector 26, the height difference of the first copper connector 17 protruding from the first silicon oxide layer 11 is less than the height difference between the top surface of the first adhesion layer 27 and the top surface of the second silicon oxide layer 22. The second copper connector 26 and the first adhesion layer 27 electrically lead out the interconnection structure to be bonded and connected to the second chip 21. Among them, the height difference between the top surface of the first adhesion layer 27 and the top surface of the second silicon oxide layer 22 can be a second height difference H2, and the second height difference H2 is slightly larger than the first height difference H1, for example, 50 nanometers to 500 nanometers larger. Of course, the second copper connector 26 and the first adhesion layer 27 formed by the above-mentioned physical vapor deposition process also cover the surface of the second patterned mask layer 23. When the second patterned mask layer 23 is removed, the redundant second copper connector 26 and the first adhesion layer 27 on its surface are also removed, and only the second copper connector 26 and the first adhesion layer 27 in the recess 25 are retained.

[0067] Next, please refer to Figure 2k , execute step S05, perform surface treatment on the first chip 10 to be bonded and the second chip 21 to be bonded, and perform hot compression bonding on the first chip 10 to be bonded and the second chip 21 to be bonded at a first temperature, so that the first silicon oxide layer 11 is connected to the second silicon oxide layer 22, and the first copper connector 17 extends into the recess 25 and retains a preset gap with the second copper connector 26.

[0068] Among them, the step of surface treatment of the first chip 10 to be bonded and the second chip 21 to be bonded includes: using weak acid to clean the first chip 10 to be bonded and the second chip 21 to be bonded to improve their hydrophilicity; using plasma bombardment and / or ammonia water soaking the first chip 10 to be bonded and the second chip 21 to be bonded to remove the surface oxide of the first copper connector 17 and the first adhesion layer 27 and improve the surface activity of the first silicon oxide layer 11 and the second silicon oxide layer 22. In specific implementation, at least part of the above surface treatment steps can be selected according to actual needs. When the first chip 10 to be bonded is surface treated, low-concentration citric acid can be used for cleaning to reduce the contact angle and improve the hydrophilicity, and then a mixed gas of argon and nitrogen can be used for bombardment to remove the oxide layer on the surface of the first copper connector 17, and then 10% to 50% ammonia water can be used for soaking for 2 minutes to 5 minutes to improve the surface activity of the first silicon oxide layer 11. When performing surface treatment on the second chip 21 to be bonded, a mixed gas of argon and nitrogen may be used to bombard the second silicon oxide layer 22 and the first adhesion layer 27 to increase the surface activity of the second silicon oxide layer 22 and reduce the oxide content on the surface of the first adhesion layer 27 in the recess 25 .

[0069] Before bonding, the first copper connector 17 of the first chip 10 is extended into the corresponding recess 25 of the second chip 21 (similar to interlocking) to conveniently realize the non-misaligned alignment of the first chip 10 and the second chip 21. Then, the first chip 10 and the second chip 21 are subjected to thermocompression bonding, and the process parameters include: the first temperature (thermocompression temperature) is 100°C to 150°C, the thermocompression time is 10 minutes to 30 minutes, and the thermocompression pressure is 300 Newtons to 700 Newtons. It should be particularly noted that the thermocompression bonding step is mainly to make the aligned first silicon oxide layer 11 and the second silicon oxide layer 22 perform preliminary bonding connection, and at this time, the first copper connector 17 extends into the recess 25 and is not connected to the first adhesive layer 27 on the second copper connector 26. In other words, before and after the thermocompression bonding, the first copper connector 17 and the bottom of the recess 25 (the first adhesive layer 27) retain a preset gap, and the first copper connector 17 and the side wall of the recess 25 also retain a gap. The reserved gap between the first copper connector 17 and the first adhesion layer 27 may be approximately the difference between the first height difference H1 and the second height difference H2, and the gap between the first copper connector 17 and the side wall of the recess 25 may be approximately half of the difference between the widths of the first opening 14 and the second opening 24. Of course, the above gaps are determined by the size (height and width) of the first copper connector 17 and the difference in thermal expansion coefficients of copper and silicon oxide layers.

[0070] Next, please refer to Figure 2l, execute step S06, perform annealing treatment on the first chip 10 to be bonded and the second chip 21 to be bonded at a second temperature, so that the first copper connector 17 is connected to the second copper connector 26 in the recess 25 to form an interlocking structure, and the second temperature is greater than the first temperature.

[0071] The annealing process may be a furnace tube annealing process, the annealing temperature (second temperature) may be 300° C. to 500° C., and the annealing time may be 2.5 hours to 4 hours.

[0072] The annealing process can not only strengthen the connection between the first silicon oxide layer 11 and the second silicon oxide layer 22, but also connect the first copper connector 17 to the second copper connector 26 using the first adhesion layer 27. Compared with direct bonding between copper and copper, the bonding temperature and the requirements for the flatness of the copper surface can be reduced by connecting using the first adhesion layer 27. In the above connection process (annealing process), considering that the thermal expansion coefficient of copper is greater than the expansion coefficient of silicon oxide, the first copper connector 17 gradually expands to contact and connect with the first adhesion layer 27 and the second copper connector 26, and basically fills the gap reserved by the side wall and bottom of the first copper connector 17 and the recess 25 before the annealing process to form an interlocking structure, which can improve the mechanical stability (mechanical strength) after bonding annealing, reduce bonding interface defects, prevent leakage current and other reliability problems caused by bonding interface defects, and thus reduce the stress of the first chip 10 and the second chip 21 after bonding annealing.

[0073] It is worth mentioning that when preparing the connection parts for bonding on the first chip 10 and the second chip 21, no CMP step is required at all, which completely avoids the need for high-precision CMP equipment and CMP process, and thereby simplifies the process flow and reduces the process complexity, thereby facilitating stable, reliable and high-performance interconnection. It can be seen from the above connection process that even if the top surface morphology of the first copper connection part 17 and / or the top morphology of the first adhesion layer 27 are uneven, the first copper connection part 17 and the first adhesion layer 27 can be confined to the corresponding recess 25 and contact and connect under high-temperature expansion. In other words, the top surface morphology of the first copper connection part 17 and / or the top morphology of the first adhesion layer 27 do not affect the bonding connection between the two in the recess 25.

[0074] Of course, the above-mentioned hot pressing bonding and annealing treatment can also be regarded as a bonding process. In some examples, the above-mentioned annealing step can also be combined into a special hot pressing bonding step, that is, the special hot pressing bonding has the above-mentioned annealing function. In other words, the special hot pressing bonding has a hot pressing temperature of a third temperature, the third temperature is between the first temperature and the second temperature, and the hot pressing time is greater than the above-mentioned hot pressing time.

[0075] This embodiment also provides a hybrid bonding structure based on an interlocking structure.

[0076] Figure 2e is a schematic structural diagram of the first chip to be bonded, Figure 2j FIG. 4 is a schematic diagram of the structure of the second chip to be bonded.

[0077] like Figure 2e and Figure 2j As shown, the hybrid bonding structure based on the interlocking structure provided in this embodiment includes a first chip 10 to be bonded and a second chip 21 to be bonded, both of which are semiconductor structures to be bonded in a broad sense, and may include, for example, a wafer to be bonded, an interposer with through-silicon vias, a semi-finished chip to be bonded, or a finished chip to be bonded. The first chip 10 and the second chip 21 each have a region to be bonded, in which an interconnection structure to be bonded (such as a plug or an interconnection line, not shown in the figure) is exposed.

[0078] like Figure 2e As shown, the surface of the area to be bonded of the first chip 10 is a first silicon oxide layer 11, and there are a number of protruding and spaced first copper connectors 17 on the first silicon oxide layer 11, each of which is connected to each interconnection structure to be bonded in the first chip 10. The first copper connector 17 may include a second adhesion layer 12, a copper seed layer 13 and a first copper layer 16 stacked in sequence from bottom to top, and a second barrier layer may be provided between the second adhesion layer 12 and the copper seed layer 13. The material of the second adhesion layer 12 may be metal titanium, and the material of the second barrier layer may include titanium nitride and / or titanium tungsten. Among them, the first copper connector 17 protrudes from the height of the surface of the first silicon oxide layer 11, that is, the height difference between the top surface of the first copper connector 17 and the surface of the first silicon oxide layer 11 may be a first height difference H1.

[0079] like Figure 2j As shown, the surface of the area to be bonded of the second chip 21 is a second silicon oxide layer 22, and the second silicon oxide layer 22 has a plurality of recesses 25 exposing the interconnection structure to be bonded and connected to the second chip 21, and the positions of these recesses 25 match the corresponding first copper connector 17 on the first chip 10. The bottom of the recess 25, that is, the interconnection structure to be bonded and connected to the second chip 21, is sequentially provided with a second copper connector 26 and a first adhesion layer 27, and the material of the first adhesion layer 27 may include titanium, and a first barrier layer may be provided between the first adhesion layer 27 and the second copper connector 26, and the material of the first barrier layer may include titanium nitride and / or titanium tungsten. The cross-sectional shape of the recess 25 is the same as the cross-sectional shape of the first copper connector 17, but the cross-sectional size (width) of the recess 25 is slightly larger than the cross-sectional size (width) of the first copper connector 17, and the height difference between the top surface of the first adhesion layer 27 in the recess 25 and the surface of the second silicon oxide layer 22 may be a second height difference H2.

[0080] The second height difference H2 is greater than the first height difference H1, and the difference between the second height difference H2 and the first height difference H1 is the reserved gap between the first copper connector 17 and the first adhesive layer 27 after the first copper connector 17 extends into the recess 25, which can be determined by the size (height and width) of the first copper connector 17 and the difference in thermal expansion coefficients between copper and silicon oxide layers. In other words, after the first chip 10 and the second chip 21 are aligned, the first silicon oxide layer 11 is in contact with the second silicon oxide layer 22, and the first copper connector 17 is not in contact with the first adhesive layer 27 after extending into the recess 25. The first copper connector 17 gradually expands to contact with the first adhesive layer 27 during the hot pressing bonding and annealing process and forms an electrical connection with the second copper connector 26, thereby filling the reserved gap between the first copper connector 17 and the first adhesive layer 27 and the gap with the side wall of the recess 25, and thus forming an interlocking structure.

[0081] In a specific example, the height of the first copper connection member 17 (the first height difference H1 ) may be 1500 nanometers to 3000 nanometers, and the second height difference H2 may be 100 nanometers to 300 nanometers greater than the first height difference H1 .

[0082] In summary, the present invention provides a hybrid bonding structure and bonding method based on an interlocking structure, wherein the hybrid bonding structure includes a first chip to be bonded and a second chip, wherein the first chip to be bonded has a first silicon oxide layer and a first copper connector protruding from the first silicon oxide layer, and the second chip to be bonded has a second silicon oxide layer, a recess provided in the second silicon oxide layer, and a second copper connector provided at the bottom of the recess, and the surface of the second copper connector is provided with a first adhesion layer, wherein the first chip to be bonded and the second chip to be bonded are configured as follows: before bonding, the height difference of the first copper connector protruding from the first silicon oxide layer is less than the height difference between the top surface of the first adhesion layer and the top surface of the second silicon oxide layer, and after bonding, the first silicon oxide layer is connected to the second silicon oxide layer and the first copper connector extends into the recess and is connected to the second copper connector using the first adhesion layer to form an interlocking structure. In the present invention, the first copper connector of the first chip is extended into the corresponding recess of the second chip to conveniently achieve non-misaligned alignment of the first chip and the second chip. Compared with direct copper-to-copper bonding, the present invention uses the first adhesive layer to connect the first copper connector and the second copper connector, which can reduce the bonding temperature and the requirements for copper surface flatness. Considering that the thermal expansion coefficient of copper is greater than the expansion coefficient of silicon oxide, a gap is reserved between the first copper connector and the first adhesive layer in the recess before bonding (the difference between the height difference of the first copper connector protruding from the first silicon oxide layer and the height difference between the top surface of the first adhesive layer and the top surface of the second silicon oxide layer). During hot pressing bonding and annealing, the first copper connector gradually expands to contact and connect with the first adhesive layer and the second copper connector, and basically fills the gap reserved between the first copper connector and the side wall and bottom of the recess before bonding to form an interlocking structure, which can improve the mechanical stability (mechanical strength) after bonding annealing, reduce bonding interface defects, prevent leakage current and other reliability problems caused by bonding interface defects, and thus reduce the stress of the first chip and the second chip after bonding annealing. Furthermore, no CMP step is required when preparing the connecting members for bonding on the first chip and the second chip, thereby completely avoiding the need for high-precision CMP equipment and CMP processes.

[0083] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A hybrid bonding structure based on an interlocking structure, characterized in that: include: A first chip to be bonded, having a first silicon oxide layer and a first copper connector protruding from the first silicon oxide layer; A second chip to be bonded has a second silicon oxide layer, a recess in the second silicon oxide layer, and a second copper connector at the bottom of the recess, and a first adhesion layer is provided on the surface of the second copper connector; The first chip to be bonded and the second chip to be bonded are configured as follows: before bonding, the height difference of the first copper connector protruding from the first silicon oxide layer is smaller than the height difference between the top surface of the first adhesion layer and the top surface of the second silicon oxide layer; after bonding, the first silicon oxide layer is connected to the second silicon oxide layer and the first copper connector extends into the recess and is connected to the second copper connector via the first adhesion layer to form an interlocking structure.

2. The hybrid bonding structure based on the interlocking structure according to claim 1, characterized in that: The recess matches the cross-sectional shape of the first copper connector, and before bonding, the cross-sectional dimension of the recess is larger than the cross-sectional dimension of the first copper connector.

3. The hybrid bonding structure based on the interlocking structure according to claim 1, characterized in that: The material of the first adhesion layer includes titanium, and a titanium nitride layer and / or a titanium tungsten layer is further included between the first adhesion layer barrier layer and the second copper connector.

4. The hybrid bonding structure based on the interlocking structure according to claim 1, characterized in that: The first chip to be bonded and / or the second chip to be bonded include a wafer to be bonded or a chip to be bonded.

5. A hybrid bonding method based on an interlocking structure, characterized in that: include: Providing a first chip to be bonded, with a first silicon oxide layer on the surface of the first chip; forming a plurality of protruding first copper connectors on the first silicon oxide layer; providing a second chip to be bonded; Forming a second silicon oxide layer having a recess on the second chip to be bonded, and forming a second copper connector and a first adhesion layer in the bottom of the recess, wherein the first adhesion layer covers the surface of the second copper connector, wherein the height difference of the first copper connector protruding from the first silicon oxide layer is smaller than the height difference between the top surface of the first adhesion layer and the top surface of the second silicon oxide layer; Performing surface treatment on the first chip to be bonded and the second chip to be bonded, and performing thermocompression bonding on the first chip to be bonded and the second chip to be bonded at a first temperature, so that the first silicon oxide layer is connected to the second silicon oxide layer, and the first copper connector extends into the recess and retains a preset gap with the second copper connector; The first chip to be bonded and the second chip to be bonded are annealed at a second temperature to connect the first copper connector to the second copper connector in the recess to form an interlocking structure, and the second temperature is greater than the first temperature.

6. The hybrid bonding method based on interlocking structure according to claim 5, characterized in that: The step of forming a plurality of protruding first copper connectors on the first silicon oxide layer comprises: forming a second adhesion layer and a copper seed layer in sequence on the first silicon oxide layer; forming a first patterned mask layer on the copper seed layer, the mask layer having a first opening exposing a portion of the copper seed layer; Performing a chemical electroplating process to fill the first opening with a first copper layer; The first patterned mask layer is removed, and a dry etching process is performed to remove the exposed copper seed layer and the second adhesion layer thereunder, with the remaining second adhesion layer, the copper seed layer and the first copper layer serving as the first copper connector.

7. The hybrid bonding method based on interlocking structure according to claim 6, characterized in that: The steps of forming the second silicon oxide layer, the second copper connector and the first adhesion layer include: forming a second silicon oxide layer on the surface of the second chip to be bonded; forming a second patterned mask layer on the second silicon oxide layer, the second patterned mask layer having a second opening exposing a portion of the second silicon oxide layer, wherein the width of the second opening is greater than the width of the first opening; Performing a dry etching process to expose a recess on the surface of the second chip to be bonded in the second silicon oxide layer; Performing a physical vapor deposition process to sequentially form a second copper layer and a first adhesion layer in the recess; The second patterned mask layer is removed, and the second copper layer in the recess is used as the second copper connector, wherein the height difference of the first copper connector protruding from the first silicon oxide layer is smaller than the height difference between the top surface of the first adhesion layer and the top surface of the second silicon oxide layer.

8. The hybrid bonding method based on interlocking structure according to claim 5, characterized in that: The step of performing surface treatment on the first chip to be bonded and the second chip to be bonded comprises: Cleaning the first chip to be bonded and the second chip to be bonded with a weak acid to improve their hydrophilicity; Plasma bombardment and / or ammonia soaking are used to remove the surface oxide of the first copper connector and the first adhesion layer and to improve the surface activity of the first silicon oxide layer and the second silicon oxide layer.

9. The hybrid bonding method based on interlocking structure according to claim 5, characterized in that: The process parameters of the hot pressing bonding include: the first temperature is 100° C. to 150° C., the hot pressing time is 10 minutes to 30 minutes, and the hot pressing pressure is 300 Newtons to 700 Newtons.

10. The hybrid bonding method based on interlocking structure according to claim 5, characterized in that: The process parameters of the annealing treatment include: the second temperature is 300° C. to 500° C., and the annealing time is 2.5 hours to 4 hours.

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