Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises the components of a semiconductor substrate which is provided with a first surface and a second surface which are opposite; the inductance dielectric layer extends into the semiconductor substrate from the first surface; the capacitor dielectric layer is located on the first surface; the inductor is located on the inductor dielectric layer; the conductive layer is located on the capacitor dielectric layer; the back electrode is located on the second surface, and the conductive layer, the capacitor dielectric layer and the back electrode can be used for forming a capacitor. According to the semiconductor device, the thicker inductance dielectric layer is arranged in the semiconductor substrate, and the thinner capacitance dielectric layer is arranged on the first surface of the semiconductor substrate, so that the consistency of electrical parameters of the semiconductor device is improved while the thickness differentiation design of the inductance dielectric layer and the capacitance dielectric layer is considered.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor device manufacturing, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] LC network is an important component of electronic circuits, and its design theory and application are the basis of electronic engineering and radio frequency wireless communication technology. LC network usually refers to a circuit containing inductor (L) and capacitor (C) components, which can be combined in series or parallel to form an LC resonant circuit. LC resonant circuits have a wide range of applications in the fields of electronics and communications, such as signal filtering, frequency selection, oscillator design, etc. In the design of radio frequency circuits, it is usually necessary to set a combination circuit consisting of multiple inductors and capacitors around a functional unit to achieve the frequency characteristics of the circuit.

[0003] With the development and progress of microelectronics manufacturing technology, it is now possible to use semiconductor processes to produce inductor and capacitor components. Figure 1 and Figure 2 As shown, a dielectric layer 110 is formed on the upper surface of a semiconductor material substrate 101, and an inductor metal layer 120 and a metal pad (not shown) and other structures are formed on the dielectric layer 110. Since the substrate 101 is conductive, if the inductor metal layer 120 is directly formed on the substrate 101, the loss of the substrate 101 will make it difficult for the inductor to obtain a high Q value (quality factor), so the dielectric layer 110 is required to isolate the substrate 101 and the inductor metal layer 120. Since the thicker the dielectric layer 110 is, the smaller the loss caused by the substrate 101 is, the thickness of the dielectric layer 110 will be increased as much as possible during design to reduce the loss caused by the substrate 101. Figure 3 As shown, an upper electrode 210 and a lower electrode 220 of a capacitor are formed on the upper and lower surfaces of a semiconductor material substrate 201, respectively, and a dielectric layer 230 is provided between the upper surface of the substrate 201 and the upper electrode 210 of the capacitor. Since the capacitance of a capacitor is related to the distance between the upper electrode 210 and the lower electrode 220, the smaller the thickness of the dielectric layer 230 between the upper electrode 210 and the lower electrode 220, the larger the capacitance. Therefore, the thickness of the dielectric layer 230 is minimized as much as possible during design to increase the capacitance. Such inductors and capacitors made on different substrates will undoubtedly occupy a large area or space when used in combination, which is not only difficult to meet the requirements of electronic circuit integration and miniaturization, but also because the two need to be connected through an external electrical connection, which increases the complexity of assembly and also reduces reliability.

[0004] If the inductor and capacitor are integrated on the same substrate, there is a contradiction in the design of the dielectric layer thickness. Therefore, it is necessary to first deposit a thick dielectric layer on the substrate, and then use the photolithography + etching process to thin the thick dielectric layer in the capacitor area. However, during the etching of the dielectric layer, substrate damage and / or dielectric residue at the edge of the wafer may occur, which in turn leads to poor consistency of electrical parameters, low product yield, and high production costs. Summary of the invention

[0005] In view of this, the present disclosure provides a semiconductor device and a method for manufacturing the same, which improves the consistency of electrical parameters of the semiconductor device while taking into account the differentiated design of dielectric layer thicknesses of inductors and capacitors.

[0006] According to one aspect of an embodiment of the present disclosure, there is provided a semiconductor device, including:

[0007] A semiconductor substrate having a first surface and a second surface opposite to each other;

[0008] an inductive dielectric layer extending from the first surface into the semiconductor substrate;

[0009] A capacitor dielectric layer, located on the first surface;

[0010] an inductor, located on the inductor dielectric layer;

[0011] A conductive layer, located on the capacitor dielectric layer; and

[0012] a back electrode, located on the second surface,

[0013] The conductive layer, the capacitor dielectric layer and the back electrode can be used to form a capacitor.

[0014] Optionally, the capacitor dielectric layer covers the inductor dielectric layer.

[0015] The inductor and the conductive layer are both located on the surface of the capacitor dielectric layer.

[0016] Optionally, an upper surface of the inductive dielectric layer is coplanar with the first surface.

[0017] Optionally, the inductor is in the shape of a vortex strip, having an inner end located at the center of the vortex and an outer end located outside the vortex,

[0018] The conductive layer includes a first capacitor layer connected to the outer end.

[0019] Optionally, it also includes:

[0020] An interlayer dielectric layer, covering the capacitor dielectric layer, the inductor and the conductive layer;

[0021] A plurality of connecting pillars, penetrating the interlayer dielectric layer; and

[0022] A connecting portion, located on the interlayer dielectric layer,

[0023] Wherein, the conductive layer further includes the second capacitor layer, which is separated from the inductor.

[0024] The second capacitor layer is connected to the inner end portion through the corresponding connecting column and the connecting portion.

[0025] Optionally, the second capacitor layer includes a main body and an inductor connecting portion that are connected, that is, the main body and the inductor connecting portion are connected.

[0026] The orthographic projection of the body on the plane where the first surface is located falls outside the orthographic projection of the inductive dielectric layer on the plane,

[0027] The orthographic projection of the inductor connecting portion on the plane falls within the orthographic projection of the inductor dielectric layer on the plane.

[0028] The body is connected to the inner end portion via the inductor connecting portion, the corresponding connecting column and the connecting portion.

[0029] Optionally, it further includes a first electrode and a second electrode located on the interlayer dielectric layer, wherein the first electrode, the second electrode and the connecting portion are separated from each other.

[0030] Wherein, the first electrode is connected to the first capacitor layer through the corresponding connecting column,

[0031] The second electrode is connected to the second capacitor layer through the corresponding connecting column.

[0032] Optionally, there are multiple inductors.

[0033] And / or, the conductive layer further includes a plurality of third capacitor layers.

[0034] Optionally, the thickness of the capacitor dielectric layer is smaller than the thickness of the inductor dielectric layer.

[0035] Optionally, the thickness of the inductor dielectric layer is not less than 5 micrometers, and the thickness of the capacitor dielectric layer is not more than 1 micrometer.

[0036] According to another aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising:

[0037] forming an inductive dielectric layer in a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, and the inductive dielectric layer extends from the first surface into the semiconductor substrate;

[0038] forming a capacitor dielectric layer on the first surface;

[0039] forming an inductor on the inductor dielectric layer;

[0040] forming a conductive layer on the capacitor dielectric layer; and

[0041] forming a back electrode on the second surface,

[0042] The conductive layer, the capacitor dielectric layer and the back electrode can be used to form a capacitor.

[0043] Optionally, the step of forming an inductive dielectric layer in the semiconductor substrate includes:

[0044] forming a patterned barrier layer on the first surface;

[0045] forming an inductive isolation trench extending from the first surface into the semiconductor substrate; and

[0046] Depositing a dielectric layer on the barrier layer and in the inductor isolation groove;

[0047] Grinding and removing the dielectric layer on the barrier layer, and the dielectric layer located in the inductor isolation groove serves as the inductor dielectric layer; and

[0048] removing the barrier layer,

[0049] The barrier layer serves as a stop layer in the grinding step.

[0050] Optionally, the step of forming an inductive dielectric layer in the semiconductor substrate includes:

[0051] forming a patterned barrier layer on the first surface;

[0052] forming a plurality of trenches extending from the first surface into the semiconductor substrate; and

[0053] Oxidizing the semiconductor substrate until the oxide fills the trench to form the inductive dielectric layer; and

[0054] The barrier layer is removed.

[0055] One of the above technical solutions has the following beneficial effects:

[0056] By setting the inductor dielectric layer in the semiconductor substrate and setting the inductor on the inductor dielectric layer, electrical isolation between the inductor and the semiconductor substrate is achieved; by setting the capacitor dielectric layer on the first surface of the semiconductor substrate, the thickness of the inductor dielectric layer can be adjusted according to the extension depth in the semiconductor substrate, and the thickness of the capacitor dielectric layer can be adjusted according to the parameters of the deposition or oxidation process, so that a thinner capacitor dielectric layer can be formed without etching and thinning, thereby taking into account the differentiated design of the dielectric layer thickness of the inductor and capacitor, while improving the consistency of the electrical parameters of the semiconductor device.

[0057] In some embodiments, the capacitor dielectric layer covers the inductor dielectric layer, and the inductor and the conductive layer are both located on the surface of the capacitor dielectric layer. For the inductor, the capacitor dielectric layer also participates in the isolation between the inductor and the semiconductor substrate, increasing the isolation thickness and further improving the Q value of the inductor. At the same time, the inductor and the conductive layer located on the same layer can be photolithographically and etched at the same time, thereby simplifying the process and saving costs.

[0058] In some embodiments, the upper surface of the inductive dielectric layer is coplanar with the first surface of the semiconductor substrate, so that the capacitive dielectric layer formed on the surface is more flat, which is beneficial to the yield of the device.

[0059] In some embodiments, the second capacitor layer includes a connected body and an inductor connecting part, wherein the inductor connecting part is arranged directly above the inductor dielectric layer, the body is arranged on the outside of the inductor dielectric layer, connecting columns are respectively arranged on the inductor connecting part and the inner end of the swirl strip inductor, and the connecting columns are connected through a connecting part located on the interlayer dielectric layer, thereby realizing electrical connection between the inner end of the inductor and the second capacitor layer.

[0060] In some embodiments, a first electrode and a second electrode are disposed on the interlayer dielectric layer, and the first electrode and the second electrode are connected to the first capacitor layer and the second capacitor layer through corresponding connecting columns, respectively. When the first capacitor layer and the second capacitor layer are used as the upper electrodes of the capacitor, the first electrode and the second electrode can be used as the lead pads of the upper electrode of the capacitor, and can also be used as the two electrodes of the inductor. In addition, the first electrode and the second electrode can also be used as the upper electrodes of the capacitor as needed, so as to realize the application of different capacitance values.

[0061] In some embodiments, the area of ​​the conductive layer is increased by providing multiple third capacitor layers to achieve integration of multiple capacitors. The number of inductor patterns in the conductive layer may also be increased as needed to adjust the inductance value.

[0062] In some embodiments, a plurality of grooves are first formed in a semiconductor substrate, and then the semiconductor substrate is oxidized until the grooves are filled with oxide to form an inductor dielectric layer. Compared with forming the inductor dielectric layer by etching grooves + deposition + grinding to remove excess dielectric layers, the inductor dielectric layer is formed by etching grooves + oxidation filling, which can save the step of grinding to remove excess dielectric layers. At the same time, the semiconductor substrate located in the capacitor region avoids the influence of uneven film thickness within the chip caused by the grinding step, thereby avoiding residue when removing the barrier layer, thereby making the capacitor dielectric layer formed on the first surface of the semiconductor substrate uniform, thereby improving the consistency and stability of the capacitance value.

[0063] In some embodiments, a capacitor dielectric layer is formed on the first surface using a dry oxygen oxidation process, which can increase the compactness of the capacitor dielectric layer and the compactness of the surface of the inductor dielectric layer, which is beneficial to the yield of the device.

[0064] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0066] Figure 1 A schematic diagram of a top view of a semiconductor device including an inductor in the related art is shown.

[0067] Figure 2 Shown along Figure 1 Cross-sectional view taken along line AA.

[0068] Figure 3 A schematic structural diagram of a semiconductor device including a capacitor in the related art is shown.

[0069] Figure 4 A schematic diagram of the three-dimensional structure of a semiconductor device in the first embodiment of the present disclosure is shown.

[0070] Figure 5 Shows Figure 4 Schematic diagram of the top view structure.

[0071] Figure 6 Shown along Figure 5 Cross-sectional view taken along line BB.

[0072] Figures 7 to 17 Cross-sectional views showing some stages of a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure are shown.

[0073] Fig.18A schematic top view of the structure of a semiconductor device according to a second embodiment of the present disclosure is shown.

[0074] Fig.19 A schematic top view of the structure of a semiconductor device according to a third embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0075] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements or parts are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, a semiconductor structure obtained after several steps can be described in one figure.

[0076] Figure 4 FIG. 1 shows a schematic diagram of the three-dimensional structure of a semiconductor device in the first embodiment of the present disclosure. Figure 5 Shows Figure 4 A top view of the structure. Figure 6 Shown along Figure 5 The cross-sectional view taken along line BB, where: Figure 4 The interlayer dielectric layer, the first electrode, the second electrode and the corresponding connecting pillars are not shown in the figure. The X-axis, Y-axis and Z-axis directions represent the length direction, width direction and height direction of the device respectively.

[0077] like Figures 4 to 6 As shown, the semiconductor device in the first embodiment of the present disclosure includes: a semiconductor substrate 10, an inductor dielectric layer 12, a capacitor dielectric layer 13, an inductor 14, a conductive layer, an interlayer dielectric layer 16, a plurality of connecting pillars 17, a first electrode 18, a second electrode 19, a connecting portion 20 and a back electrode 21, wherein the conductive layer includes a first capacitor layer 15a and a second capacitor layer 15b.

[0078] The semiconductor substrate 10 has a first surface 10a and a second surface 10b opposite to each other. The material of the semiconductor substrate 10 is, for example, silicon, silicon carbide, etc.

[0079] The inductive dielectric layer 12 extends from the first surface 10a of the semiconductor substrate 10 into the semiconductor substrate 10 . The material of the inductive dielectric layer 12 is, for example, silicon oxide, silicon nitride, etc. Optionally, the upper surface of the inductive dielectric layer 12 is coplanar with the first surface 10a of the semiconductor substrate 10 .

[0080] The capacitor dielectric layer 13 is located on the first surface 10a of the semiconductor substrate 10. In this embodiment, the capacitor dielectric layer 13 covers the inductor dielectric layer 12. Optionally, the thickness of the capacitor dielectric layer 13 is less than the thickness of the inductor dielectric layer 12, wherein the thickness of the inductor dielectric layer 12 is not less than 5 microns, and the thickness of the capacitor dielectric layer 13 is not greater than 1 micron. In some other embodiments, the capacitor dielectric layer 13 may not cover the inductor dielectric layer 12.

[0081] The inductor 14 and the conductive layer are both located on the capacitor dielectric layer 13, wherein the inductor 14 is located directly above the inductor dielectric layer 12. In this embodiment, the inductor 14 is in the shape of a vortex strip, having an inner end located at the center of the vortex and an outer end located outside the vortex.

[0082] Along the X-axis direction, the first capacitor layer 15a and the second capacitor layer 15b are respectively located on both sides of the inductor 14. The first capacitor layer 15a is connected to the outer end of the inductor 14, and the second capacitor layer 15b is separated from the inductor 14. The second capacitor layer 15b includes a connected body 15b1 and an inductor connecting portion 15b2, the orthographic projection of the body 15b1 on the plane where the first surface 10a of the semiconductor substrate 10 is located falls outside the orthographic projection of the inductor dielectric layer 12 on the plane, and the orthographic projection of the inductor connecting portion 15b2 on the plane falls within the orthographic projection of the inductor dielectric layer 12 on the plane.

[0083] The interlayer dielectric layer 16 covers the capacitor dielectric layer 13, the inductor 14, the first capacitor layer 15a and the second capacitor layer 15b. A plurality of connecting posts 17 penetrate the interlayer dielectric layer 16 and are respectively connected to the inner end of the inductor 14, the first capacitor layer 15a, the body 15b1 of the second capacitor layer 15b and the inductor connecting portion 15b2.

[0084] The first electrode 18, the second electrode 19 and the connecting portion 20 are all located on the interlayer dielectric layer 16 and are separated from each other. The first electrode 18 is connected to the first capacitor layer 15a through the corresponding connecting column 17, the second electrode 19 is connected to the second capacitor layer 15b through the corresponding connecting column 17, and the body 15b1 of the second capacitor layer 15b is connected to the inner end of the inductor 14 through the inductor connecting portion 15b2, the corresponding connecting column 17 and the connecting portion 20.

[0085] The back electrode 21 is located on the second surface 10b of the semiconductor substrate 10. In the present embodiment, the first capacitor layer 15a, the second capacitor layer 15b, the capacitor dielectric layer 13 and the back electrode 21 are used to form a capacitor. The first capacitor layer 15a and the second capacitor layer 15b serve as the upper electrodes of the capacitor, the back electrode 21 serves as the lower electrode of the capacitor, and the first electrode 18 and the second electrode 19 serve as the lead-out pads of the upper electrodes of the capacitor. Among them, the first electrode 18 and the second electrode 19 can also be used as two electrodes of the inductor 14. In some other embodiments, the first electrode 18 and the second electrode 19 can also be used as the upper electrodes of two capacitors or together as a capacitor as needed, so as to realize the application of different capacitance values.

[0086] Figures 7 to 17 Cross-sectional views showing some stages of a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure are shown.

[0087] First, an inductive dielectric layer 12 needs to be formed in a semiconductor substrate 10 .

[0088] In some specific embodiments, the inductive dielectric layer 12 is formed by etching+filling+grinding. Figure 7 As shown, a barrier layer 22 is formed on the first surface 10a of the semiconductor substrate 10. The material of the barrier layer 22 includes, for example, Si3N4. The barrier layer 22 is patterned by photolithography and etching processes. Then, the semiconductor substrate 10 is etched by an etching process to form an inductor isolation groove 11 extending from the first surface 10a of the semiconductor substrate 10 to the semiconductor substrate 10. In this step, the etching depth of the inductor isolation groove 11 is not less than 5 microns.

[0089] Further, a dielectric layer 12a is deposited on the barrier layer 22 and in the inductor isolation groove 11, such as Figure 8 In this step, for example, the dielectric layer 12a is deposited by chemical vapor deposition (CVD), and the deposition thickness needs to be greater than the depth of the inductor isolation groove 11 to ensure that the inductor isolation groove 11 is completely filled. The material of the dielectric layer 12a is, for example, silicon oxide.

[0090] Furthermore, the dielectric layer 12a on the areas other than the inductor isolation groove 11 is removed by chemical mechanical polishing (CMP). Fig. 9 In this step, the barrier layer 22 serves as a grinding stop layer.

[0091] Further, the barrier layer 22 is removed, such as Fig.10 In this step, for example, the barrier layer 22 is rinsed clean by a wet etching process, and the remaining dielectric layer 12 a filled in the inductor isolation groove 11 serves as the inductor dielectric layer 12 .

[0092] The inductor dielectric layer 12 is formed by etching + filling + grinding. Although deep grooves can be filled, the film thickness in the non-filled area is too thick, so it takes a long time and a lot of material to remove it by CMP. In addition, the residual oxide layer in the capacitor area at different positions on the wafer is difficult to control, which affects the stability of the capacitor parameters and the consistency within the chip. It is not suitable for mass production and cost control.

[0093] In some other specific embodiments, for example, an etching+oxidation method is used to form the inductive dielectric layer 12. Fig.11As shown, a barrier layer 22 is formed on the first surface 10a of the semiconductor substrate 10. The material of the barrier layer 22 includes, for example, Si3N4. The barrier layer 22 is patterned by photolithography and etching processes. Then, the semiconductor substrate 10 is etched by an etching process to form a plurality of grooves 23 extending from the first surface 10a of the semiconductor substrate 10 to the semiconductor substrate 10. Optionally, the width of each groove 23 is not greater than 1 μm, the depth is not less than 5 μm, and the spacing between adjacent grooves 23 is not greater than 2 μm. The actual SEM cross-sectional image is as shown in FIG. Fig.13 shown.

[0094] Further, the semiconductor substrate 10 is oxidized until the oxide fills the trench 23 to form the inductor dielectric layer 12, as shown in FIG. Fig.12 In this step, for example, Si between the grooves 23 is oxidized by high-temperature furnace oxidation and the grooves 23 are continuously filled by oxidation until the grooves 23 are filled, wherein the barrier layer 22 is not oxidized. Experiments have shown that the grooves 23 with a width of 1 μm, a spacing of 1 μm, and a depth of 5 μm can be completely oxidized and filled under the conditions of 1100°C and 60 minutes to form the inductor isolation medium 12, as shown in FIG. Fig.14 However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art can adjust the size parameters and oxidation conditions of the trench 23 as needed.

[0095] Furthermore, the barrier layer 22 is removed. In this step, for example, a wet etching process is used to rinse the barrier layer 22.

[0096] Compared with the etching + filling + grinding scheme, the etching + oxidation scheme saves the CMP time and reduces the processing cost. At the same time, the semiconductor substrate 10 located in the capacitor area avoids the influence of uneven film thickness within the chip caused by etching or CMP, thereby avoiding residue when removing the barrier layer, and thus making the capacitor dielectric layer 13 subsequently formed on the first surface 10a of the semiconductor substrate 10 more uniform, thereby improving the consistency and stability of the capacitance value.

[0097] After forming the inductor dielectric layer 12, a capacitor dielectric layer 13 is formed on the first surface 10a of the semiconductor substrate 10. Fig.15 In this step, for example, a dry oxygen oxidation process is used to form a dense capacitor dielectric layer 13. Optionally, the capacitor dielectric layer 13 has a thickness between 0.01 and 0.1 μm. The dense capacitor dielectric layer 13 can also improve the density of the surface of the inductor isolation medium 12.

[0098] Furthermore, an inductor 14, a first capacitor layer 15a and a second capacitor layer 15b are formed on the capacitor dielectric layer 13, as shown in FIG. Fig.16In this step, for example, a metal material is first deposited on the capacitor dielectric layer 13, and then the metal patterns of the inductor 14, the first capacitor layer 15a and the second capacitor layer 15b are simultaneously formed by a photolithography + etching process, and the metal material includes but is not limited to Al, Cu, AlCu, AlSiCu, etc.

[0099] Further, an interlayer dielectric layer 16 is formed to cover the capacitor dielectric layer 13, the inductor 14, the first capacitor layer 15a and the second capacitor layer 15b, and then a plurality of connecting pillars penetrating the interlayer dielectric layer 16 are formed, such as Fig.17 In this step, for example, the interlayer dielectric layer 16 is formed by CVD, and a plurality of contact holes penetrating the interlayer dielectric layer 16 are formed by photolithography + etching, and then the contact holes are filled with conductive material to form connecting pillars 17. Optionally, the material of the interlayer dielectric layer 16 is silicon oxide or other insulating media, and the aperture of the contact hole is not less than 1 μm to facilitate the filling of the conductive material.

[0100] Furthermore, a first electrode 18, a second electrode 19 and a connecting portion 20 are formed on the interlayer dielectric layer 16, as shown in FIG. Figure 6 As shown. In this step, a metal material is first deposited on the interlayer dielectric layer 16, and then the metal patterns of the first electrode 18, the second electrode 19 and the connecting portion 20 are simultaneously formed by, for example, a photolithography + etching process. The first electrode 18 and the second electrode 19 can be used as the two poles of the inductor 14, respectively, or can be used as the upper electrode of the capacitor separately or simultaneously. The connecting portion 20 is used as an auxiliary connection according to the shape of the pattern of the inductor 14.

[0101] Furthermore, a back electrode 21 is formed on the second surface 10b of the semiconductor substrate 10, such as Figure 6 As shown. In this step, in order to minimize the resistance between the back electrode 21 and the capacitor dielectric layer 13, the semiconductor substrate 10 should be thinned to within 200 μm, and a substrate with a resistivity of less than or equal to 0.01 Ω·cm should be selected. The back electrode 21 can be made of low-resistivity metal materials such as Au, Ag, Cu, etc., and formed by evaporation or sputtering, with a thickness of not less than 1 μm, so as to facilitate full connection between the chip and the tube shell during sintering, improve firmness, and reduce contact resistance.

[0102] Through the above process flow, a semiconductor LC integrated structure can be realized, and the capacitor and inductor are prepared on the same semiconductor substrate 10, and the first electrode (pad) 18, the second electrode (pad) 19 and the back electrode 21 are led out during the pressure welding package. The capacitor and the inductor can be used independently or in combination. When used as an inductor, the first electrode 18 and the second electrode 19 are only used as the two poles of the inductor; when used as a capacitor, the first electrode 18 and the second electrode 19 are used together as the upper electrode of the capacitor, and the back electrode 21 is used as the lower electrode of the capacitor; when the capacitor and the inductor are used in combination, the first electrode 18 and the second electrode 19 are used as the two poles of the inductor, and the first electrode 18 and the second electrode 19 are used as the upper electrode of the capacitor, and the back electrode 21 is used as the lower electrode of the capacitor.

[0103] Fig.18 A schematic top view of the structure of a semiconductor device according to a second embodiment of the present disclosure is shown.

[0104] like Fig.18 As shown, the semiconductor device of the second embodiment of the present disclosure is substantially similar to the first embodiment, and the similarities are not repeated here. Figures 4 to 17 The difference is that in this embodiment, the conductive layer also includes a plurality of third capacitor layers 15c, and the area of ​​the metal layer is increased by increasing the number of capacitor layer patterns, and the integration of multiple capacitors is achieved through combination to achieve the application of different capacitance values. When used only as a capacitor, 15a and 15b can also be connected and used as the upper electrode of the capacitor.

[0105] Fig.19 A schematic top view of the structure of a semiconductor device according to a third embodiment of the present disclosure is shown.

[0106] like Fig.19 As shown, the semiconductor device of the third embodiment of the present disclosure is substantially similar to the first embodiment, and the similarities are not repeated here. Figures 4 to 17 The difference is that, in this embodiment, the number of inductors 14 is multiple, and the inductance value is adjusted by increasing the number of inductor metal patterns. For example, the first electrodes 18a and 18b are connected and led out, and the second electrodes 19a and 19b are connected and led out, so that the two inductors 14 are connected in parallel; for another example, the first electrodes 18a and 18b are connected, and the second electrodes 19a and 19b are led out separately, so that the two inductors 14 are connected in series.

[0107] In this embodiment, the two electrodes corresponding to each inductor 14 are independent and not connected to each other, thereby increasing the flexibility of the device when used, and a parallel connection or a series connection can be selected according to needs.

[0108] The semiconductor device with integrated LC and the manufacturing method thereof provided by the present disclosure have at least the following advantages: 1. It solves the problem that the inductor and capacitor need to be configured separately in the application of radio frequency circuits, saves the area and volume occupied by the device, is conducive to improving product reliability, and adapts to the requirements of miniaturization and lightweight electronic equipment / systems. 2. In the process of filling the grooves, especially using the groove etching + oxidation method, it can not only shorten the process time, but also improve the surface uniformity of the non-deep groove area, thereby improving the consistency of electrical parameters. 3. The capacitance value can be flexibly adjusted by adjusting the area of ​​the capacitor metal layer, and the inductance can also be adjusted by increasing the number of inductor metal layer graphics, which has strong operability. 4. LC can be packaged separately, or it can be packaged in the same tube shell with other functional chips.

[0109] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A semiconductor substrate having a first surface and a second surface opposite to each other; an inductive dielectric layer extending from the first surface into the semiconductor substrate; A capacitor dielectric layer, located on the first surface; an inductor, located on the inductor dielectric layer; A conductive layer, located on the capacitor dielectric layer; as well as a back electrode, located on the second surface, The conductive layer, the capacitor dielectric layer and the back electrode can be used to form a capacitor.

2. The semiconductor device according to claim 1, wherein The capacitor dielectric layer covers the inductor dielectric layer, The inductor and the conductive layer are both located on the surface of the capacitor dielectric layer.

3. The semiconductor device according to claim 2, wherein: The upper surface of the inductive dielectric layer is coplanar with the first surface.

4. The semiconductor device according to claim 2, wherein: The inductor is in the shape of a vortex strip, having an inner end portion located at the center of the vortex and an outer end portion located outside the vortex, The conductive layer includes a first capacitor layer connected to the outer end.

5. The semiconductor device according to claim 4, further comprising: An interlayer dielectric layer, covering the capacitor dielectric layer, the inductor and the conductive layer; A plurality of connection pillars, penetrating the interlayer dielectric layer; as well as A connecting portion, located on the interlayer dielectric layer, Wherein, the conductive layer further includes the second capacitor layer, which is separated from the inductor. The second capacitor layer is connected to the inner end portion through the corresponding connecting column and the connecting portion.

6. The semiconductor device according to claim 5, wherein: The second capacitor layer includes a main body and an inductor connecting portion connected to each other, The orthographic projection of the body on the plane where the first surface is located falls outside the orthographic projection of the inductive dielectric layer on the plane, The orthographic projection of the inductor connecting portion on the plane falls within the orthographic projection of the inductor dielectric layer on the plane. The body is connected to the inner end portion via the inductor connecting portion, the corresponding connecting column and the connecting portion.

7. The semiconductor device according to claim 5, further comprising a first electrode and a second electrode located on the interlayer dielectric layer, wherein the first electrode, the second electrode and the connecting portion are separated from each other. in, The first electrode is connected to the first capacitor layer through the corresponding connecting column, The second electrode is connected to the second capacitor layer through the corresponding connecting column.

8. The semiconductor device according to any one of claims 4 to 7, wherein: The number of the inductors is multiple, And / or, the conductive layer further includes a plurality of third capacitor layers.

9. A method for manufacturing a semiconductor device, comprising: forming an inductive dielectric layer in a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, and the inductive dielectric layer extends from the first surface into the semiconductor substrate; forming a capacitor dielectric layer on the first surface; forming an inductor on the inductor dielectric layer; forming a conductive layer on the capacitor dielectric layer; as well as forming a back electrode on the second surface, The conductive layer, the capacitor dielectric layer and the back electrode can be used to form a capacitor.

10. The manufacturing method according to claim 9, wherein: The step of forming an inductive dielectric layer in a semiconductor substrate comprises: forming a patterned barrier layer on the first surface; forming an inductive isolation trench extending from the first surface into the semiconductor substrate; and Depositing a dielectric layer on the barrier layer and in the inductor isolation groove; Grinding and removing the dielectric layer on the barrier layer, and using the dielectric layer in the inductor isolation groove as the inductor dielectric layer; and removing the barrier layer, The barrier layer serves as a stop layer in the grinding step.

11. The manufacturing method according to claim 9, wherein: The step of forming an inductive dielectric layer in a semiconductor substrate comprises: forming a patterned barrier layer on the first surface; forming a plurality of trenches extending from the first surface into the semiconductor substrate; and Oxidizing the semiconductor substrate until the oxide fills the trench to form the inductive dielectric layer; and The barrier layer is removed.

12. The manufacturing method according to claim 9, wherein: A capacitor dielectric layer is formed on the first surface by using a dry oxygen oxidation process.

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