Voltage conversion circuit

Abstract

The present invention provides a voltage conversion circuit, comprising: the input end of a first inverter is used as the input end of the voltage conversion circuit, the output end of the first inverter is connected to the gate end of a second NMOS tube, the drain end of the second NMOS tube is connected to the source end of the first NMOS tube, the gate end of the first NMOS tube is connected to the source end of a fifth NMOS tube and the drain end of a sixth NMOS tube, the drain end of the first NMOS tube is connected to the drain end of a first PMOS tube and the gate end of a third PMOS tube, the drain end of the third PMOS tube is connected to the input end of a third inverter and the drain end of a third NMOS tube, the source end of the third NMOS tube is connected to the drain end of a fourth NMOS tube, the gate end of the fourth NMOS tube is connected to the output end of the second inverter, and the output end of the third inverter is the output end of the voltage conversion circuit. The voltage conversion circuit of the present invention has a fast conversion speed.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a voltage conversion circuit. Background Art

[0002] In integrated circuit design, the diversity of power supply voltage is becoming increasingly rich as the scale of circuits expands. The connection between signals of different voltages is essential, and voltage conversion circuits of various structures have emerged. Generally, it is required that the signals in the voltage conversion circuit can be transmitted (converted) as quickly as possible. However, the most commonly used voltage conversion circuit has a positive feedback latch structure. In the process of voltage signal conversion, the existing latch state must be overcome to continue the subsequent action, so the response speed is difficult to improve. The improvement of conversion speed has encountered a bottleneck, especially in the signal conversion between the low voltage domain (0.8V or 1.1V) and the higher voltage domain (above 5V, higher than the general high voltage domain 3.3V or 2.5V). The existing voltage conversion circuit is even more stretched, and a new voltage conversion circuit is urgently needed. Summary of the invention

[0003] The object of the present invention is to provide a voltage conversion circuit with a faster conversion speed.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] The present invention provides a voltage conversion circuit, which includes a first inverter, a second inverter, a third inverter, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first PMOS tube, a third PMOS tube, a fourth PMOS tube, and a fifth PMOS tube; the input end of the first inverter serves as the input end of the voltage conversion circuit to receive an input signal; the first inverter and the second inverter are sequentially connected in series, the output end of the first inverter is connected to the gate end of the second NMOS tube, the source end of the second NMOS tube is connected to the ground, the drain end of the second NMOS tube is connected to the source end of the first NMOS tube, and the The gate end of the first NMOS tube is connected to the source end of the fifth NMOS tube and the drain end of the sixth NMOS tube, the source end of the sixth NMOS tube is connected to the ground, the gate end of the sixth NMOS tube is connected to the input end of the third inverter, the drain end of the fifth NMOS tube is connected to the second working voltage, the gate end of the fifth NMOS tube is connected to the output end of the third inverter, the drain end of the first NMOS tube is connected to the drain end of the first PMOS tube and the gate end of the third PMOS tube, the gate end of the first PMOS tube is connected to the output end of the third inverter, the source end of the first PMOS tube is connected to the third working voltage, the source end of the third PMOS tube is connected to the third working voltage, and the The drain end is connected to the input end of the third inverter and the drain end of the third NMOS tube, the gate end of the third NMOS tube is connected to the second working voltage, the source end of the third NMOS tube is connected to the drain end of the fourth NMOS tube, the gate end of the fourth NMOS tube is connected to the output end of the second inverter, the source end of the fourth NMOS tube is connected to the ground, the drain end of the fifth PMOS tube is connected to the input end of the third inverter, the gate end of the fifth PMOS tube is connected to the output end of the third inverter, the source end of the fifth PMOS tube is connected to the third working voltage, the drain end of the fourth PMOS tube is connected to the input end of the third inverter, the gate end of the fourth PMOS tube receives a set signal, and the fourth PMOS tube receives a set signal. The source end of the OS tube is connected to the third operating voltage, the output end of the third inverter is the output end of the voltage conversion circuit, the first inverter and the second inverter are devices operating at the first operating voltage, the first NMOS tube, the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are devices operating at the second operating voltage, the fifth NMOS tube, the sixth NMOS tube, the first PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, and the third inverter are devices operating at the third operating voltage, the first operating voltage is lower than the second operating voltage, and the second operating voltage is lower than the third operating voltage.

[0006] In one embodiment, the voltage conversion circuit also includes a second PMOS tube, the source end of the second PMOS tube is connected to the third operating voltage, the gate end of the second PMOS tube is connected to the drain end of the second PMOS tube, and the drain end of the second PMOS tube is connected to the gate end of the third PMOS tube.

[0007] In one embodiment, the voltage conversion circuit further includes a tri-state gate, the input end of the tri-state gate is connected to the output end of the third inverter, the output end of the tri-state gate is connected to the input end of the third inverter, and the working state of the tri-state gate is controlled by a latch signal.

[0008] In one embodiment, an even number of inverters are provided between the output end of the second inverter and the gate end of the fourth NMOS transistor.

[0009] In one embodiment, the fifth NMOS tube is replaced by a sixth PMOS tube, and the source end of the six PMOS tubes is connected to the second operating voltage, the drain end of the six PMOS tubes is connected to the gate end of the first NMOS tube, and the gate end of the six PMOS tubes is connected to the input end of the third inverter.

[0010] In one implementation, the set signal has a process of rising from a low voltage to a high voltage.

[0011] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0012] The voltage conversion circuit of the present invention adopts a unidirectional open-loop structure, which shortens the conversion delay of the signal, so the conversion speed is faster. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A structural block diagram of a voltage conversion circuit provided in a first embodiment of the present invention;

[0015] Figure 2 This is a structural block diagram of a voltage conversion circuit provided in the second embodiment of the present invention. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present invention. It should be noted that the description order of the following embodiments is not used as a limitation on the preferred order of the embodiments of the present invention. In the following embodiments, the description of each embodiment has its own emphasis. For the parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0017] See also Figure 1As shown, the first embodiment of the present invention provides a voltage conversion circuit, which includes a first inverter inv1, a second inverter inv2, a third inverter inv3, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a first PMOS tube PM1, a third PMOS tube PM3, a fourth PMOS tube PM4, and a fifth PMOS tube PM5; the input end of the first inverter inv1 serves as the input end of the voltage conversion circuit to receive an input signal in; the first inverter inv1 and the second inverter inv2 are connected in series in sequence, and the first inverter inv1 and the second inverter inv2 are connected in series in sequence; The output end of an inverter inv1 is connected to the gate end of the second NMOS tube NM2, the source end of the second NMOS tube NM2 is connected to the ground, the drain end of the second NMOS tube NM2 is connected to the source end of the first NMOS tube NM1, the gate end NM1 of the first NMOS tube is connected to the source end of the fifth NMOS tube NM5 and the drain end of the sixth NMOS tube NM6, the source end of the sixth NMOS tube NM6 is connected to the ground, the gate end of the sixth NMOS tube NM6 is connected to the input end of the third inverter inv3, the drain end of the fifth NMOS tube NM5 is connected to the second working voltage MVDD, and the gate end of the fifth NMOS tube NM5 is connected to the output end of the third inverter inv3. The drain end of the first NMOS tube NM1 is connected to the drain end of the first PMOS tube PM1 and the gate end of the third PMOS tube PM3, the gate end of the first PMOS tube PM1 is connected to the output end of the third inverter inv3, the source end of the first PMOS tube PM1 is connected to the third working voltage HVDD, the source end of the third PMOS tube PM3 is connected to the third working voltage HVDD, the drain end of the third PMOS tube PM3 is connected to the input end of the third inverter inv3 and the drain end of the third NMOS tube NM3, the gate end of the third NMOS tube NM3 is connected to the second working voltage MVDD, and the source end of the third NMOS tube NM3 is connected to the fourth NMOS The drain end of the fourth NMOS tube NM4 is connected to the output end of the second inverter inv2, the source end of the fourth NMOS tube NM4 is connected to the ground, the drain end of the fifth PMOS tube PM5 is connected to the input end of the third inverter inv3, the gate end of the fifth PMOS tube PM5 is connected to the output end of the third inverter inv3, the source end of the fifth PMOS tube PM5 is connected to the third working voltage HVDD, the drain end of the fourth PMOS tube PM4 is connected to the input end of the third inverter inv3, the gate end of the fourth PMOS tube PM4 receives the set signal rtb, and the source end of the fourth PMOS tube PM4 is connected to the third working voltage HVDD,The output end of the third inverter inv3 is the output end out of the voltage conversion circuit, the first inverter inv1 and the second inverter inv2 are devices operating at a first operating voltage, the first NMOS tube NM1, the second NMOS tube NM2, the third NMOS tube NM3, and the fourth NMOS tube NM4 are devices operating at a second operating voltage MVDD, the fifth NMOS tube NM5, the sixth NMOS tube NM6, the first PMOS tube PM1, the third PMOS tube PM3, the fourth PMOS tube PM4, the fifth PMOS tube PM5, and the third inverter inv3 are devices operating at a third operating voltage HVDD, the first operating voltage is less than the second operating voltage MVDD, and the second operating voltage MVDD is less than the third operating voltage HVDD.

[0018] Among them, the first working voltage can be 1.1V or less, for example, 0.8V (hereinafter referred to as low voltage); the second working voltage MVDD can be 3.3V or 2.5V (hereinafter referred to as medium voltage); the third working voltage HVDD can be 5.0V or more (hereinafter referred to as high voltage). Correspondingly, the input signal in is a signal in the low voltage domain, and the output signal output by the output end out of the voltage conversion circuit is a signal in the high voltage domain. After the voltage conversion circuit of the present invention, the conversion of the signal from the low voltage domain to the high voltage domain is realized.

[0019] The following will be combined Figure 1 The working principle of the voltage conversion circuit of the present invention is explained. Figure 1 Some key nodes are defined in the following: Node la represents the output end of the first inverter inv1, the input end of the second inverter inv2, and the gate end of the second NMOS transistor NM2; Node lb represents the output end of the second inverter inv2 and the gate end of the fourth NMOS transistor NM4; Node hb represents the gate end of the first NMOS transistor NM1, the source end of the fifth NMOS transistor NM5, and the drain end of the sixth NMOS transistor NM6; Node hd represents the drain end of the first NMOS transistor NM1, the source end of the first PMOS transistor P The node outb represents the input terminal of the third inverter inv3, the drain terminal of the third NMOS tube NM3, the drain terminal of the third PMOS tube PM3, the drain terminal of the fifth PMOS tube PM5, the drain terminal of the fourth PMOS tube PM4, and the gate terminal of the sixth NMOS tube NM6; the output terminal out is also the output terminal of the third inverter inv3, the gate terminal of the fifth PMOS tube PM5, the gate terminal of the first PMOS tube PM1, and the gate terminal of the fifth NMOS tube NM5. The symbols of these nodes and the symbols of each component will be directly used for explanation in the following text.

[0020] First, the voltage conversion circuit of the present invention is set by the set signal rtb during operation. In a specific embodiment, the set signal rtb may have a process of being raised from a low voltage to a high voltage, so that PM4 is first turned on and then turned off, outb is pulled to a high potential due to the conduction of PM4, out is at a low potential due to the inversion of outb by inv3, PM5 and PM1 are both turned on, hd is at a high potential, NM5 is turned off and in a high impedance state, NM6 is turned on, hb is at a low potential, NM1 is turned off and in a high impedance state, and the initial setting is completed.

[0021] After the initial setting, when in rises from low to high, la falls, and NM2 turns off. lb rises, NM4 turns on, and NM3 is in the normally on state, so it starts to discharge the charge of outb (there are HVDD and PM5 in the discharge path). Because the on-resistance of NM3 and NM4 is much smaller than the on-resistance of PM5, the potential of outb is pulled down, and the potential of out rises (corresponding to the rise of in, completing the conversion). PM5 is turned off, and at the same time, NM5 is turned on, and then NM1 is turned on. At this time, PM1 is turned off and is in a high-impedance state. At the same time, because NM2 is turned off, hd is still maintained at a higher potential. The high potential of out is maintained by the on-state of NM3 and NM4.

[0022] When in drops from high to low, la rises, and NM2 turns on. At this time, hd-NM1-NM2 begins to have current, the potential of hd drops, and PM3 gradually turns on and starts to charge outb. At the same time, lb also drops, and NM4 turns off, so the potential of outb starts to rise, so NM6 also turns on, and the charge on hb begins to discharge. When outb rises and is reversed by inv3, out falls (corresponding to the fall of in, completing the conversion). PM5 turns on, and outb is pulled to a relatively high potential. hb is also pulled down due to the closure of NM5 and the conduction of NM6, causing NM1 to close. Finally, PM1 turns on, and the potential of hd is pulled up again. The low potential of out is maintained by the feedback of PM5.

[0023] The voltage conversion circuit of the present invention adopts a unidirectional open-loop structure, which shortens the signal conversion delay, so the conversion speed is faster. Moreover, the cascade structure from low voltage to medium voltage and then to high voltage protects the low voltage devices working under high voltage and improves the service life of the circuit. Moreover, the circuit is only sensitive to edge jumps, eliminating DC power consumption. Except at the moment of edge conversion, the potential of hd is maintained at a high potential, and PM3 is always in a closed state.

[0024] The applicant further studied and noticed that if in goes from a low potential to a high potential state for a long time, then in a high temperature environment or when NM2 has a large leakage (greater than the leakage of PM1), the hd potential will drop, which will cause PM3 to be partially closed. At this time, if there is a falling edge of in, then the voltage of hd does not drop from HVDD, but from a certain intermediate voltage. It can be seen that PM3 will turn on quickly and outb will rise very quickly. However, if in is at a high potential for a short time, then even if the leakage of NM2 is large, because the charge of hd does not have enough time to be discharged by NM1 and NM2, the potential of hd will be very close to the HVDD voltage value. If in has a falling edge at this time, the voltage of hd will be pulled down from the HVDD voltage until PM3 is turned on. This time is obviously longer. This characteristic leads to the fact that the signal flow cannot have good delay uniformity when high-frequency and low-frequency mixed signals are transmitted. Therefore, in one embodiment, the voltage conversion circuit further includes a second PMOS tube PM2 (at the dotted box A in the figure), the source end of the second PMOS tube PM2 is connected to the third working voltage HVDD, the gate end of the second PMOS tube PM2 is connected to the drain end of the second PMOS tube PM2, and the drain end of the second PMOS tube PM2 is connected to the gate end of the third PMOS tube PM3. In this way, when NM1 is turned on, NM2 is turned off, and PM1 is turned off, PM2 provides power to HD (when HD drops, PM2 will be turned on, and then power HD), ensuring that HD is still maintained at a higher potential. Of course, this second PMOS tube is also a device that works at the third working voltage.

[0025] For further information, please refer to Figure 1As shown, in one embodiment, the voltage conversion circuit further includes a tri-state gate tri_inv (at the dotted box B in the figure), the input end of the tri-state gate tri_inv is connected to the output end of the third inverter inv3, the output end of the tri-state gate tri_inv is connected to the input end of the third inverter inv3, and the working state of the tri-state gate tri_inv is controlled by a latch signal latch. Because in a larger system circuit using the voltage conversion circuit of the present invention, the first working voltage and the second working voltage MVDD are sometimes powered off as needed during operation (while the third working voltage HVDD is generally not powered off), if there is no tri-state gate tri_inv, then when the first working voltage and the second working voltage MVDD are powered off, the potential of out will also change disorderly, and cannot be maintained in the state before the power-off, which brings trouble to the normal operation of the system. The present invention forms a loop with the third inverter inv3 through the tri-state gate tri_inv, and allows the tri-state gate tri_inv to work through the latch signal latch before the system is powered off, and keeps the potential of out in the state before power off through the loop formed with the third inverter inv3, while in the general working process, the tri-state gate tri_inv is in a non-working state through the latch signal latch. For example, when the latch signal latch is low, the tri-state gate tri_inv does not work; when the latch signal latch is high, the tri-state gate tri_inv enters a working state.

[0026] Next, see Figure 2 As shown, the second embodiment of the present invention also provides a voltage conversion circuit, and please refer to Figure 1 The first embodiment shown in the figure mainly differs in that an even number of inverters are provided between the output terminal inv2 of the second inverter and the gate terminal of the fourth NMOS tube NM4 (in the dotted box C in the figure). In this way, more discharge time can be given to hd. Because the delay of the inverter is very small under some processes, it is not enough to make PM3 have a sufficiently small on-resistance, so the slew rate of outb will be slow, that is, the climbing speed will be slow. Although the potential change of out is enough to turn off NM1, the slew rate of out will be slow in the second half, which is not conducive to shortening the signal conversion time.

[0027] Please continue to compare Figure 1 , Figure 2As shown, in one embodiment, the fifth NMOS transistor NM5 can be replaced by a sixth PMOS transistor PM6 (at the dotted box D in the figure), and the source end of the sixth PMOS transistor PM6 is connected to the second working voltage MVDD, the drain end of the sixth PMOS transistor PM6 is connected to the gate end of the first NMOS transistor NM1, and the gate end of the sixth PMOS transistor PM6 is connected to the input end of the third inverter inv3. In this way, the wiring of the entire circuit can be reduced and the circuit structure can be simplified.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] The voltage conversion circuit of the present invention adopts a unidirectional open-loop structure, which shortens the signal conversion delay, so the conversion speed is faster. Moreover, the cascade structure from low voltage to medium voltage and then to high voltage protects the low voltage devices working under high voltage and improves the service life of the circuit. Moreover, the circuit is only sensitive to edge jumps, eliminating DC power consumption. And it has a latch structure, which can help maintain the output result unchanged when the low voltage power supply is powered off.

[0030] The above is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims. In addition, the specification uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. The content of this specification should not be understood as a limitation on the present invention.

Claims

1. A voltage conversion circuit, characterized in that: The voltage conversion circuit includes a first inverter, a second inverter, a third inverter, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first PMOS tube, a third PMOS tube, a fourth PMOS tube, and a fifth PMOS tube; the input end of the first inverter serves as the input end of the voltage conversion circuit to receive an input signal; the first inverter and the second inverter are connected in series in sequence, the output end of the first inverter is connected to the gate end of the second NMOS tube, the source end of the second NMOS tube is connected to the ground, and the The drain end of the second NMOS tube is connected to the source end of the first NMOS tube, the gate end of the first NMOS tube is connected to the source end of the fifth NMOS tube and the drain end of the sixth NMOS tube, the source end of the sixth NMOS tube is connected to the ground, the gate end of the sixth NMOS tube is connected to the input end of the third inverter, the drain end of the fifth NMOS tube is connected to the second working voltage, the gate end of the fifth NMOS tube is connected to the output end of the third inverter, the drain end of the first NMOS tube is connected to the drain end of the first PMOS tube and the gate end of the third PMOS tube, and the gate end of the first PMOS tube is connected to the ground. The output end of the third inverter is connected to the source end of the first PMOS tube, the source end of the third PMOS tube is connected to the third operating voltage, the drain end of the third PMOS tube is connected to the input end of the third inverter and the drain end of the third NMOS tube, the gate end of the third NMOS tube is connected to the second operating voltage, the source end of the third NMOS tube is connected to the drain end of the fourth NMOS tube, the gate end of the fourth NMOS tube is connected to the output end of the second inverter, the source end of the fourth NMOS tube is connected to ground, and the drain end of the fifth PMOS tube is connected to the input end of the third inverter and the drain end of the third NMOS tube. The input end of the three inverters, the gate end of the fifth PMOS tube is connected to the output end of the third inverter, the source end of the fifth PMOS tube is connected to the third working voltage, the drain end of the fourth PMOS tube is connected to the input end of the third inverter, the gate end of the fourth PMOS tube receives a set signal, the source end of the fourth PMOS tube is connected to the third working voltage, the output end of the third inverter is the output end of the voltage conversion circuit, the voltage of the input signal is the first working voltage, the first working voltage is less than the second working voltage, and the second working voltage is less than the third working voltage.

2. The voltage conversion circuit according to claim 1, characterized in that: The voltage conversion circuit also includes a second PMOS tube, a source end of the second PMOS tube is connected to the third operating voltage, a gate end of the second PMOS tube is connected to the drain end of the second PMOS tube, and the drain end of the second PMOS tube is connected to the gate end of the third PMOS tube.

3. The voltage conversion circuit according to claim 1, characterized in that: The voltage conversion circuit also includes a tri-state gate, the input end of the tri-state gate is connected to the output end of the third inverter, the output end of the tri-state gate is connected to the input end of the third inverter, and the working state of the tri-state gate is controlled by a latch signal.

4. The voltage conversion circuit according to claim 1, characterized in that: An even number of inverters are arranged between the output end of the second inverter and the gate end of the fourth NMOS tube.

5. The voltage conversion circuit according to claim 1, characterized in that: The fifth NMOS tube is replaced by a sixth PMOS tube, and the source end of the sixth PMOS tube is connected to the second operating voltage, the drain end of the sixth PMOS tube is connected to the gate end of the first NMOS tube, and the gate end of the sixth PMOS tube is connected to the input end of the third inverter.

6. The voltage conversion circuit according to claim 1, characterized in that: The set signal has a process of rising from a low voltage to a high voltage.

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