Pulse width modulation method, circuit and chip

Abstract

The embodiment of the invention provides a pulse width modulation method, a circuit and a chip, and relates to the technical field of pulse width debugging. The method comprises the following steps: acquiring a first count value of a first timer and / or a second count value of a second timer; if it is determined that the first count value or the second count value is equal to the first preset value, a first signal is generated, and the pulse signal is overturned according to the first signal. If it is determined that the first count value or the second count value is equal to a second preset value, a second signal is generated, and the pulse signal is overturned according to the second signal. According to the invention, the effect of improving the precision of pulse width modulation can be achieved.

Description

Technical Field

[0001] The present application relates to the technical field of pulse signal width modulation, and in particular to a pulse width modulation method, circuit and chip. Background Art

[0002] At present, with the development of electronic technology, a variety of pulse width modulation (PWM) technologies have emerged, including: phase voltage control PWM, pulse width PWM method, random PWM, SPWM method, line voltage control PWM, etc.

[0003] In the prior art, the up and down counting of the timer is used to generate the count value and the triangular carrier, and the comparison register is used. When the count value reaches the set value of the comparison register, the corresponding chip pin is switched between high and low levels, thereby generating a pulse PWM sequence with a changing duty cycle.

[0004] However, in the prior art, the frequency requirement for the internal clock is relatively high. Summary of the invention

[0005] The embodiments of the present application provide a pulse width modulation method, a circuit and a chip to achieve the effect of improving the accuracy of pulse width modulation.

[0006] In a first aspect, an embodiment of the present application provides a pulse width modulation method, including a first timer and a second timer, wherein the first timer times a preset first clock, and the second timer times a preset second clock; the method includes:

[0007] Obtaining a first count value of the first timer and / or a second count value of the second timer;

[0008] If it is determined that the first count value or the second count value is equal to a first predetermined value, a first signal is generated, and the pulse signal is flipped according to the first signal;

[0009] If it is determined that the first count value or the second count value is equal to a second predetermined value, a second signal is generated, and the pulse signal is flipped according to the second signal.

[0010] In a possible implementation manner, the first counting period of the first timer is different from the second counting period of the second timer; and the method further includes:

[0011] Determining the first predetermined value and the second predetermined value according to a preset target width of the pulse signal and a difference between the first counting period and the second counting period;

[0012] According to the target width and the difference, a comparison value of the first predetermined value and a comparison value of the second predetermined value are determined respectively; wherein the comparison value is the first count value or the second count value.

[0013] In a possible implementation, determining the first predetermined value and the second predetermined value according to a preset target width of the pulse signal and a difference between the first counting period and the second counting period; and determining a comparison value of the first predetermined value and a comparison value of the second predetermined value according to the target width and the difference, respectively, include:

[0014] Determine the first predetermined value and the second predetermined value respectively according to the target width of the pulse signal, the first counting period, the second counting period, and the difference between the first counting period and the second counting period;

[0015] A comparison value of the first predetermined value and a comparison value of the second predetermined value are determined according to the target width, the first counting cycle, the second counting cycle and the difference, respectively; wherein the comparison value is the first counting value or the second counting value.

[0016] In a possible implementation manner, the first counting period of the first timer and the second counting period of the second timer are the same but have different phases, and the method further includes:

[0017] Determine the first predetermined value and the second predetermined value according to a preset target width of the pulse signal, a first counting period, a second counting period, and a phase difference between the first counting period and the second counting period;

[0018] A comparison value of the first predetermined value and a comparison value of the second predetermined value are determined respectively according to a target width, a first counting cycle, a second counting cycle and a phase difference between the first counting cycle and the second counting cycle; wherein the comparison value is the first counting value or the second counting value.

[0019] In a possible implementation manner, obtaining the first count value of the first timer and / or the second count value of the second timer includes:

[0020] The first timer counts at a transition edge of the first clock, and the second timer counts at a transition edge of the second clock;

[0021] The transition edge includes a rising edge and / or a falling edge.

[0022] In a possible implementation manner, obtaining the first count value of the first timer and / or the second count value of the second timer includes any one of the following methods:

[0023] The first timer detects and counts both the rising edge and the falling edge, and the second timer detects and counts both the rising edge and the falling edge;

[0024] The first timer detects and counts the rising edge or the falling edge, and the second timer detects and counts both the rising edge and the falling edge;

[0025] The first timer detects and counts both the rising edge and the falling edge, and the second timer detects and counts the rising edge or the falling edge;

[0026] The first timer detects and counts rising edges or falling edges, and the second timer detects and counts rising edges or falling edges.

[0027] In a possible implementation manner, the direction of the first timer and the second timer is the same as or opposite to that of the first timer.

[0028] In a second aspect, an embodiment of the present application provides a pulse width modulation apparatus, which is applied to a pulse width modulation device, wherein the pulse width modulation device includes a first timer and a second timer, wherein the first timer times a preset first clock, and the second timer times a preset second clock; and the method includes:

[0029] an acquisition module, used to acquire a first count value of the first timer and / or a second count value of the second timer;

[0030] A first generating module, configured to generate a first signal if it is determined that the first count value or the second count value is equal to a first predetermined value, and flip the pulse signal according to the first signal;

[0031] The second generating module is used to generate a second signal if it is determined that the first count value or the second count value is equal to a second predetermined value, and flip the pulse signal according to the second signal.

[0032] In a possible implementation manner, the first counting period of the first timer is different from the second counting period of the second timer; and the device further includes:

[0033] A first determination module is used to determine the first predetermined value and the second predetermined value according to a preset target width of the pulse signal and a difference between the first counting period and the second counting period after obtaining the first counting value of the first timer and / or the second counting value of the second timer; and to determine a comparison value of the first predetermined value and a comparison value of the second predetermined value according to the target width and the difference, respectively; wherein the comparison value is the first counting value or the second counting value.

[0034] In a possible implementation manner, the first determining module is specifically configured to:

[0035] Determine the first predetermined value and the second predetermined value according to the target width of the pulse signal, the first counting cycle, the second counting cycle, and the difference between the first counting cycle and the second technical cycle;

[0036] A comparison value of the first predetermined value and a comparison value of the second predetermined value are determined according to the target width, the first counting cycle, the second counting cycle and the difference, respectively; wherein the comparison value is the first counting value or the second counting value.

[0037] In a possible implementation manner, the first counting period of the first timer and the second counting period of the second timer are the same but have different phases; the device further includes:

[0038] A second determination module is used to determine the first predetermined value and the second predetermined value according to a preset target width of the pulse signal and a difference between a first counting period and a second counting period after obtaining the first counting value of the first timer and / or the second counting value of the second timer; and to determine a comparison value of the first predetermined value and a comparison value of the second predetermined value according to the target width and the difference, respectively; wherein the comparison value is the first counting value or the second counting value.

[0039] In a possible implementation manner, the acquisition module is specifically configured to:

[0040] The first timer counts at a transition edge of the first clock, and the second timer counts at a transition edge of the second clock;

[0041] The transition edge includes a rising edge and / or a falling edge.

[0042] In a possible implementation manner, obtaining the first count value of the first timer and / or the second count value of the second timer includes any one of the following methods:

[0043] The first timer detects and counts both the rising edge and the falling edge, and the second timer detects and counts both the rising edge and the falling edge;

[0044] The first timer detects and counts the rising edge or the falling edge, and the second timer detects and counts both the rising edge and the falling edge;

[0045] The first timer detects and counts both the rising edge and the falling edge, and the second timer detects and counts the rising edge or the falling edge;

[0046] The first timer detects and counts rising edges or falling edges, and the second timer detects and counts rising edges or falling edges.

[0047] In a possible implementation manner, the direction of the first timer and the second timer is the same as or opposite to that of the first timer.

[0048] In a third aspect, an embodiment of the present application provides a pulse width modulation circuit, the circuit comprising a first timer, a second timer, a first comparator, a second comparator, a first multiplexer, a second multiplexer, and a pulse width modulation control module;

[0049] The output ends of the first timer and the second timer are connected to the input end of the first multiplexer and the input end of the second multiplexer respectively; the output end of the first multiplexer is connected to the input end of the first comparator respectively; the output end of the second multiplexer is connected to the input end of the second comparator; the input end of the first comparator is connected to the output end of the first multiplexer; the input end of the second comparator is connected to the output end of the second multiplexer; the pulse width modulation control module is connected to the first multiplexer, the second multiplexer, the first comparator and the second comparator respectively;

[0050] The pulse width modulation control module is used to send a first selection signal to the first multiplexer and provide a second selection signal to the second multiplexer according to a preset pulse width;

[0051] The first multiplexer is used to send the count value of the timer corresponding to the received first selection signal to the first comparator;

[0052] The second multiplexer is used to send the count value of the timer corresponding to the received second selection signal to the second comparator;

[0053] The first comparator is used to generate a first signal according to the received count value and the first preset value; wherein the first signal represents a flip pulse signal at a current moment;

[0054] The second comparator is used to generate a second signal according to the received count value and the second preset value; wherein the second signal represents the flipping of the pulse signal at the current moment.

[0055] In a fourth aspect, an embodiment of the present application provides a microprocessor chip, wherein the microprocessor chip includes the pulse width modulation method described in the first aspect or the pulse signal width modulation circuit described in the third aspect.

[0056] In a fifth aspect, an embodiment of the present application provides a pulse width modulation device, wherein the pulse width modulation device includes the pulse width modulation method described in the first aspect or the pulse signal width modulation circuit described in the third aspect.

[0057] In a sixth aspect, an embodiment of the present application provides a pulse width modulation device, including: a memory, a processor;

[0058] The memory stores computer-executable instructions;

[0059] The processor executes the computer-executable instructions stored in the memory, so that the processor executes various possible implementations of the first aspect as described above.

[0060] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-readable storage medium is stored computer execution instructions, and when the computer execution instructions are executed by a processor, they are used to implement the first aspect above and / or various possible implementation methods of the first aspect.

[0061] In an eighth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the above first aspect and / or various possible implementations of the first aspect.

[0062] A pulse width modulation method, circuit and chip provided in an embodiment of the present application obtain a first count value of a first timer and / or a second count value of a second timer. If it is determined that the first count value or the second count value is equal to a first predetermined value, a first signal is generated, and the pulse signal is flipped according to the first signal. If it is determined that the first count value or the second count value is equal to a second predetermined value, a second signal is generated, and the pulse signal is flipped according to the second signal. In this scheme, the count value of the first timer is obtained through the first clock, the count value of the second timer is obtained through the second clock, and the first signal and the second signal are determined according to the count values ​​of the two timers, and the pulse signal is flipped according to the first signal and the second signal. Therefore, without further increasing the clock frequency, the PWM accuracy is improved through two clock timers, thereby achieving the effect of improving the accuracy of pulse width modulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0064] Figure 1 A schematic diagram of a pulse width modulation method provided in this application;

[0065] Figure 2 A schematic diagram of a pulse width modulation method provided in this application;

[0066] Figure 3 A schematic diagram of another pulse width modulation method provided in this application;

[0067] Figure 4 A schematic diagram of another pulse width modulation method provided in this application;

[0068] Figure 5 A schematic diagram of another pulse width modulation method provided in this application;

[0069] Figure 6 A schematic diagram of another pulse width modulation method provided in this application;

[0070] Figure 7 A schematic diagram of the structure of a pulse width modulation device provided in this application;

[0071] Figure 8 A schematic diagram of the structure of another pulse width modulation device provided in the present application;

[0072] Fig. 9 A circuit diagram of a pulse width modulation circuit provided in the present application;

[0073] Fig.10 A schematic diagram of the structure of another pulse width modulation device provided in this application.

[0074] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0075] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application.

[0076] At present, with the development of electronic technology, a variety of pulse width modulation (PWM) technologies have emerged, including: phase voltage control PWM, pulse width PWM method, random PWM, SPWM method, line voltage control PWM, etc. The purpose of controlling the charging current can be achieved by adjusting the PWM period and PWM duty cycle.

[0077] In one example, the up and down counting of the timer is used to generate the count value and the triangular carrier, and the comparison register is used. When the count value reaches the set value of the comparison register, the corresponding chip pin is switched between high and low levels, thereby generating a pulse PWM sequence with a variable duty cycle. However, in the prior art, since the up and down counting of the timer needs to be obtained based on the time pulses emitted by multiple internal clocks of the chip, the up and down counting accuracy is affected by the frequency of the internal clock, and the frequency of the internal clock is required to be relatively high.

[0078] In combination with the above scenario, it can be seen that in the prior art, if the frequency of the internal clock does not meet the requirements, it will lead to a technical problem of poor PWM accuracy.

[0079] The pulse width modulation method provided by the present application obtains the count value of the first timer through the first clock, obtains the count value of the second timer through the second clock, determines the pulse width modulation pulse according to the count values ​​of the two timers, and performs flip processing on the level signal according to the second signal. Therefore, without further increasing the clock frequency, the PWM accuracy can be improved by using two clock timers, thereby achieving the effect of improving the accuracy of pulse width modulation.

[0080] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0081] Figure 1 A pulse width modulation method is provided in this application. Figure 1 As shown, a first timer and a second timer are included, the first timer counts a preset first clock, and the second timer counts a preset second clock; the method includes:

[0082] S201: Obtain a first count value of a first timer and / or a second count value of a second timer.

[0083] Exemplarily, the clock includes a first clock corresponding to a first timer and a second clock corresponding to a second timer. The period of the first clock is a preset first period, the period of the second clock is a preset second period, the first period and the second period may be the same or different, and there is no limitation on this; the timer is used to count the time pulses emitted by the clock, that is, to count the jump edges.

[0084] In this step, based on the first clock, a first count value of the first timer is obtained, and / or based on the second clock, a second count value of the second timer is obtained.

[0085] S202: If it is determined that the first count value or the second count value is equal to the first predetermined value, a first signal is generated, and the pulse signal is flipped according to the first signal.

[0086] Exemplarily, a comparison value is first determined, and the comparison value refers to a first count value or a second count value. If the comparison value is the first count value, the first count value is compared with the first predetermined value. If it is determined that the first count value is equal to the first predetermined value, a first signal is generated, and the current pulse signal is flipped according to the first signal. Alternatively, if the comparison value is the second count value, the second count value is compared with the first predetermined value. If it is determined that the second count value is equal to the first predetermined value, a first signal is generated, and the current pulse signal is flipped according to the first signal. Among them, if the current pulse signal is a high level, the flipping process refers to converting the current high level to a low level; if the current pulse signal is a low level, the flipping process refers to converting the current low level to a high level, and there is no limitation on this.

[0087] S203: If it is determined that the first count value or the second count value is equal to the second predetermined value, a second signal is generated, and the pulse signal is flipped according to the second signal.

[0088] Exemplarily, if the comparison value is the first count value, the first count value is compared with the second predetermined value, and if it is determined that the first count value is greater than or equal to the second predetermined value, a second signal is generated, and the pulse signal is flipped according to the second signal. Alternatively, if the comparison value is the second count value, the second count value is compared with the second predetermined value, and if it is determined that the second count value is greater than or equal to the second predetermined value, a second signal is generated, and the pulse signal is flipped according to the second signal.

[0089] For example, Figure 2 A schematic diagram of a pulse width modulation method provided in this application, such as Figure 2 As shown, the resolution of the PWM signal is determined by the difference in counting cycles between the first timer and the second timer; Figure 2 As shown, the counting period of the first timer is 10ns, and the counting period of the second timer is 11ns; according to target width / difference = first predetermined value = second predetermined value, the first predetermined value and the second predetermined value are determined by the target width of the PWM pulse to be generated and the difference. For example, a signal with a target width of 12ns needs to be generated, and the ratio of the target width to the difference is 12. The first predetermined value can be set to 12, and the second predetermined value can be set to 12. When the first count value of the first timer is equal to the first predetermined value, the pulse signal is flipped, and when the second count value of the second timer is equal to the second predetermined value, the pulse signal is flipped again.

[0090] The pulse width modulation method provided in the embodiment of the present application obtains the first count value of the first timer and / or the second count value of the second timer. If it is determined that the first count value or the second count value is equal to the first predetermined value, a first signal is generated, and the pulse signal is flipped according to the first signal. If it is determined that the first count value or the second count value is equal to the second predetermined value, a second signal is generated, and the pulse signal is flipped according to the second signal. In this scheme, the count value of the first timer is obtained through the first clock, the count value of the second timer is obtained through the second clock, and the first signal and the second signal are determined according to the count values ​​of the two timers, and the pulse signal is flipped according to the first signal and the second signal. Therefore, without further increasing the clock frequency, the PWM accuracy can be improved by using two clock timers to achieve the effect of improving the accuracy of pulse width modulation. Counting personnel in this field should understand that the above method cannot constitute a limitation.

[0091] This embodiment Figure 1 Based on the embodiment, the pulse width modulation method is described in detail, and the method includes:

[0092] S301: Obtain a first count value of a first timer and / or a second count value of a second timer.

[0093] In one example, the first timer performs timing at a transition edge of a first clock, and the second timer performs timing at a transition edge of a second clock; wherein the transition edge includes a rising edge and / or a falling edge.

[0094] In one example, obtaining the first count value of the first timer and / or the second count value of the second timer includes any one of the following methods: the first timer detects and counts both the rising edge and the falling edge, and the second timer detects and counts both the rising edge and the falling edge; the first timer detects and counts the rising edge or the falling edge, and the second timer detects and counts both the rising edge and the falling edge; the first timer detects and counts both the rising edge and the falling edge, and the second timer detects and counts the rising edge or the falling edge; the first timer detects and counts the rising edge or the falling edge, and the second timer detects and counts the rising edge or the falling edge.

[0095] In one example, the directions of the first timer and the second timer are the same or opposite.

[0096] In one example, after step 301, two implementation methods are included:

[0097] The first implementation method: the first counting period of the first timer is different from the second counting period of the second timer; the first predetermined value and the second predetermined value are determined according to the target width of the pulse signal and the difference between the first counting period and the second counting period; the comparison value of the first predetermined value and the comparison value of the second predetermined value are determined according to the target width and the difference, respectively; wherein the comparison value is the first counting value or the second counting value.

[0098] In one example, "determine the first predetermined value and the second predetermined value based on a preset target width of the pulse signal and the difference between the first counting period and the second counting period; determine the comparison value of the first predetermined value and the comparison value of the second predetermined value respectively based on the target width and the difference", includes: determine the first predetermined value and the second predetermined value based on the target width of the pulse signal, the first counting period, the second counting period, and the difference between the first counting period and the second counting period; determine the comparison value of the first predetermined value and the comparison value of the second predetermined value respectively based on the target width, the first counting period, the second counting period and the difference; wherein the comparison value is the first counting value or the second counting value.

[0099] The second implementation method: the first counting period of the first timer and the second counting period of the second timer are the same but have different phases; the first predetermined value and the second predetermined value are determined according to the preset target width of the pulse signal and the difference between the first counting period and the second counting period; the comparison value of the first predetermined value and the comparison value of the second predetermined value are determined according to the target width and the difference, respectively; wherein the comparison value is the first counting value or the second counting value.

[0100] Exemplarily, the first timer performs timing at the transition edge of the first clock to obtain a first count value; and the second timer performs timing at the transition edge of the second clock to obtain a second count value, and the transition edge includes a rising edge and / or a falling edge. Further, in the counting process of the timer, the timer detection edge is not limited, and the counting methods of the first timer and the second timer include any one of the following: the first timer detects and counts both the rising edge and the falling edge, and the second timer detects and counts both the rising edge and the falling edge; the first timer detects and counts the rising edge or the falling edge, and the second timer detects and counts the rising edge and the falling edge; the first timer detects and counts both the rising edge and the falling edge, and the second timer detects and counts the rising edge or the falling edge; the first timer detects and counts the rising edge or the falling edge, and the second timer detects and counts the rising edge or the falling edge.

[0101] Specifically, in a first implementation, the first counting period of the first timer is different from the second counting period of the second timer; the target width of the pulse signal is a preset value. The first predetermined value and the second predetermined value are calculated according to the preset target width of the pulse signal, the difference between the first counting period and the second counting period. And according to the target width and the difference, the comparison value of the first predetermined value and the comparison value of the second predetermined value are determined respectively.

[0102] Further, Figure 3 A schematic diagram of another pulse width modulation method provided in this application, such as Figure 3 As shown, the first predetermined value, the second predetermined value and the comparison value are determined according to the target width, the first counting cycle of the first timer, the second counting cycle of the second timer and the difference between the first counting cycle and the second counting cycle;

[0103] For example, assuming that the least common multiple M of the first counting period and the second counting period is:

[0104] x*first counting period=y*second counting period=M;

[0105] right

[0106] First predetermined value=((target width mod first counting period) / difference-(target width / / first counting period))+nx;

[0107] Second predetermined value=((target width mod first counting period) / difference+ny

[0108] Find a positive integer solution, where n is a natural number, the comparison value of the first predetermined value is a first count value, and the comparison value of the second predetermined value is a second count value;

[0109] or, yes

[0110] First predetermined value=((target width mod second counting period)+(target width / / second counting period))+ny;

[0111] The second predetermined value = ((target width mod second counting period) + nx;

[0112] Find a positive integer solution, where n is a natural number, the comparison value of the first predetermined value is the second count value, and the comparison value of the second predetermined value is the first count value;

[0113] Specifically, the target width is 12ns. According to the first counting period of 10ns, the second counting period of 11ns, and the difference between the first counting period and the second counting period of 1ns, the first predetermined value is 1, the second predetermined value is 2, the comparison value of the first predetermined value is the first counting value, and the comparison value of the second predetermined value is the second counting value. According to 11ns*2-10ns*1=10ns, a pulse of target width can be obtained; or the first predetermined value is 2, the first predetermined value is 1, the comparison value of the first predetermined value is the second counting value, and the comparison value of the second predetermined value is the first counting value. According to 11ns*2-10ns*1=10ns, a pulse of target width can be obtained.

[0114] Similarly, other pulse widths can be implemented by the above method, and the above method is only used as an example. That is, the first predetermined value and the second predetermined value can be calculated according to the target width of the pulse signal, the first counting cycle, the second counting cycle, and the difference between the first counting cycle and the second counting cycle. And according to the target width, the first counting cycle, the second counting cycle and the difference, the comparison value of the first predetermined value and the comparison value of the second predetermined value are determined respectively. Therefore, compared with the implementation method of "calculating the first predetermined value, the second predetermined value, and the comparison value according to the target width and difference of the pulse signal" in the previous paragraph, the pulse signal width modulation speed of this method is faster. Those skilled in the art should understand that the above method does not constitute a limitation on "calculating the first predetermined value and the second predetermined value according to the target width of the pulse signal, the first counting cycle, the second counting cycle, and the difference between the first counting cycle and the second counting cycle. And according to the target width, the first counting cycle, the second counting cycle and the difference, the comparison value of the first predetermined value and the comparison value of the second predetermined value are determined respectively".

[0115] For example, Figure 4 A schematic diagram of another pulse width modulation method provided in this application, such as Figure 4As shown, the first timer and the second timer both count both the rising edge and the falling edge, and the first counting cycle of the first timer and the second counting cycle of the second timer are not equal; one count value is one counting cycle, and one clock cycle includes a low level and a high level. The first timer and the second timer both start at the same timing time 0. If the first timer detects that a transition edge occurs in half a clock cycle, that is, a low level changes to a high level between 0-1, then the period of the transition edge that occurs in half a clock cycle is determined to be half a clock cycle, and the first timer increases the first count value by 1 when the next half clock cycle passes, and so on. If the second timer detects that a transition edge occurs in half a clock cycle, that is, a low level changes to a high level between 0-1, then the period of the transition edge that occurs in half a clock cycle is determined to be half a clock cycle, and the second timer increases the second count value by 1 when the next half clock cycle passes. The difference between the first counting cycle and the second counting cycle is obtained by subtracting the half clock cycle of the transition edge in the first timer from the half clock cycle of the transition edge in the second timer. The first predetermined value and the second predetermined value are calculated based on the target width, the difference between the first counting cycle and the second counting cycle, and the comparison value of the first predetermined value and the comparison value of the second predetermined value are determined based on the target width and the difference. Specifically, Figure 4 As shown, when the period of the first clock is 10ns and the period of the second clock is 11ns, the half clock period of the first clock is 5ns, the half clock period of the second clock is 5.5ns, and the difference between the first counting period and the second counting period is 5.5ns-5ns=0.5ns. The minimum target width that can be modulated can be 0.5ns. The first predetermined value and the second predetermined value can be calculated based on the target width, the difference between the first counting period and the second counting period, and the comparison value of the first predetermined value and the comparison value of the second predetermined value can be determined respectively based on the target width and the difference.

[0116] The first timer and the second timer count the rising edge and the falling edge of the clock, which can further improve the resolution of the pulse width modulation.

[0117] In a second implementation, the first counting period of the first timer and the second counting period of the second timer are the same but have different phases. The first predetermined value and the second predetermined value are calculated according to a preset target width of the pulse signal and the difference between the first counting period and the second counting period. And the comparison value of the first predetermined value and the comparison value of the second predetermined value are determined respectively according to the target width and the difference.

[0118] For example, Figure 5 A schematic diagram of another pulse width modulation method provided in this application, such as Figure 5As shown, the first timer and the second timer both count the rising edge and the falling edge; the first cycle of the first clock and the second cycle of the second clock are equal, and the cycle is T, and the phase of the jump edge of the first clock and the phase of the jump edge of the second clock differ by half a cycle. The first timer and the second timer both start at the same timing moment. If the first timer detects that the jump edge occurs in half a clock cycle, the phase of the jump edge that occurs in half a clock cycle is determined, and the first timer increases the first count value by 1 when the next half clock cycle passes. If the second timer detects that the jump edge occurs in half a clock cycle, the phase of the jump edge that occurs in half a clock cycle is determined, and the second timer increases the second count value by 1 when the next half clock cycle passes. According to the preset target width of the pulse signal and the phase difference between the first clock and the second clock, the first predetermined value and the second predetermined value are calculated, and the comparison value of the first predetermined value and the comparison value of the second predetermined value are determined respectively according to the target width and the phase difference. Then, based on the phase of the jump edge in the first timer and the phase of the jump edge in the second timer, the comparison value of the first predetermined value is compared with the first predetermined value, and the comparison value of the second predetermined value is compared with the second predetermined value. If it is determined that the comparison value of the first predetermined value is equal to the first predetermined value, a first signal is generated, and if it is determined that the comparison value of the second predetermined value is equal to the second predetermined value, a second signal is generated. According to the first signal and the second signal, the target pulse width is output; the first timer and the second timer are respectively selected using the preset target width, and pulses of T / 2, T, T+T / 2, 2T, 2T+T / 2... can be obtained. When there are other phases, pulses of various widths can also be obtained.

[0119] It should be noted that Figure 6 A schematic diagram of another pulse width modulation method provided in this application, such as Figure 6 As shown, the directions of the first timer and the second timer can be the same, or opposite, and there is no limitation on this. The direction does not affect the PWM pulse width modulation.

[0120] S302: If it is determined that the first count value or the second count value is equal to the first predetermined value, a first signal is generated, and the pulse signal is flipped according to the first signal.

[0121] For example, this step can be referred to Figure 1 Step 202 in will not be described in detail.

[0122] S303: If it is determined that the first count value or the second count value is equal to the second predetermined value, a second signal is generated, and the pulse signal is flipped according to the second signal.

[0123] For example, this step can be referred to Figure 1 Step 203 in the above is not described in detail.

[0124] The pulse width modulation method provided in the embodiment of the present application obtains the first count value of the first timer and / or the second count value of the second timer. If it is determined that the first count value or the second count value is equal to the first predetermined value, a first signal is generated, and the pulse signal is flipped according to the first signal. If it is determined that the first count value or the second count value is equal to the second predetermined value, a second signal is generated, and the pulse signal is flipped according to the second signal. In this scheme, the count value of the first timer is obtained through the first clock, the count value of the second timer is obtained through the second clock, and the pulse width modulation pulse is determined according to the count values ​​of the two timers. Therefore, without further increasing the clock frequency, the PWM accuracy can be improved by two clock counters, thereby achieving the effect of improving the accuracy of pulse width modulation.

[0125] Figure 7 The schematic diagram of the structure of the pulse width modulation device provided in this application is as follows: Figure 7 As shown, it is applied to a pulse width modulation device, the pulse width modulation device includes a first timer and a second timer, the first timer counts a preset first clock, and the second timer counts a preset second clock; the pulse width modulation device 40 provided in this embodiment includes:

[0126] The acquisition module 41 is used to acquire a first count value of the first timer and / or a second count value of the second timer.

[0127] The first generating module 42 is configured to generate a first signal if it is determined that the first count value or the second count value is equal to a first predetermined value, and flip the pulse signal according to the first signal.

[0128] The second generating module 43 is configured to generate a second signal if it is determined that the first count value or the second count value is equal to a second predetermined value, and flip the pulse signal according to the second signal.

[0129] The pulse width modulation device of this embodiment can implement the technical solution in the above method. Its specific implementation process and technical principles are the same and will not be repeated here.

[0130] Figure 8 A schematic diagram of the structure of another pulse width modulation device provided in an embodiment of the present application, in Figure 7 Based on the embodiment shown, Figure 8 The device also includes:

[0131] The first determination module 51 is used to determine the first predetermined value and the second predetermined value according to the preset target width of the pulse signal and the difference between the first counting period and the second counting period after obtaining the first counting value of the first timer and / or the second counting value of the second timer; determine the comparison value of the first predetermined value and the comparison value of the second predetermined value according to the target width and the difference, respectively; wherein the comparison value is the first counting value or the second counting value.

[0132] In a possible implementation, the first determining module 51 is specifically configured to:

[0133] Determine a first predetermined value and a second predetermined value according to a target width of the pulse signal, a first counting period, a second counting period, and a difference between the first counting period and the second counting period;

[0134] According to the target width, the first counting cycle, the second counting cycle and the difference, a comparison value of the first predetermined value and a comparison value of the second predetermined value are determined respectively; wherein the comparison value is the first counting value or the second counting value.

[0135] In a possible implementation, a first counting period of the first timer and a second counting period of the second timer are the same but have different phases; the device further includes:

[0136] The second determination module 52 is used to determine the first predetermined value and the second predetermined value according to a preset target width of the pulse signal and a phase difference between the first counting period and the second counting period after obtaining the first counting value of the first timer and / or the second counting value of the second timer; and to determine a comparison value of the first predetermined value and a comparison value of the second predetermined value respectively according to the target width and the phase difference; wherein the comparison value is the first counting value or the second counting value.

[0137] In a possible implementation, the acquisition module 41 is specifically configured to:

[0138] The first timer counts at the transition edge of the first clock, and the second timer counts at the transition edge of the second clock.

[0139] The transition edge includes a rising edge and / or a falling edge.

[0140] In a possible implementation manner, obtaining the first count value of the first timer and / or the second count value of the second timer includes any one of the following manners:

[0141] The first timer detects and counts both the rising edge and the falling edge, and the second timer detects and counts both the rising edge and the falling edge.

[0142] The first timer detects and counts the rising edge or the falling edge, and the second timer detects and counts both the rising edge and the falling edge.

[0143] The first timer detects and counts both rising edges and falling edges, and the second timer detects and counts either a rising edge or a falling edge.

[0144] The first timer detects and counts the rising edge or the falling edge, and the second timer detects and counts the rising edge or the falling edge.

[0145] In a possible implementation manner, the directions of the first timer and the second timer are the same, or opposite.

[0146] The pulse width modulation device provided in this embodiment can execute the method provided in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be described in detail here.

[0147] In one example, based on the above embodiment, Fig. 9 A circuit diagram of a pulse width modulation circuit provided in an embodiment of the present application, such as Fig. 9 As shown, an embodiment of the present application provides a pulse width modulation circuit including a first timer, a second timer, a first comparator, a second comparator, a first multiplexer, a second multiplexer and a pulse width modulation control module.

[0148] The output ends of the first timer and the second timer are respectively connected to the input ends of the first multiplexer and the input ends of the second multiplexer; the output end of the first multiplexer is connected to the input end of the first comparator; the output end of the second multiplexer is connected to the input end of the second comparator; the input end of the first comparator is connected to the output end of the first multiplexer; the input end of the second comparator is connected to the output end of the second multiplexer; and the pulse width modulation control module is respectively connected to the first multiplexer, the second multiplexer, the first comparator and the second comparator.

[0149] The pulse width modulation control module is used to send a first selection signal to the first multiplexer according to a preset pulse width, and provide a second selection signal to the second multiplexer, and provide a first preset value to the first comparator according to the preset pulse width, and provide a second preset value to the second comparator.

[0150] The first multiplexer is used to send the count value of the timer corresponding to the received first selection signal to the first comparator.

[0151] The second multiplexer is used to send the count value of the timer corresponding to the received second selection signal to the second comparator.

[0152] The first comparator is used to generate a first signal according to the received first multiplexer output value and the first preset value; wherein the first signal is used to flip the pulse signal at a current moment.

[0153] The second comparator is used to generate a second signal according to the received second multiplexer output value and a second preset value; wherein the second signal is used to flip the pulse signal at the current moment.

[0154] Exemplarily, the pulse width modulation circuit includes a first timer, a second timer, a first comparator, a second comparator, a first multiplexer, a second multiplexer, and a pulse width modulation control module.

[0155] The output ends of the first timer and the second timer are connected to the input end of the first multiplexer and the input end of the second multiplexer respectively. The output end of the first multiplexer is connected to the input end of the first comparator respectively. The output end of the second multiplexer is connected to the input end of the second comparator; the input end of the first comparator is connected to the output end of the first multiplexer. The input end of the second comparator is connected to the output end of the second multiplexer. The pulse width modulation control module is connected to the first multiplexer, the second multiplexer, the first comparator and the second comparator respectively.

[0156] A pulse width modulation control module is used to send a first selection signal to a first multiplexer according to a preset pulse width, and provide a second selection signal to a second multiplexer, wherein the first selection signal and / or the second selection signal represent a selected timer. The first multiplexer is used to determine a corresponding timer according to the received first selection signal, and send the count value of the corresponding timer to a first comparator. The second multiplexer is used to determine a corresponding timer according to the received second selection signal, and send the count value of the corresponding timer to a second comparator. The first comparator is used to compare the received count value with a first preset value to generate a first signal, and the first signal is used to flip the pulse signal at the current moment. The second comparator is used to compare the received count value with a second preset value to generate a second signal, and the second signal is used to flip the pulse signal at the current moment.

[0157] In one example, the embodiment of the present application provides a microprocessor chip, which includes the pulse width modulation method or pulse signal width modulation circuit indicated in the above embodiment. For example, the microprocessor chip can be a micro central control chip, system-on-chip chip, etc., which can process digital signals, analog signals, or perform signal control functions, instruction processing and calculation functions, such as MCU, DSP, MPU, micro CPU, etc., and is not limited to this.

[0158] In one example, an embodiment of the present application provides a pulse width modulation device, which includes the pulse width modulation method or pulse signal width modulation circuit indicated in the above embodiments.

[0159] Fig.10 This is a schematic diagram of the structure of the pulse width modulation device provided in this application. Fig.10 As shown, the pulse width modulation device 50 provided in this embodiment includes: at least one processor 501 and a memory 502. Optionally, the device 50 also includes a communication component 503. The processor 501, the memory 502 and the communication component 503 are connected via a bus 504.

[0160] In a specific implementation process, at least one processor 501 executes the computer-executable instructions stored in the memory 502, so that at least one processor 501 executes the above method.

[0161] The specific implementation process of the processor 501 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0162] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the invention may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0163] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0164] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0165] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0166] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0167] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0168] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0169] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0170] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0171] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0172] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0173] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0174] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A pulse width modulation method, characterized in that: comprising a first timer and a second timer; The first timer counts a preset first clock, and the second timer counts a preset second clock; the method includes: Obtaining a first count value of the first timer and / or a second count value of the second timer; If it is determined that the first count value or the second count value is equal to a first predetermined value, a first signal is generated, and the pulse signal is flipped according to the first signal; If it is determined that the first count value or the second count value is equal to a second predetermined value, a second signal is generated, and the pulse signal is flipped according to the second signal.

2. The method according to claim 1, characterized in that A first counting period of the first timer is different from a second counting period of the second timer, and the method further includes: The first predetermined value and the second predetermined value are determined according to a preset target width of the pulse signal and a difference between the first counting period and the second counting period.

3. The method according to claim 2, characterized in that The method further comprises: According to the target width and the difference, a comparison value of the first predetermined value and a comparison value of the second predetermined value are determined respectively; wherein the comparison value is the first count value or the second count value.

4. The method according to claim 2, characterized in that: Determining the first predetermined value and the second predetermined value according to a preset target width of the pulse signal and a difference between the first counting period and the second counting period; Determining the comparison value of the first predetermined value and the comparison value of the second predetermined value respectively according to the target width and the difference, including: Determine the first predetermined value and the second predetermined value respectively according to the target width of the pulse signal, the first counting period, the second counting period, and the difference between the first counting period and the second counting period; A comparison value of the first predetermined value and a comparison value of the second predetermined value are determined according to the target width, the first counting cycle, the second counting cycle and the difference, respectively; wherein the comparison value is the first counting value or the second counting value.

5. The method according to claim 1, characterized in that The first counting period of the first timer and the second counting period of the second timer are the same but have different phases, and the method further includes: Determine the first predetermined value and the second predetermined value according to a preset target width of the pulse signal, a first counting period, a second counting period, and a phase difference between the first counting period and the second counting period; A comparison value of the first predetermined value and a comparison value of the second predetermined value are determined respectively according to a target width, a first counting cycle, a second counting cycle and a phase difference between the first counting cycle and the second counting cycle; wherein the comparison value is the first counting value or the second counting value.

6. The method according to claim 1, characterized in that The obtaining the first count value of the first timer and / or the second count value of the second timer includes: The first timer counts at the transition edge of the first clock, and the second timer counts at the transition edge of the second clock; The transition edge includes a rising edge and / or a falling edge.

7. The method according to claim 6, characterized in that The obtaining of the first count value of the first timer and / or the second count value of the second timer includes any one of the following methods: The first timer detects and counts both the rising edge and the falling edge, and the second timer detects and counts both the rising edge and the falling edge; The first timer detects and counts the rising edge or the falling edge, and the second timer detects and counts both the rising edge and the falling edge; The first timer detects and counts both the rising edge and the falling edge, and the second timer detects and counts the rising edge or the falling edge; The first timer detects and counts rising edges or falling edges, and the second timer detects and counts rising edges or falling edges.

8. The method according to any one of claim 1, characterized in that: The direction of the first timer is the same as that of the second timer, or is opposite to that of the first timer.

9. A pulse width modulation circuit, characterized in that: The circuit includes a first timer, a second timer, a first comparator, a second comparator, a first multiplexer, a second multiplexer, and a pulse width modulation control module; The output ends of the first timer and the second timer are connected to the input end of the first multiplexer and the input end of the second multiplexer respectively; the output end of the first multiplexer is connected to the input end of the first comparator; The output end of the second multiplexer is connected to the input end of the second comparator; the input end of the first comparator is connected to the output end of the first multiplexer; the input end of the second comparator is connected to the output end of the second multiplexer; the pulse width modulation control module is respectively connected to the first multiplexer, the second multiplexer, the first comparator and the second comparator; The pulse width modulation control module is used to send a first selection signal to the first multiplexer according to a preset pulse width, provide a second selection signal to the second multiplexer, and provide a first preset value to the first comparator according to the preset pulse width, and provide a second preset value to the second comparator; The first multiplexer is used to send the count value of the timer corresponding to the received first selection signal to the first comparator; The second multiplexer is used to send the count value of the timer corresponding to the received second selection signal to the second comparator; The first comparator is used to generate a first signal according to the received first multiplexer output value and the first preset value; wherein the first signal is used to flip the pulse signal at a current moment; The second comparator is used to generate a second signal according to the received second multiplexer output value and the second preset value; wherein the second signal is used to flip the pulse signal at a current moment.

10. A microprocessor chip, characterized in that: The microprocessor chip includes the pulse signal width modulation method according to any one of claims 1 to 8 or the pulse signal width modulation circuit according to claim 9.

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