Transparent bottom gate coplanar thin film transistor, preparation method thereof and display

Abstract

The invention provides a transparent bottom gate coplanar thin film transistor, a preparation method thereof and a display, and relates to the field of semiconductors, and the preparation method of the transparent bottom gate coplanar thin film transistor comprises the steps that S10, a gate electrode and an insulating layer are sequentially deposited on a substrate, the gate electrode covers a part of the surface of the substrate, and the insulating layer covers a part of the surface of the substrate; the insulating layer covers the gate electrode and the other part of the surface of the substrate; s20, forming a semiconductor layer on the insulating layer; s30, in a gas atmosphere, processing the semiconductor layer by using a laser direct writing method to form two semiconductor channels; and S40, respectively forming a source electrode and a drain electrode in the two semiconductor channels by adopting a laser direct writing method in a gas atmosphere to obtain the transparent bottom gate coplanar thin film transistor. According to the technical scheme, the laser direct writing technology is adopted, the active layer area and the source and drain electrodes are formed through one-time deposition, the method has the advantages of being simple in process and rapid in preparation, the size is accurate and controllable, and the method is suitable for preparing various specifications.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a transparent bottom-gate coplanar thin film transistor, a preparation method thereof and a display. Background Art

[0002] In recent years, in order to meet people's growing demand for display screens and their aesthetic pursuit of technological beauty and tactile feel, major display manufacturers have rushed to launch electronic products with large screens, full screens and curved screens as highlights. Large-size displays and flexible displays have swept the display market and become one of the biggest hot spots in the electronic display industry. Thin Film Transistor (TFT) backplane technology is the basic technology and core technology of the display industry. The metal oxide semiconductor layer of the Metal Oxide Thin Film Transistor (MOTFT) is mostly an amorphous structure with transparency and excellent large-area uniformity, which is suitable for preparation on flexible substrates; and MOTFT has a high mobility (10-100cm 2 / Vs), simple process and low cost, which is in line with the current requirements of future transparent display preparation directions such as large size and flexibility.

[0003] There is a large overlap area between the source and drain electrodes and the gate electrode of a conventional bottom-gate top-contact metal oxide thin film transistor, which introduces a large parasitic capacitance.

[0004] At present, the preparation of the active layer and source-drain electrodes of the traditional TFT integrated driving backplane requires multiple deposition, masking, and etching. This process is cumbersome, has great environmental pollution, low material utilization, and a single pattern that is difficult to adjust. Summary of the invention

[0005] The main purpose of the present invention is to provide a transparent bottom-gate coplanar thin film transistor, a preparation method thereof and a display, aiming to form an active layer region and a source-drain electrode by one-time deposition.

[0006] To achieve the above object, the present invention provides a method for preparing a transparent bottom-gate coplanar thin film transistor, comprising the following steps:

[0007] S10. depositing a gate electrode and an insulating layer on the substrate in sequence, wherein the gate electrode covers a portion of the surface of the substrate, and the insulating layer covers the gate electrode and other portions of the surface of the substrate;

[0008] S20. forming a semiconductor layer on the insulating layer;

[0009] S30. In a gas atmosphere, the semiconductor layer is processed by a laser direct writing method to form two semiconductor channels;

[0010] S40. In a gas atmosphere, a source electrode and a drain electrode are respectively formed in the two semiconductor channels by a laser direct writing method to obtain a transparent bottom-gate coplanar thin film transistor.

[0011] The present invention also provides a transparent bottom-gate coplanar thin film transistor, which is prepared according to the above-mentioned method for preparing the transparent bottom-gate coplanar thin film transistor.

[0012] The present invention further provides a display, comprising the transparent bottom-gate coplanar thin film transistor as described above.

[0013] The technical solution of the present invention forms a semiconductor channel on a semiconductor layer by adopting laser direct writing technology, and forms a source electrode and a drain electrode in the semiconductor channel. The active layer area and the source and drain electrodes are formed by one deposition using laser processing, and no additional deposition of the source and drain electrodes is required, and no multiple etching steps are required. The process is simple, the preparation is fast, and the material utilization rate is high. The length and width of the semiconductor channel can be flexibly adjusted, and the size can be precisely controlled. It is suitable for preparing TFT devices of various specifications and has a wide range of applications. In addition, the laser direct writing processing technology has the advantages of precise controllable processing area, high efficiency, and low temperature. The transparent metal oxide film can be precisely processed without damaging the substrate. The metal oxide film can be converted into a high-performance semiconductor film or a conductive film under different processing processes. The high-performance semiconductor film area of ​​the integrated drive backplane is first processed under suitable laser parameters and processing atmosphere, and then the parameters and atmosphere are adjusted to perform a second laser processing to form the source and drain electrodes, which can realize the preparation of a large-area TFT integrated drive substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0015] Figure 1 A schematic flow chart of an embodiment of a method for preparing a transparent bottom-gate coplanar thin film transistor provided in the present invention;

[0016] Figure 2 A schematic cross-sectional structure diagram of an embodiment of a transparent bottom-gate coplanar thin film transistor provided in the present invention;

[0017] Figure 3 The IV curve diagram of the transparent bottom-gate coplanar thin film transistor provided in Example 1 of the present invention;

[0018] Figure 4 An IV curve diagram of a transparent bottom-gate coplanar thin film transistor provided in Example 2 of the present invention;

[0019] Figure 5 This is an IV curve diagram of the transparent bottom-gate coplanar thin film transistor provided in Comparative Example 1 of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] 100. Transparent bottom-gate coplanar thin film transistor; 1. source electrode; 2. drain electrode; 3. semiconductor layer; 4. insulating layer; 5. gate electrode; 6. substrate.

[0022] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0023] To make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them.

[0024] It should be noted that, in the embodiments, those without specifying specific conditions are carried out according to normal conditions or conditions recommended by the manufacturer. Those without specifying the manufacturer of reagents or instruments used are conventional products that can be purchased commercially. In addition, the meaning of "and / or" appearing in the full text includes three parallel schemes, and "A and / or B" is taken as an example, including schemes A, B, or A and B that meet the same time. In addition, the technical schemes between the various embodiments can be combined with each other, but must be based on the ability of ordinary technicians in the field to achieve. When the combination of the technical schemes is contradictory or cannot be achieved, it should be considered that the combination of such technical schemes does not exist, and is not within the scope of protection required by the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work, all belong to the scope of protection of the present invention.

[0025] Tunnel field-effect transistors (TFETs) show great potential as low-power devices. Unlike conventional metal-oxide semiconductor field-effect transistors (MOSFETs), TFETs can break through the theoretical limit of subthreshold swing of 60mV / dec, making them a promising new device that can replace MOSFETs and lead the development of future low-power devices.

[0026] At present, with the increasing demand for the speed of thin film transistor circuits, in order to adapt to new technical requirements, the parasitic capacitance of thin film transistors needs to be reduced accordingly. Therefore, coplanar MOTFTs are produced. Since there is no overlap between the source and drain electrodes and the gate electrode, the coplanar MOTFT can greatly reduce the parasitic capacitance. The preparation of the active layer and source and drain electrodes of the traditional TFT integrated drive backplane requires multiple deposition, masking, and etching. The process preparation process is cumbersome, the environmental pollution is large, the material utilization rate is low, and the pattern is single and difficult to adjust.

[0027] Patent CN111696868A discloses a method for preparing a coplanar indium gallium zinc oxide thin film transistor, which improves the device performance of the IGZO thin film transistor by directly growing source and drain electrodes after patterning the IGZO source and drain regions.

[0028] Patent CN106098559A discloses a method for preparing a bottom-gate coplanar metal oxide thin film transistor, in which the active layer is deposited after the source and drain regions are patterned, so that the back of the active layer is not affected by the patterning of the source and drain regions.

[0029] Although the above two methods effectively improve the device performance of metal oxide thin film transistors, their preparation process involves multiple etching steps, the process is cumbersome and complicated, the material utilization rate is low, the environmental pollution is large, and the device structure and size are difficult to change due to process limitations. In addition, the above methods also require thermal annealing treatment to improve device performance, and have poor compatibility with flexible substrates, making it difficult to prepare low-cost, high-performance flexible devices.

[0030] Patent CN107204309A discloses a method for manufacturing a dual-gate metal oxide semiconductor TFT substrate and its structure. The method uses a photoresist mask to perform laser irradiation on the areas on both sides of the channel layer to form a contact area. The method requires multiple mask etching processes, the pattern is fixed and single, and the source and drain electrodes need to be prepared additionally, and the process is cumbersome.

[0031] Patent CN114122012A discloses a method of laser processing metal oxides. By changing the laser energy density, the oxygen vacancies in the metal oxide insulating layer are regulated, thereby improving the performance of TFT devices. However, this method can only improve the contact interface between the metal oxide insulating layer and the oxide semiconductor layer, and cannot effectively change the conductivity of the metal oxide.

[0032] In view of this, see Figure 1The present invention proposes a method for preparing a transparent bottom-gate coplanar thin film transistor, comprising the following steps: S10. depositing a gate electrode and an insulating layer on a substrate in sequence, wherein the gate electrode covers a portion of the surface of the substrate, and the insulating layer covers the gate electrode and other portions of the surface of the substrate; S20. forming a semiconductor layer on the insulating layer; S30. processing the semiconductor layer by a laser direct writing method in a gas atmosphere to form two semiconductor channels; S40. forming a source electrode and a drain electrode in the two semiconductor channels by a laser direct writing method in a gas atmosphere to obtain a transparent bottom-gate coplanar thin film transistor.

[0033] The technical solution of the present invention forms a semiconductor channel on a semiconductor layer by adopting laser direct writing technology, and forms a source electrode and a drain electrode in the semiconductor channel. The active layer area and the source and drain electrodes are formed by one deposition using laser processing, and no additional deposition of the source and drain electrodes is required, and no multiple etching steps are required. The process is simple, the preparation is fast, and the material utilization rate is high. The length and width of the semiconductor channel can be flexibly adjusted, and the size can be precisely controlled. It is suitable for preparing TFT devices of various specifications and has a wide range of applications. In addition, the laser direct writing processing technology has the advantages of precise controllable processing area, high efficiency, and low temperature. The transparent metal oxide film can be precisely processed without damaging the substrate. The metal oxide film can be converted into a high-performance semiconductor film or a conductive film under different processing processes. The high-performance semiconductor film area of ​​the integrated drive backplane is first processed under suitable laser parameters and processing atmosphere, and then the parameters and atmosphere are adjusted to perform a second laser processing to form the source and drain electrodes, which can realize the preparation of a large-area TFT integrated drive substrate.

[0034] In one embodiment, in step S30, during laser direct writing, the energy density of the laser is 100 mJ / cm 2 ~200mJ / cm 2 , the wavelength of the laser is 150nm to 1500nm; and / or, in step S40, during laser direct writing, the energy density of the laser is 100mJ / cm 2 ~200mJ / cm 2 , the wavelength of the laser is 150nm~1500nm.

[0035] The technical solution of the present invention adopts a laser energy density within a specific range (100mJ / cm 2 ~200mJ / cm 2) and wavelength (150nm~1500nm), it is possible to achieve precise modification of the surface microstructure of the semiconductor layer. This precise control can ensure high precision in the processing process and reduce unnecessary heat-affected areas, thereby improving the processing accuracy of semiconductor channels and electrodes, while reducing the heat during laser processing to avoid damaging the substrate; by adopting a suitable combination of energy density and wavelength, it is possible to effectively promote the absorption of materials and reduce nonlinear effects in the processing process, thereby improving processing efficiency; by adopting a wavelength of 150nm~1500nm, it can be applied to metals, semiconductors and some organic materials, which can expand the material selection range of the semiconductor layer and expand the application field of the preparation method.

[0036] In one embodiment, surfaces of the source electrode and the drain electrode are lower than a surface of the semiconductor layer, or surfaces of the source electrode and the drain electrode are flush with a surface of the semiconductor layer.

[0037] The technical solution of the present invention can effectively improve the performance of the coplanar MOTFT, reduce parasitic capacitance and contact resistance, and thus improve the operating frequency and switching speed of the device by making the surface of the source electrode and the drain electrode lower than the surface of the semiconductor layer, or making their surfaces flush with the surface of the semiconductor layer. The device structure of the coplanar MOTFT can greatly reduce the parasitic capacitance and effectively improve the response speed of the device because there is no overlap between the source and drain electrodes and the gate electrode.

[0038] In one embodiment, in step S30, the gas atmosphere includes at least one of air, argon, helium, nitrogen, oxygen and hydrogen; and / or, in step S40, the gas atmosphere includes at least one of argon, nitrogen, helium and oxygen.

[0039] The technical solution of the present invention adopts at least one of air, argon, helium, nitrogen, oxygen and hydrogen as the processing gas atmosphere in step S30, which indicates that step S30 can adapt to a variety of different processing conditions so that the step of laser direct patterning of semiconductor channels can be applied to a wide range of material processing scenarios; by adopting at least one of argon, nitrogen and helium as the processing environment, a more controllable and stable processing environment can be created, and an oxygen-free environment can be provided, thereby reducing the occurrence of electrode oxidation during laser direct writing processing, thereby improving the performance of TFT devices and increasing the mobility of TFT devices.

[0040] In one embodiment, the material of the gate electrode includes at least one of aluminum, silver, copper, molybdenum, platinum and indium tin oxide.

[0041] The technical solution of the present invention can improve the conductive performance of the gate electrode by adopting at least one of aluminum, silver, copper, molybdenum, platinum and indium tin oxide as the gate electrode, thereby improving the response speed and working efficiency of the overall circuit; wherein aluminum, molybdenum and platinum have high chemical stability and corrosion resistance, and can maintain good performance in harsh environments, so that the gate electrode has a long service life and can maintain stable electrical characteristics; molybdenum and copper have high mechanical strength, which can improve the structural stability of the gate electrode and can effectively avoid failures caused by mechanical stress; metals such as silver and copper have low resistivity, which can significantly reduce the resistance of the gate electrode, thereby reducing energy loss during signal transmission; indium tin oxide (ITO) is a transparent conductive oxide that can be used to manufacture transparent electrodes. Using ITO as a part of the gate electrode can not only maintain good conductivity, but also be compatible with transparent substrates or other transparent components, and be used to manufacture displays or other optical devices.

[0042] In one embodiment, the material of the semiconductor layer includes at least one of zinc oxide, indium zinc oxide, and gallium zinc oxide; and / or the thickness of the semiconductor layer is 5 nm to 200 nm.

[0043] The technical solution of the present invention adopts zinc oxide (ZnO), indium zinc oxide (IZO) and gallium zinc oxide (GZO) as semiconductor layer materials, wherein ZnO, IZO and GO are all transparent conductive oxides, have high electron mobility and good transparency, effectively improve the photoelectric conversion efficiency, so that the semiconductor layer can be applied to transparent devices; by controlling the thickness of the semiconductor layer between 5nm and 200nm, it helps to optimize the transmission and collection of carriers, reduce interface defects, thereby improving the overall electrical performance of the device, and reducing the driving voltage and energy consumption. The material of the semiconductor layer and the thickness of the semiconductor layer can be defined separately or simultaneously; when defined simultaneously, the stability and electrical performance of the semiconductor layer can be further improved.

[0044] In one embodiment, the material of the insulating layer includes at least one of silicon oxide, silicon nitride, and aluminum oxide; and / or the thickness of the insulating layer is 5 nm to 400 nm.

[0045] The technical solution of the present invention adopts silicon oxide (SiO2), silicon nitride (Si3N4), and aluminum oxide (Al2O3) as the insulating layer. These materials have excellent dielectric properties and high breakdown voltage, can effectively improve the insulation performance of the device, reduce leakage current, and extend the life of the device; by limiting the thickness of the insulating layer to between 5nm and 400nm, the insulation performance of the insulating layer and the process difficulty can be balanced. A thinner insulating layer can reduce parasitic capacitance and increase the switching speed of the device, and an appropriate thickness can also ensure sufficient insulation performance and reduce leakage current. The material of the above-mentioned insulating layer and the thickness of the insulating layer can be defined separately or simultaneously; when defined simultaneously, the insulation performance of the insulating layer can be further improved.

[0046] In one embodiment, in step S20, the semiconductor layer is formed by one of physical vapor deposition, plasma enhanced chemical vapor deposition, inkjet printing and spin coating.

[0047] The technical solution of the present invention forms a semiconductor layer by adopting methods such as physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), inkjet printing and spin coating, which can ensure that the film has good uniformity and density, thereby improving the quality of the semiconductor layer; in addition, different deposition methods are suitable for different materials. For example, PECVD is suitable for depositing high-quality oxide films, while inkjet printing is suitable for depositing solution-type materials, which provides more room for selecting the material most suitable for a specific application; physical vapor deposition and plasma enhanced chemical vapor deposition methods can achieve rapid deposition, thereby improving production efficiency; compared with traditional PVD and PECVD methods, inkjet printing and spin coating methods usually operate at lower temperatures, which can reduce energy consumption, thereby reducing the overall energy consumption of processing.

[0048] The present invention also provides a transparent bottom-gate coplanar thin film transistor, which is prepared according to the above-mentioned method for preparing the transparent bottom-gate coplanar thin film transistor.

[0049] Since the transparent bottom-gate coplanar thin film transistor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0050] The present invention further provides a display, comprising the transparent bottom-gate coplanar thin film transistor as described above.

[0051] Since the present display adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0052] The technical solution of the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the following embodiments are only used to explain the present invention, and are not used to limit the present invention.

[0053] Example 1

[0054] This embodiment provides a transparent bottom-gate coplanar thin film transistor, whose structure is as follows Figure 2 As shown, the preparation method thereof comprises the following steps:

[0055] 1. A 40nm thick a-IZO active layer was deposited on a substrate with a gate electrode and an insulating layer using a vacuum magnetron sputtering apparatus. The molar ratio of indium to zinc in the IZO target used was 1:4, the sputtering power was 90W, the sputtering atmosphere was Ar:O2=95:5, and the working pressure was 3.5mTorr.

[0056] 2. After sputtering, place the sample on the laser direct writing patterning processing platform. The laser wavelength is 248nm, the beam moving speed is set to 1230mm / s, the beam lateral overlap rate is 50%, and the beam longitudinal spacing is 41μm. First, in the atmosphere, set the laser energy density to 150mJ / cm 2 The a-IZO thin film channel region is patterned to form a high-performance a-IZO semiconductor channel with a channel length and width of 10 μm and 90 μm, respectively.

[0057] 3. After the a-IZO semiconductor channel region is formed, the laser energy density is set to 200mJ / cm at a pressure of 5mTorr and an argon atmosphere. 2 The source and drain electrode regions of the a-IZO thin film are processed to form conductive electrodes, thereby obtaining an a-IZO bottom-gate coplanar thin film transistor.

[0058] Example 2

[0059] This embodiment provides a transparent bottom-gate coplanar thin film transistor, and its preparation method is similar to that of embodiment 1, except that: the laser energy density of the laser treatment in step 2 is 100 mJ / cm 2 .

[0060] Comparative Example 1

[0061] This comparative example provides a transparent bottom-gate coplanar thin film transistor, and its preparation method is similar to that of Example 1, except that: in step 3, the gas atmosphere is Ar:O2=90:10.

[0062] Performance Testing

[0063] The transparent bottom-gate coplanar thin film transistors provided in Example 1, Example 2 and Comparative Example 1 were tested using a semiconductor parameter analyzer (Agilent B1500) to obtain output characteristic curves of each transparent bottom-gate coplanar thin film transistor. The test results are shown in FIG. Figures 3 to 5 As shown in the figure, V G Represents different gate voltages, V D represents the drain voltage. The device saturation mobility is calculated by formula 1, where μ sat represents the device saturation mobility, L represents the channel length, W represents the channel width, C i Represents the insulation capacitance, I DS represents the source-drain current, V GS Represents the gate voltage.

[0064]

[0065] The mobility of the transparent bottom-gate coplanar thin film transistor provided in Example 1 is 4.87 cm 2 V -1 s -1 ;

[0066] The mobility of the transparent bottom-gate coplanar thin film transistor provided in Example 2 is 4.48 cm 2 V -1 s -1 ;

[0067] The mobility of the transparent bottom-gate coplanar thin film transistor provided in Comparative Example 1 is 1.66 cm 2 V -1 s -1 .

[0068] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A method for preparing a transparent bottom-gate coplanar thin film transistor, characterized in that: The following steps are involved: S10. depositing a gate electrode and an insulating layer on the substrate in sequence, wherein the gate electrode covers a portion of the surface of the substrate, and the insulating layer covers the gate electrode and other portions of the surface of the substrate; S20. forming a semiconductor layer on the insulating layer; S30. In a gas atmosphere, the semiconductor layer is processed by a laser direct writing method to form two semiconductor channels; S40. In a gas atmosphere, a source electrode and a drain electrode are respectively formed in the two semiconductor channels by a laser direct writing method to obtain a transparent bottom-gate coplanar thin film transistor.

2. The method for preparing a transparent bottom-gate coplanar thin film transistor according to claim 1, characterized in that: In step S30, during laser direct writing, the energy density of the laser is 100 mJ / cm 2 ~200mJ / cm 2 , the wavelength of the laser is 150nm to 1500nm; and / or, In step S40, during laser direct writing, the energy density of the laser is 100 mJ / cm 2 ~200mJ / cm 2 , the wavelength of the laser is 150nm~1500nm.

3. The method for preparing a transparent bottom-gate coplanar thin film transistor according to claim 1, characterized in that: Surfaces of the source electrode and the drain electrode are lower than a surface of the semiconductor layer, or surfaces of the source electrode and the drain electrode are flush with a surface of the semiconductor layer.

4. The method for preparing a transparent bottom-gate coplanar thin film transistor according to claim 1, characterized in that: In step S30, the gas atmosphere includes at least one of air, argon, helium, nitrogen, oxygen and hydrogen; and / or, In step S40, the gas atmosphere includes at least one of argon, nitrogen, helium and oxygen.

5. The method for preparing a transparent bottom-gate coplanar thin film transistor according to claim 1, characterized in that: The material of the gate electrode includes at least one of aluminum, silver, copper, molybdenum, platinum and indium tin oxide.

6. The method for preparing a transparent bottom-gate coplanar thin film transistor according to claim 1, characterized in that: The material of the semiconductor layer includes at least one of zinc oxide, indium zinc oxide, and gallium zinc oxide; and / or, The thickness of the semiconductor layer is 5nm-200nm.

7. The method for preparing a transparent bottom-gate coplanar thin film transistor according to claim 1, characterized in that: The material of the insulating layer includes at least one of silicon oxide, silicon nitride and aluminum oxide; and / or, The thickness of the insulating layer is 5nm-400nm.

8. The method for preparing a transparent bottom-gate coplanar thin film transistor according to claim 1, characterized in that: In step S20, the semiconductor layer is formed by one of physical vapor deposition, plasma enhanced chemical vapor deposition, inkjet printing and spin coating.

9. A transparent bottom-gate coplanar thin film transistor, characterized in that: The transparent bottom-gate coplanar thin film transistor is prepared according to the method for preparing the transparent bottom-gate coplanar thin film transistor according to any one of claims 1 to 8.

10. A display, characterized in that: The display comprises the transparent bottom-gate coplanar thin film transistor according to claim 9.

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