Method for improving channel electric leakage of medium-voltage device

Abstract

The invention provides a method for improving channel electric leakage of a medium-voltage device, and the method comprises the steps: providing a semiconductor substrate which at least comprises a medium-voltage device region, shallow trench isolation structures are formed in the semiconductor substrate in the medium-voltage device region, and the semiconductor substrate between the shallow trench isolation structures is an active region, the surface of the shallow trench isolation structure is higher than the surface of the semiconductor substrate of the active region; etching the shallow trench isolation structure by adopting an etching process so as to reduce the height of the shallow trench isolation structure; performing back etching on the active region, wherein the surface of the active region after back etching is lower than the surface of the etched shallow trench isolation structure; forming an oxide layer on the surface of the active region and the surface of the shallow trench isolation structure; and forming a high dielectric material layer on the surface of the oxide layer. The problem that an existing medium-voltage device is prone to electric leakage is solved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a method for improving channel leakage of a medium voltage device. Background Art

[0002] OLED display drivers at the 28nm HV node have great advantages in being used in mobile devices and more energy-saving devices. They include low-voltage devices, medium-voltage devices, and high-voltage devices. Among them, medium-voltage devices are usually used as input-output (IO) devices, and their gate oxide thickness is between the gate oxide thickness of low-voltage devices and the gate oxide thickness of high-voltage devices.

[0003] Since the gate silicon oxide of the medium voltage device is relatively thick, in order to ensure the high uniformity of the high dielectric material layer and the metal gate, the active area of ​​the medium voltage area needs to be etched back before the gate oxide layer is grown in the medium voltage area. However, the shallow trench isolation structure formed in the medium voltage area is higher than the active area after the back etching. In the subsequent etching process to form the gate, the high dielectric material layer formed on the shallow trench isolation structure will be etched first, and in order to remove the high dielectric material layer on all areas, the high dielectric material layer formed on the active area (that is, the high dielectric material layer in the area outside the metal gate) will also be etched and removed. However, dry etching is used when etching the high dielectric material layer in the active area, and the damage of the plasma in the dry etching will accumulate to the high dielectric material layer under the gate that cannot be removed. Moreover, since the shallow trench isolation structure of the medium voltage device (especially the narrow medium voltage device) is higher than the active area, a large amount of positive charge will be generated in the shallow trench isolation structure. The positive charge increases the leakage of the NMOS tube on the side wall of the channel. Due to the center / edge effect in dry etching (the plasma in the middle area is relatively strong), the leakage of the middle area of ​​the device will be larger, and the corresponding threshold voltage Vt will be reduced, while the threshold voltage Vt of the edge area will be higher. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving channel leakage of a medium voltage device, so as to solve the problem that the existing medium voltage device is prone to leakage.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for improving channel leakage of a medium voltage device, the method comprising:

[0006] A semiconductor substrate is provided, which comprises at least a medium voltage device region, wherein a shallow trench isolation structure is formed in the semiconductor substrate of the medium voltage device region, and the semiconductor substrate between the shallow trench isolation structures is an active region, wherein a surface of the shallow trench isolation structure is higher than a surface of the semiconductor substrate of the active region;

[0007] Etching the shallow trench isolation structure using an etching process to reduce the height of the shallow trench isolation structure;

[0008] Etching back the active area, wherein the surface of the active area after etching back is lower than the surface of the shallow trench isolation structure after etching;

[0009] forming an oxide layer on the surface of the active area and the shallow trench isolation structure;

[0010] A high dielectric material layer is formed on the surface of the oxide layer.

[0011] Optionally, the thickness of the oxide layer includes

[0012] Optionally, the material of the oxide layer includes silicon oxide.

[0013] Optionally, the material of the shallow trench isolation structure includes silicon oxide.

[0014] Optionally, the semiconductor substrate further includes a low voltage device region and a high voltage device region, and the medium voltage device region is located between the two.

[0015] Optionally, the method further comprises the step of forming a gate material layer on the surface of the high dielectric material layer.

[0016] Optionally, the applicable technology node is less than or equal to 28 nm.

[0017] As described above, the method for improving the channel leakage of a medium voltage device of the present invention reduces the height of the shallow trench isolation structure by adding a step of reducing the height of the shallow trench isolation structure before etching back the active area of ​​the medium voltage region, thereby improving the damage caused by etching of high dielectric materials, avoiding the accumulation of positive charges in the shallow trench isolation structure, improving the uniformity problem of the center and edge of the device, and improving the leakage of the IO device; moreover, the above method is compatible with existing processes and there is no need for new process development. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Shown is a flow chart of a method for improving channel leakage of a medium voltage device according to the present invention.

[0019] Figure 2 It is a schematic diagram showing the structure of a semiconductor substrate having a medium voltage device region with a shallow trench isolation structure according to the present invention.

[0020] Figure 3 It is a schematic diagram showing the structure of a semiconductor substrate after etching the shallow trench isolation structure and etching back the active area.

[0021] Figure 4It is a schematic diagram showing the structure of a semiconductor substrate after forming an oxide layer and a high dielectric material layer according to the present invention. DETAILED DESCRIPTION

[0022] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0023] See also Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0024] like Figure 1 As shown, this embodiment provides a method for improving channel leakage of a medium voltage device, the method comprising:

[0025] A semiconductor substrate is provided, which comprises at least a medium voltage device region, wherein a shallow trench isolation structure is formed in the semiconductor substrate of the medium voltage device region, and the semiconductor substrate between the shallow trench isolation structures is an active region, wherein a surface of the shallow trench isolation structure is higher than a surface of the semiconductor substrate of the active region;

[0026] Etching the shallow trench isolation structure using an etching process to reduce the height of the shallow trench isolation structure;

[0027] Etching back the active area, wherein the surface of the active area after etching back is lower than the surface of the shallow trench isolation structure after etching;

[0028] forming an oxide layer on the surface of the active area and the shallow trench isolation structure;

[0029] A high dielectric material layer is formed on the surface of the oxide layer.

[0030] In this embodiment, the material of the semiconductor substrate includes silicon.

[0031] Specifically, the thickness of the oxide layer includes

[0032] Specifically, the material of the oxide layer includes silicon oxide.

[0033] Specifically, the material of the shallow trench isolation structure includes silicon oxide.

[0034] Specifically, the semiconductor substrate further includes a low voltage device region and a high voltage device region, and the medium voltage device region is located between the two.

[0035] Specifically, the method further comprises the step of forming a gate material layer on the surface of the high dielectric material layer. In this embodiment, the gate material layer is used to form a gate, and its material comprises metal.

[0036] Specifically, the applicable technology node is less than or equal to 28nm.

[0037] In summary, the method for improving the channel leakage of the medium voltage device of the present invention reduces the height of the shallow trench isolation structure by adding a step of reducing the height of the shallow trench isolation structure before etching back the active area of ​​the medium voltage region, thereby improving the damage caused by the etching of the high dielectric material, avoiding the accumulation of positive charges in the shallow trench isolation structure, improving the uniformity problem of the center and edge of the device, and improving the leakage of the IO device; moreover, the above method is compatible with the existing process and does not require the development of new processes. Therefore, the present invention effectively overcomes various shortcomings in the existing technology and has a high industrial utilization value.

[0038] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving channel leakage of a medium voltage device, characterized in that: The method comprises: A semiconductor substrate is provided, which comprises at least a medium voltage device region, wherein a shallow trench isolation structure is formed in the semiconductor substrate of the medium voltage device region, and the semiconductor substrate between the shallow trench isolation structures is an active region, wherein a surface of the shallow trench isolation structure is higher than a surface of the semiconductor substrate of the active region; Etching the shallow trench isolation structure using an etching process to reduce the height of the shallow trench isolation structure; Etch back the active area, wherein the surface of the active area after the etching is lower than the surface of the shallow trench isolation structure after etching; forming an oxide layer on the surface of the active area and the shallow trench isolation structure; A high dielectric material layer is formed on the surface of the oxide layer.

2. The method for improving channel leakage of a medium voltage device according to claim 1, characterized in that: The thickness of the oxide layer includes 3. The method for improving channel leakage of a medium voltage device according to claim 1, characterized in that: The material of the oxide layer includes silicon oxide.

4. The method for improving channel leakage of a medium voltage device according to claim 1, characterized in that: The material of the shallow trench isolation structure includes silicon oxide.

5. The method for improving channel leakage of a medium voltage device according to claim 1, characterized in that: The semiconductor substrate further comprises a low voltage device region and a high voltage device region, and the medium voltage device region is located between the two.

6. The method for improving channel leakage of a medium voltage device according to claim 1, characterized in that: The method further comprises the step of forming a gate material layer on the surface of the high dielectric material layer.

7. The method for improving channel leakage of a medium voltage device according to claim 1, characterized in that: Applicable technology nodes are less than or equal to 28nm.

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