Nano synapse integrated device and preparation method thereof
By using GaN-based nanowires to connect to microelectrodes, the problem of difficult preparation and low integration of nanosynaptic devices is solved, and a high-density and high-integration nanosynaptic integrated device is realized, with photoelectric pulse stimulation performance and suitable in brain-like computing system.
Patent Information
- Application Number
- CN202310916603.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-25
- Publication Date
- 2025-02-07
AI Technical Summary
The preparation of existing nanosynaptic devices is difficult and the integration is extremely low, which has greatly limited the application in brain-like computing systems and other fields.
GaN-based nanowires are used as synaptic elements in the device. By depositing an insulating layer on the substrate, preparing microelectrodes and growing GaN-based nanowires therein, combined with dielophoresis technology, the nanowires are connected to the microelectrode to form a high-density Nanosynaptic integrated devices.
It realizes nanosynaptic integrated devices with simple preparation technology and high integration, with the performance of optical pulse stimulation and electrical pulse stimulation, and is suitable for brain-like computing systems and other fields.
Smart Images
Figure CN119403165A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of artificial nerve technology, and in particular to a nano synapse integrated device and a preparation method thereof. Background Art
[0002] In the nervous system of the human brain, a synapse is defined as a connection point between two neurons, which serves as an important pathway for transmitting nerve impulses from the presynaptic neuron to the postsynaptic neuron. When an electrical signal is sent to the presynaptic neuron, an electrical spike called an action potential is generated, which then triggers an impulse in the postsynaptic neuron by releasing chemicals (so-called neurotransmitters) through the synaptic cleft. Artificial synapses mimic biological synapses in neuromorphic computing systems, and are applied to various detection devices and bionic structures based on this synaptic structure.
[0003] In recent years, with the rapid development of big data, the Internet, and artificial intelligence, traditional von Neumann architecture computing systems (independent memory and storage units) have been difficult to meet future application needs. In contrast, the human brain has a remarkable ability to process large amounts of data. It can store, integrate, and process information simultaneously through a dense coordinated network of synapses and neurons. When processing analog signals detected by sensory organs, such as visual information received by the retina, it can greatly reduce energy consumption and improve data management efficiency. Interconnected neural networks can perform distributed processing and achieve high-speed computing capabilities. Inspired by the human brain, artificial synaptic devices have emerged and have attracted widespread attention for their ability to process and memorize data simultaneously. Therefore, artificial synapses are expected to become an indispensable core component in the next generation of computing systems.
[0004] Nanowires are considered to be effective in simulating learning and cognition of artificial synapses because of their outstanding characteristics such as large surface / volume ratio and small size. At present, the preparation of nanosynaptic devices is difficult and the integration is extremely low. Therefore, high-density integrated systems based on nanosynaptic devices are difficult to prepare, and their application in fields such as brain-like computing systems is greatly limited. Summary of the invention
[0005] In view of this, the present invention provides a nano-synapse integrated device with simple preparation process and high integration and a preparation method thereof.
[0006] In order to achieve the above object, the present invention adopts the following technical solutions:
[0007] A nanosynapse integrated device, comprising:
[0008] substrate;
[0009] An insulating layer disposed on the substrate;
[0010] a plurality of nanosynapse units disposed on the insulating layer;
[0011] The nanosynaptic unit includes a first microelectrode and a second microelectrode arranged opposite to each other and a GaN-based nanowire arranged between the first microelectrode and the second microelectrode, wherein the first end of the GaN-based nanowire is bonded to the first microelectrode, and the second end of the GaN-based nanowire is bonded to the second microelectrode.
[0012] In a preferred embodiment, the GaN-based nanowires are GaN nanowires, AlGaN nanowires or InGaN nanowires.
[0013] In a preferred embodiment, the thickness of the first microelectrode and the second microelectrode are respectively 50 nm to 500 nm, and the distance between the first microelectrode and the second microelectrode is 0.8 μm to 5 μm.
[0014] In a preferred embodiment, the plurality of nanosynaptic units are arranged on the insulating layer in an array of M rows×N columns, where M and N are positive integers.
[0015] In a preferred embodiment, in the nanosynaptic unit, the first microelectrode is electrically connected to a first external electrode, and the second microelectrode is electrically connected to a second external electrode; wherein the first microelectrodes of all the nanosynaptic units are connected to a first external electrode one by one, and the second microelectrodes of all the nanosynaptic units are connected to the same second external electrode; or, the first microelectrodes of all the nanosynaptic units are connected to the same first external electrode, and the second microelectrodes of all the nanosynaptic units are connected to the same second external electrode.
[0016] In a preferred embodiment, a first covering electrode is formed on the first microelectrode and covers the first end of the GaN-based nanowire, and a second covering electrode is formed on the second microelectrode and covers the second end of the GaN-based nanowire.
[0017] In a preferred embodiment, the thickness of the first covering electrode and the second covering electrode are respectively 80 nm to 200 nm.
[0018] In a preferred embodiment, the first microelectrode and the first covering electrode together constitute a source electrode, the second microelectrode and the second covering electrode together constitute a drain electrode, and a gate layer is formed on the surface of the substrate facing away from the insulating layer.
[0019] Another aspect of the present invention is to provide a method for preparing the nanosynapse integrated device as described above, comprising:
[0020] Providing a substrate and depositing an insulating layer on the substrate;
[0021] Using a photolithography process to prepare a plurality of groups of first microelectrodes and second microelectrodes arranged opposite to each other on the insulating layer;
[0022] Growing GaN-based nanowires on an epitaxial substrate;
[0023] The GaN-based nanowires are peeled off from the epitaxial substrate and transferred between the first microelectrode and the second microelectrode;
[0024] The two ends of the GaN-based nanowire are bonded and connected to the first microelectrode and the second microelectrode respectively.
[0025] In a preferred embodiment, after the GaN-based nanowires are transferred between the first microelectrode and the second microelectrode, a dielectrophoresis process is applied to allow the two ends of the GaN-based nanowires to be overlapped onto the surfaces of the first microelectrode and the second microelectrode, respectively; wherein the process parameters of the dielectrophoresis process include: an AC voltage of 3V to 15V, a frequency of 1kHz to 1MHz, a power-on time of 10min to 20min, and a dielectrophoresis solution of acetone, isopropanol or ethanol.
[0026] The nanosynaptic integrated device and its preparation method provided by the embodiment of the present invention use GaN-based nanowires as synaptic elements in the device. The GaN-based nanowires have a controllable direct band gap and stable physical and chemical properties. They are compatible with existing semiconductor technology and have a mature and stable preparation process, simple process, and can be integrated with a light source on a chip to form an optoelectronic neuromorphic device, and can simultaneously have the performance of light pulse stimulation and electrical pulse stimulation. In the nanosynaptic integrated device, multiple nanosynaptic units are integrated on the same substrate, which can be prepared on a large scale, with a small volume and high integration. Among them, the integrated multiple nanosynaptic units can be set to be independently controlled or to be controlled as a whole array according to an arranged array pattern. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 is a cross-sectional view of the nanosynapse integrated device in Example 1;
[0028] Figure 2 is a schematic diagram of the distribution structure of the nanosynapse units on the insulating layer in Example 1;
[0029] Figure 3 is a SEM image of GaN-based nanowires connected between microelectrodes in Example 1;
[0030] Figure 4 is a diagram of the test results of light pulse stimulation response with different pulse times in Example 1;
[0031] Figure 5 is a diagram showing the results of the continuous light pulse stimulation response test in Example 1;
[0032] Figure 6 is a schematic diagram of the distribution structure of nanosynapse units on the insulating layer in another preferred embodiment;
[0033] Figure 7 is a schematic diagram of the distribution structure of nanosynapse units on the insulating layer in another preferred embodiment;
[0034] Figure 8 is a cross-sectional view of the nanosynapse integrated device in Example 2;
[0035] Fig. 9 is a graphical representation of the test results of simulating synaptic learning behavior in Example 2;
[0036] Fig.10 It is a cross-sectional view of the nanosynapse integrated device in Example 3. DETAILED DESCRIPTION
[0037] In order to make the purpose, technical scheme and advantages of the present invention clearer, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the present invention shown in the accompanying drawings and described according to the accompanying drawings are merely exemplary, and the present invention is not limited to these embodiments.
[0038] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.
[0039] Example 1
[0040] This embodiment provides a nanosynapse integrated device, Figure 1 is a cross-sectional view of the nanosynapse integrator of this embodiment at a position corresponding to a nanosynapse unit, Figure 2 Schematic diagram of the distribution structure of the nanosynapse units on the insulating layer in this embodiment.
[0041] See also Figure 1 and Figure 2 The nanosynaptic integrated device comprises a substrate 1 and an insulating layer 2 disposed on the substrate 1. The insulating layer 2 is provided with a plurality of nanosynaptic units 3, and the plurality of nanosynaptic units 3 are arranged in an array to form a nanosynaptic unit array 4.
[0042] The nanosynapse unit 3 includes a first microelectrode 31 and a second microelectrode 32 arranged opposite to each other and a GaN-based nanowire 33 arranged between the first microelectrode 31 and the second microelectrode 32, wherein the first end of the GaN-based nanowire 33 is bonded to the first microelectrode 31, and the second end of the GaN-based nanowire 33 is bonded to the second microelectrode 32. In this embodiment, the substrate 1 is selected as a silicon substrate, and the material of the insulating layer 2 is SiO2.
[0043] As a preferred solution, in this embodiment, the GaN-based nanowire is a GaN nanowire. In some other embodiments, the GaN-based nanowire may be an AlGaN nanowire or an InGaN nanowire.
[0044] As a preferred solution, in this embodiment, the thickness of the first microelectrode 31 and the second microelectrode 32 are 80nm respectively, specifically including a 20nm thick Ti metal layer and a 60nm thick Au metal layer stacked, and the spacing between the first microelectrode 31 and the second microelectrode 32 is 1μm. In some other embodiments, the thickness of the first microelectrode 31 and the second microelectrode 32 are preferably set in the range of 50nm to 500nm, and the spacing between the first microelectrode 31 and the second microelectrode 32 is preferably set in the range of 0.8μm to 5μm.
[0045] In a preferred embodiment, the plurality of nanosynaptic units 3 are arranged on the insulating layer 2 in an array of M rows × N columns, where M and N are positive integers. Figure 2 As shown, in this embodiment, the plurality of nanosynaptic units 3 are arranged in an array of 4 rows x 2 columns on the insulating layer 2. In some other embodiments, Figure 6 and Figure 7 As shown, the plurality of nanosynaptic units 3 are arranged on the insulating layer 2 in an array of 6 rows×1 column.
[0046] In the preferred solution, see Figure 2 In the nanosynaptic unit 3, the first microelectrode 31 is electrically connected to the first external electrode 51, and the second microelectrode 32 is electrically connected to the second external electrode 52. In some embodiments, Figure 2 and Figure 7 As shown, the first microelectrodes 31 of all the nanosynaptic units 3 are connected to a first external electrode 51 one by one, and the second microelectrodes 32 of all the nanosynaptic units 3 are connected to the same second external electrode 52, so that each of the nanosynaptic units 3 can be independently controlled.
[0047] In some other embodiments, Figure 6As shown, the first microelectrodes 31 of all the nanosynaptic units 3 are connected to the same first external electrode 51, and the second microelectrodes 32 of all the nanosynaptic units 3 are connected to the same second external electrode 52. At this time, all the nanosynaptic units 3 need to be controlled at the same time, that is, all the nanosynaptic units 3 can be controlled as a whole array according to the arranged array pattern.
[0048] The method for preparing the nanosynapse integrated device provided in this embodiment comprises the following steps:
[0049] The first step is to provide a substrate 1 and deposit an insulating layer 2 on the substrate 1 .
[0050] Step 2: Prepare multiple groups of first microelectrodes 31 and second microelectrodes 32 arranged opposite to each other on the insulating layer 2 by using a photolithography process.
[0051] Step 3: Grow GaN nanowires on the epitaxial substrate using molecular beam epitaxy, transfer them to an isopropanol solution by physical exfoliation and ultrasonically disperse them, so that the GaN nanowires and the isopropanol solution are fully integrated.
[0052] Step 4: Place the device obtained in the second step in the probe platform, extract 5 μL of the solution obtained in the third step with a micro-injector and drop it between the first microelectrode 31 and the second microelectrode 32, and use the dielectrophoresis method to make one end of the GaN nanowire in the solution overlap on the first microelectrode 31, and the other end of the GaN nanowire overlap on the second microelectrode 32. The process parameters of the dielectrophoresis process include: the AC voltage can be selected as 3V to 15V, the frequency can be set to 1kHz to 1MHz, the power-on time is within the range of 10min to 20min until the solution is completely volatilized, and the dielectrophoresis solution can be selected as acetone, isopropanol or ethanol.
[0053] Step 5: Place the device obtained in the fourth step into an annealing furnace for high-temperature annealing, so that the two ends of the GaN nanowire are bonded and connected to the first microelectrode 31 and the second microelectrode 32 respectively, thereby preparing a nanosynapse integrated device.
[0054] The surface of the nanosynaptic integrated device was observed by scanning electron microscopy (SEM). Figure 3 As shown, a single GaN nanowire can be seen connected between two microelectrodes.
[0055] The nanosynaptic integrated device obtained in this embodiment is subjected to an optical pulse stimulation test. Specifically, the first external electrode 51 and the second external electrode 52 are respectively connected to the two ends of a DC power supply, and a 5V DC voltage is applied to the first microelectrode 31 and the second microelectrode 32 through the first external electrode 51 and the second external electrode 52. The GaN nanowires are irradiated with ultraviolet light for optical pulse stimulation: (1) the output power of the ultraviolet lamp is 2W, and the pulse time is set to 100ms, 250ms, 500ms, 1000ms and 1500ms respectively. Multiple groups of tests are performed, such as Figure 4 The test results shown in Figure 2 show that in each set of tests, when there are two light pulses stimulating, the device has a memory function for the detected photon signal. (2) The output power of the UV lamp is 2W, the pulse time is set to 1s, and the GaN nanowire is tested for continuous light pulse stimulation. Figure 5 The test results shown in the figure show that when there is continuous signal source stimulation, the device will continue to respond, and when the signal source stops, the device response will slowly return to the initial state. From the test results, it can be seen that by changing the light power, pulse time and number of pulses of ultraviolet light, synaptic-like performance can be obtained, which has the performance of light pulse stimulation.
[0056] The nanosynapse integrated device obtained in this embodiment is subjected to an electric pulse stimulation test. Specifically, the first external electrode 51 and the second external electrode 52 are connected to the two ends of the pulse power supply, respectively, and a pulse voltage is applied to the first microelectrode 31 and the second microelectrode 32 through the first external electrode 51 and the second external electrode 52. The voltage amplitude is 3V and the voltage pulse time is 100ms. From the test results, it can be seen that by changing the time, number and voltage of the voltage pulse, the synapse-like performance can be obtained, which has the performance of electric pulse stimulation.
[0057] Example 2
[0058] The nanosynapse integrated device provided in this embodiment is based on the device structure provided in Example 1 and additionally has the following structure: Figure 8 A first covering electrode 61 is formed on the first microelectrode 31 and covers the first end of the GaN-based nanowire 33 , and a second covering electrode 62 is formed on the second microelectrode 32 and covers the second end of the GaN-based nanowire 33 .
[0059] In this embodiment, the first microelectrode 31 and the first covering electrode 61 together form a source electrode, and the second microelectrode 32 and the second covering electrode 62 together form a drain electrode.
[0060] In this embodiment, the thickness of the first cover electrode 61 and the second cover electrode 62 are 80 nm respectively. In some other embodiments, the thickness of the first cover electrode 61 and the second cover electrode 62 can be set in the range of 80 nm to 200 nm.
[0061] The difference between the preparation process of the nanosynapse integrated device of this embodiment and that of Embodiment 1 is that: referring to the preparation process steps of Embodiment 1, after proceeding to the fourth step of overlapping the GaN nanowire between the two microelectrodes, the first covering electrode 61 is first prepared on the first microelectrode 31 by the overlay method, and the second covering electrode 62 is prepared on the second microelectrode 32, and then the fifth step of annealing and bonding process is performed.
[0062] An electric pulse stimulation test is carried out on the nanosynaptic integrated device obtained in this embodiment. Specifically, the first external electrode 51 and the second external electrode 52 are respectively connected to the two ends of the pulse power supply, and a pulse voltage is applied to the source electrode and the drain electrode through the first external electrode 51 and the second external electrode 52. The voltage amplitude is 5V and the voltage pulse time is 1s, wherein the source electrode is used to simulate the presynaptic, the drain electrode is used to simulate the postsynaptic, the pulse power supply is used to simulate the presynaptic stimulation, and the GaN nanowire is used to simulate the synaptic effect.
[0063] Fig. 9 This is a diagram of the test results of simulating synaptic learning behavior. A total of 4 groups of tests were conducted in sequence, such as Fig. 9 Middle: From left to right, after completing the first group of 20 pulse stimulations, stop the electrical stimulation for a certain period of time before performing the second group of 20 pulse stimulations; after completing the second group of 20 pulse stimulations, stop the electrical stimulation for a certain period of time before performing the third group of 20 pulse stimulations; after completing the third group of 20 pulse stimulations, stop the electrical stimulation for a certain period of time before performing the fourth group of 20 pulse stimulations. This simulates the learning-forgetting-relearning process of the synapse: the initial 20 continuous pulse stimulations serve as the training process of the artificial synapse, which is similar to the learning process of the human brain. After the pulse stimulation is removed, the weight of the device gradually decreases, which is similar to the forgetting process of the human brain. After a period of time, when the pulse is applied again, only a smaller number of pulses are needed for the synaptic device to reach the memory amount before forgetting, which is similar to the relearning process of the human brain. Fig. 9 It can be seen that the nanosynaptic integrated device of this embodiment has the performance of simulating the learning-forgetting-relearning process of synapses. This learning-forgetting-relearning process can be used in the learning and recognition functions of future artificial neural networks.
[0064] The nanosynapse integrated device of this embodiment was compared with the device of Example 1 through long-term testing, and it was found that after the covering electrode was set on the microelectrode of this embodiment, the contact point between the GaN nanowire and the electrode could be effectively protected, thereby improving the reliability of the device.
[0065] Example 3
[0066] The nanosynapse integrated device provided in this embodiment is based on the device structure provided in Example 2 and additionally has the following structure: Fig.10 A gate layer 7 is formed on the surface of the substrate 1 facing away from the insulating layer 2. In a specific solution, a PCB circuit board can be added below the substrate 1, and the two are connected by silver paste, so that the PCB circuit board forms a gate.
[0067] The nanosynaptic integrated device obtained in this embodiment is subjected to an electric pulse stimulation test, specifically: the first microelectrode 31 and the first covering electrode 61 together form a source electrode connected to one end of a pulse power supply, and the other end of the pulse power supply is connected to the lead port of the gate layer 7; the source electrode is also connected to one end of a DC power supply, and the other end of the DC power supply is connected to a drain electrode composed of a second microelectrode 32 and a second covering electrode 62, the voltage of the DC power supply is set to 10V, the voltage of the pulse power supply is set to 5V, and the pulse time is 1s. The gate is used to simulate presynaptic, the drain electrode is used to simulate postsynaptic, the pulse power supply is used to simulate presynaptic stimulation, the DC power supply is used to supply energy to the source electrode, and the GaN nanowire is used to simulate double pulse facilitation behavior. Adding a gate in this embodiment can make the device easier to control.
[0068] In summary, the nanosynaptic integrated device and its preparation method provided by the embodiment of the present invention use GaN-based nanowires as synaptic elements in the device. GaN-based nanowires have controllable direct band gaps and stable physical and chemical properties. They are compatible with existing semiconductor technologies and have mature and stable preparation processes, simple processes, and can be integrated with light sources to form optoelectronic neuromorphic devices on-chip, and can have the performance of both light pulse stimulation and electrical pulse stimulation. In this nanosynaptic integrated device, multiple nanosynaptic units are integrated on the same substrate, which can be prepared on a large scale, with a small volume and high integration. In some specific embodiments, the multiple nanosynaptic units that are integrated can be controlled independently; in other specific embodiments, the multiple nanosynaptic units that are integrated can be controlled as a whole array according to the arranged array pattern.
[0069] It should be pointed out that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.
Claims
1. A nanosynaptic integrated device, characterized in that: include: substrate; An insulating layer disposed on the substrate; a plurality of nanosynapse units disposed on the insulating layer; The nanosynaptic unit includes a first microelectrode and a second microelectrode arranged opposite to each other and a GaN-based nanowire arranged between the first microelectrode and the second microelectrode, wherein the first end of the GaN-based nanowire is bonded to the first microelectrode, and the second end of the GaN-based nanowire is bonded to the second microelectrode.
2. The nanosynapse integrated device according to claim 1, characterized in that: The GaN-based nanowires are GaN nanowires, AlGaN nanowires or InGaN nanowires.
3. The nanosynapse integrated device according to claim 1, characterized in that: The thickness of the first microelectrode and the second microelectrode are respectively 50 nm to 500 nm, and the distance between the first microelectrode and the second microelectrode is 0.8 μm to 5 μm.
4. The nanosynapse integrated device according to claim 1, characterized in that: The plurality of nanosynaptic units are arranged on the insulating layer in an array of M rows×N columns, where M and N are positive integers respectively.
5. The nanosynapse integrated device according to claim 4, characterized in that: In the nanosynaptic unit, the first microelectrode is electrically connected to a first external electrode, and the second microelectrode is electrically connected to a second external electrode; wherein, The first microelectrodes of all the nanosynaptic units are connected to a first external electrode one by one, and the second microelectrodes of all the nanosynaptic units are connected to the same second external electrode; or, the first microelectrodes of all the nanosynaptic units are connected to the same first external electrode, and the second microelectrodes of all the nanosynaptic units are connected to the same second external electrode.
6. The nanosynapse integrated device according to any one of claims 1 to 5, characterized in that: A first covering electrode is formed on the first microelectrode and covers the first end of the GaN-based nanowire, and a second covering electrode is formed on the second microelectrode and covers the second end of the GaN-based nanowire.
7. The nanosynapse integrated device according to claim 6, characterized in that: The thickness of the first covering electrode and the second covering electrode are respectively 80 nm to 200 nm.
8. The nanosynapse integrated device according to claim 6, characterized in that: The first microelectrode and the first covering electrode together constitute a source electrode, the second microelectrode and the second covering electrode together constitute a drain electrode, and a gate layer is formed on a surface of the substrate facing away from the insulating layer.
9. A method for preparing a nanosynapse integrated device according to any one of claims 1 to 8, characterized in that: include: Providing a substrate and depositing an insulating layer on the substrate; Using a photolithography process to prepare a plurality of groups of first microelectrodes and second microelectrodes arranged opposite to each other on the insulating layer; Growing GaN-based nanowires on an epitaxial substrate; The GaN-based nanowires are peeled off from the epitaxial substrate and transferred between the first microelectrode and the second microelectrode; The two ends of the GaN-based nanowire are bonded and connected to the first microelectrode and the second microelectrode respectively.
10. The method for preparing a nanosynapse integrated device according to claim 9, characterized in that: After the GaN-based nanowires are transferred between the first microelectrode and the second microelectrode, a dielectrophoresis process is applied to allow the two ends of the GaN-based nanowires to overlap the surfaces of the first microelectrode and the second microelectrode, respectively; wherein the process parameters of the dielectrophoresis process include: an AC voltage of 3V to 15V, a frequency of 1kHz to 1MHz, a power-on time of 10min to 20min, and a dielectrophoresis solution of acetone, isopropanol or ethanol.