Semiconductor electronic device including heterostructure-based electronic component and manufacturing process

Abstract

The invention relates to a semiconductor electronic device including a heterostructure-based electronic component and a manufacturing process. A semiconductor electronic device is formed in a die of a substrate having a semiconductor material of a first conductivity type. The device has a heterostructure-based first electronic component having a body structure of semiconductor material extending over a substrate in a die and an epitaxial multilayer extending in contact with the body structure and having a heterostructure. The body structure of the first electronic component has a first doped region extending between the heterostructure and the substrate and having a semiconductor material of a second conductivity type different from the first conductivity type.

Description

Technical Field

[0001] The present disclosure relates to semiconductor electronic devices including heterostructure-based electronic components and manufacturing processes. Background Art

[0002] Semiconductor electronic devices including heterostructure-based electronic components such as HEMTs (High Electron Mobility Transistors) are known.

[0003] In practice, the operation of such electronic components is based on the electronic properties of a heterojunction between two different semiconductor materials.

[0004] In detail, in HEMT, the conductive channel is based on the formation of a two-dimensional electron gas (2DEG) layer with high-mobility electrons formed at a heterojunction, i.e., at an interface between semiconductor materials with different band gaps. For example, HEMTs based on a heterojunction between an aluminum gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer are known.

[0005] HEMTs, especially those based on AlGaN / GaN heterojunctions or heterostructures, have several advantages that make them particularly suitable and widely used in different applications. For example, the high breakdown threshold of HEMTs can be used for high-performance power switches; the high mobility of electrons in the conduction channel enables high-frequency amplifiers; in addition, the high concentration of electrons in the 2DEG allows for low on-state resistance (R ON ).

[0006] Additionally, HEMTs used in radio frequency (RF) applications generally provide better RF performance than similar silicon LDMOS devices.

[0007] The above electronic equipment is from <111> Silicon wafers are obtained starting either from sapphire (Al2O3) or silicon carbide substrates, and heterostructure-based electronic components are integrated in the heterostructures grown epitaxially on the wafer.

[0008] However, known electronic components based on heterostructures have electrical performance that depends on the operating conditions of the electronic device itself during use. Therefore, the corresponding electronic device has low reliability.

[0009] For example, the on-state resistance of a HEMT is known to have high variability in use; for example, its value can increase between 50% and 200% of the designed value, especially when the HEMT is used as a high-side switch in a circuit in a source-follower configuration. Summary of the invention

[0010] According to the present disclosure, a semiconductor electronic device and a manufacturing process include: a tube core, including a substrate having a semiconductor material of a first conductivity type; a first electronic component, including a main structure of the semiconductor material extending on the substrate; and an epitaxial multilayer, extending in contact with the main structure and including a heterostructure; and a separation region, extending in the tube core and surrounding the epitaxial multilayer and located between the epitaxial multilayer and the main structure, wherein the main structure of the first electronic component includes a first doped region extending between the heterostructure and the substrate and having a semiconductor material of a second conductivity type different from the first conductivity type. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a better understanding of the present disclosure, embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0012] Figure 1 shows a top plan view of a semiconductor electronic device according to one embodiment;

[0013] Figure 2 yes Figure 1 A cross-sectional view of the electronic device along the section line II-II;

[0014] Figure 3 According to an embodiment Figure 1 an electrical equivalent diagram of a portion of the electronic equipment; and

[0015] Figure 4A-4H Shows Figure 2 Cross-section of a portion of a device in successive manufacturing steps. DETAILED DESCRIPTION

[0016] The following description refers to the arrangements shown in the accompanying drawings. Therefore, terms such as "above", "below", "top", "bottom", "right", "left", "high", "low", etc. are related to the accompanying drawings and should not be interpreted in a limiting manner.

[0017] Figure 1 A semiconductor electronic device (hereinafter simply referred to as device) 1 is shown, which is located in a Cartesian reference system XYZ having a first X axis, a second Y axis and a third Z axis.

[0018] The device 1 comprises a die 3 and one or more electronic components 5 based on a heterostructure, wherein a first HEMT 5A and a second HEMT 5B are connected in a Figure 1 It is shown integrated in die 3.

[0019] After a dicing step of the semiconductor wafer, dies 3 are obtained.

[0020] The first HEMT 5A is integrated in an active area 7A of the die 3 , which active area 7A is laterally delimited by corresponding insulating structures 8 .

[0021] The second HEMT 5B is integrated in an active area 7B of the chip 3 , which is different from the active area 7A and is laterally delimited by corresponding insulating structures 9 .

[0022] Optionally, the device 1 may also include one or more silicon-based electronic components, for example of active or passive type, which are also integrated in the die 3. For example, Figure 1 In the embodiment shown in FIG. 1 , the device 1 may include one or more MOSFETs 10A, one or more BJTs 10B, and / or one or more passive components 10C, such as diodes and resistors.

[0023] In practice, the operation of silicon-based electronic components is based on the electronic properties of a single semiconductor material, particularly silicon.

[0024] exist Figure 1 In FIG. 3 , as indicated by dashed lines, the MOSFET 10A, the BJT 10B and the passive element 10C are each integrated in a corresponding active region 11A, 11B, 11C of the die 3 .

[0025] Depending on the specific application of the device 1 , the active regions 11A, 11B, 11C may be electrically insulated from one another or in electrical contact with one another.

[0026] For example, the active regions 11A, 11B, 11C may be electrically insulated from one another via BCD (Bipolar-CMOS-DMOS) technology.

[0027] exist Figure 1 In the embodiment of FIG. 8 , the active regions 11A, 11B, 11C are arranged outside the insulating structures 8, 9. However, depending on the specific application, one or more of the silicon-based electronic components 10 may be integrated in the active regions 7A and / or 7B.

[0028] refer to Figure 2 In cross section, the die 3 comprises a substrate 15 and a device region 16 extending on the substrate 15 and in which the heterostructure-based component 5 and the silicon-based component 10 (if present) are integrated.

[0029] The active area 7A forms the first front surface 3A of the die 3 .

[0030] The substrate 15 is made of a semiconductor material, in particular, a single-crystalline semiconductor material, and has a top surface 15A.

[0031] In detail, in this embodiment, the substrate 15 is made of single crystal silicon, and in particular, the top surface 15A is shaped according to the crystal orientation. <111> Directional.

[0032] In this embodiment, the substrate 15 is of P type and has a resistivity between 0.1 Ω·cm and 20 Ω·cm, for example.

[0033] The first HEMT 5A comprises a main structure 20 of semiconductor material extending in the die 3 within the active area 7A on the substrate 15 and an epitaxial multilayer 21 in contact with the main structure 20 and comprising a heterostructure 22 of a layer configured to accommodate a two-dimensional gas of charge carriers.

[0034] In practice, the epitaxial multilayer 21 is a heteroepitaxial multilayer grown starting from the host structure 20 .

[0035] The main structure 20 , here silicon, can be of single-crystalline type, in particular having the same crystal orientation as the substrate 15 .

[0036] The main structure 20 comprises at least one doped region having a conductivity type different from that of the substrate 15 and arranged between the heterostructure 22 and the substrate 15 , in particular below the heterostructure 22 and facing the latter.

[0037] In this embodiment, the main structure 20 includes a plurality of doped regions, hereinafter referred to as: a first epitaxial region 25 ; a second epitaxial region 26 ; a third epitaxial region 27 ; a fourth epitaxial region 28 ; and a fifth epitaxial region 29 .

[0038] Depending on the specific application, epitaxial regions 25 - 29 may be formed from one or more epitaxial layers grown on substrate 15 .

[0039] The first epitaxial region 25 has a conductivity type different from that of the substrate 15; that is, here it is N-type.

[0040] The first epitaxial region 25 is arranged below the epitaxial multilayer 21 in parallel with the third axis Z. In other words, the first epitaxial region 25 faces the epitaxial multilayer 21. Figure 2 In the embodiment of FIG. 5 , a certain distance is maintained from the epitaxial multilayer 21 .

[0041] The first epitaxial region 25 may be a region buried in the die 3 .

[0042] In detail, the first epitaxial region 25 extends in direct contact with the substrate 15 .

[0043] In practice, the main structure 20 is delimited below, ie in the direction along the third axis Z of the substrate 15 , by the first epitaxial region 25 .

[0044] The first epitaxial region 25 may have a uniform or variable doping level along the first axis, the second axis and / or the third axis Z, for example, with a doping level between 8·10·m 14Atom / cm 3 and 5.10 19 Atom / cm 3 The doping level is between , for example, such that the resistivity is between 0.02 Ω·cm and 20 Ω·cm.

[0045] In particular, the first epitaxial region 25 may have a peak doping level that is higher than a peak doping level of the substrate 15. This may result in a depletion region extending mainly in the substrate 15 between the first epitaxial region 25 and the substrate 15 in use.

[0046] The second epitaxial region 26 extends on the first epitaxial region 25 .

[0047] In detail, the epitaxial region 26 extends from the first front surface 3A of the die 3 along the third axis Z deep into the die 3 up to the first epitaxial region 25 .

[0048] Depending on the specific application, the second epitaxial region 26 may have the same or different doping type as the substrate 15 , in particular here the same doping type (P).

[0049] The second epitaxial region 26 may have a uniform or variable doping level along the first axis, the second axis and / or the third axis Z, for example, with a doping level between 8·10·m·s and 1·m·s. 14 Atom / cm 3 and 5.10 19 Atom / cm 3 The doping level is between , for example, such that the resistivity is between 0.02 Ω·cm and 20 Ω·cm.

[0050] The third epitaxial region 27 extends below the epitaxial multilayer 21 in the die 3 and faces the epitaxial multilayer 21 parallel to the third axis Z.

[0051] The third epitaxial region 27 may be a region buried in the die 3 .

[0052] In detail, the third epitaxial region 27 extends in the second epitaxial region 26 and maintains a certain distance from the first epitaxial region 25 .

[0053] The third epitaxial region 27 may be of P type or N type (in Figure 1 In the embodiment of the present invention, the doping level of the first axis, the second axis and / or the third axis Z may be uniform or variable, for example, with a doping level between 8·10 14 Atom / cm 3 and 5.10 19 Atom / cm 3The doping level of the first and third epitaxial regions 25, 27 is between 100 Ω·cm and 100 Ω·cm, for example so as to have a resistivity between 0.02 Ω·cm and 20 Ω·cm. In case the first HEMT 5A is designed to operate at high voltage relative to the substrate 15, for example starting from approximately 20 V, for example 60 V, 100 V or 650 V, the presence of both first and third epitaxial regions 25, 27, both of N-type (i.e. of a type different from that of the substrate 15) may be useful for simplifying the manufacture of the device 1 and for obtaining excellent electrical performance of the device 1 in use.

[0054] The fourth epitaxial region 28 extends on the third epitaxial region 27 and has a central portion 28A and a peripheral portion 28B surrounding the central portion 28A.

[0055] In this embodiment, the epitaxial multilayer 21 is grown starting from the fourth epitaxial region 28, in particular starting from the corresponding central portion 28A.

[0056] exist Figure 1 In the embodiment of FIG. 2 , the peripheral portion 28B is connected to the central portion 28A.

[0057] In addition, Figure 1 In the embodiment of the present invention, the peripheral portion 28B contacts the second epitaxial region 26. In detail, in this embodiment, the peripheral portion 28B of the fourth epitaxial region 28 is laterally connected to the second epitaxial region 26 in parallel with the first axis X.

[0058] The fourth epitaxial region 28 may be of N-type or P-type (here N-type) and may have a uniform or variable doping level, for example, with a doping level between 8·10 14 Atom / cm 3 and 5.10 19 Atom / cm 3 The doping level is between , for example, such that the resistivity is between 0.02 Ω·cm and 20 Ω·cm.

[0059] In particular, the fourth epitaxial region 28 may have a peak doping level that is lower than a peak doping level of the third epitaxial region 27. This may be useful for optimizing the growth of the epitaxial multilayer 21 during manufacturing.

[0060] The fifth epitaxial region 29 extends over the fourth epitaxial region 28 , in particular within the second epitaxial region 26 .

[0061] In detail, the fifth epitaxial region 29 extends on the peripheral portion 28B of the fourth epitaxial region 28 , and in particular overlies it.

[0062] The fifth epitaxial region 29 may be of P-type or N-type (here, N-type) and have a uniform or variable doping level, for example, so as to have a resistivity between 0.1 Ω·cm and 20 Ω·cm.

[0063] The epitaxial multilayer 21 extends over the central portion 28A of the fourth epitaxial region 28, in particular in direct contact therewith, up to a top surface 30. The top surface 30 forms a second front surface of the active area 7A.

[0064] In practice, the epitaxial multilayer 21 grows starting from the fourth epitaxial region 28 .

[0065] In general, depending on the specific application, the thickness of the main structure 20 along the third axis Z below the epitaxial multilayer 21, i.e., the thickness measured between the bottom surface of the epitaxial multilayer 21 and the top surface 15A of the substrate 15, can be between 5μm and 30μm, for example approximately 15μm.

[0066] The first HEMT 5A is integrated in the heterostructure 22 of the epitaxial multilayer 21 .

[0067] exist Figure 2 In an embodiment of the present invention, the epitaxial multilayer 21 further comprises a transition region 32 formed by one or more buffer layers (not shown here) overlying each other and arranged between the fourth epitaxial region 28 and the heterostructure 22. The transition region 32 may be useful during the manufacture of the device 1 to facilitate the epitaxial growth of the heterostructure 22 on the fourth epitaxial region 28.

[0068] For example, the transition region 32 may be formed of an aluminum nitride (AlN) layer extending on and in direct contact with the fourth epitaxial region 28 and an aluminum gallium nitride (AlGaN) layer extending on and in direct contact with the AlN layer.

[0069] The heterostructure 22 includes a compound semiconductor material containing elements of Group III and Group V of the periodic table.

[0070] In this embodiment, heterostructure 22 forms a top surface 30 of epitaxial multilayer 21 .

[0071] Depending on the specific manufacturing steps used to produce the device 1 , the top surface 30 of the epitaxial multilayer 21 may extend at coordinates along the third axis Z that are the same as or different from the coordinates of the first front surface 3A of the die 3 .

[0072] In particular, in this embodiment, the top surface 30 of the epitaxial multilayer 21 extends a smaller distance from the substrate 15 than the first front surface 3A of the die 3 , measured along the third axis Z. This may enable improved manufacturing of the device 1 .

[0073] The heterostructure 22 includes a channel layer 35 and a barrier layer 36 overlying each other.

[0074] The channel layer 35 is made of a first semiconductor material, for example gallium nitride (GaN) or an alloy comprising gallium nitride, such as InGaN, here gallium nitride (GaN), and extends over the transition region 32 , in particular in direct contact therewith.

[0075] The barrier layer 36 is made of a second semiconductor material, such as a compound based on a ternary or quaternary alloy of gallium nitride, such as Al x Ga 1-x N, AlInGaN, In x Ga 1-x N、Al x In 1-x Al, AlScN, here aluminum gallium nitride (AlGaN), extends on the channel layer 35 , in particular in direct contact therewith, up to the top surface 30 of the epitaxial multilayer 21 .

[0076] According to specific applications, the channel layer 35 and the barrier layer 36 may be of intrinsic type, P type, or N type; in particular, both the channel layer 35 and the barrier layer 36 may be of N type.

[0077] For example, when barrier layer 36 is AlGaN, the presence of aluminum atoms may make barrier layer 36 N-type.

[0078] The heterostructure 22 is configured to accommodate a two-dimensional gas of (mobile) charge carriers, in particular electrons here (2DEG), which is arranged between the channel layer 35 and the barrier layer 36 , in particular at the interface between the channel layer 35 and the barrier layer 36 .

[0079] An insulating region may extend over the top surface 3A, 30, for example, in a manner known per se and serving the functions of passivation, electrical insulation etc., depending on the specific application.

[0080] The first HEMT 5A also includes surface structures, such as various conductive and / or insulating regions that may vary depending on the specific type of the first HEMT 5A, that extend over the top surface 30 of the epitaxial multilayer 21 and form functional regions of the first HEMT 5A.

[0081] In this embodiment, the first HEMT 5A comprises a source region 40 and a drain region 41 made of a conductive material, which extend along a first axis X at a distance from each other.

[0082] The source region 40 may form a closed line having a substantially circular shape in a top plan view, with two portions at Figure 2 For example, according to a specific design layout, the source region 40 may have a circular, polygonal, regular or irregular shape.

[0083] The drain region 41 may, for example, have a stripe-like shape elongated along the second axis Y, or a different shape, such as a circular, polygonal, regular or irregular shape, in a top plan view.

[0084] The source region 40 and the drain region 41 are in electrical contact, in particular ohmic contact, with the heterostructure 22 , in particular with the two-dimensional gas formed at the interface between the channel layer 35 and the barrier layer 36 , and respectively form a source terminal S and a drain terminal D of the first HEMT 5A.

[0085] exist Figure 2 In the embodiment of FIG. 4 , the source region 40 and the drain region 41 extend in a direction parallel to the third axis Z up to the top surface 30 .

[0086] However, depending on the specific application, the source region 40 and the drain region 41 may extend parallel to the third axis Z and also partially pass through the heterostructure 22 , for example through part of the barrier layer 36 or through the entire thickness of the barrier layer 36 , in particular extending to the interface with the channel layer 35 .

[0087] The surface structure of the first HEMT 5A further comprises a gate structure, here formed by a channel-modulation region 43 and a gate-contact region 44 , which can be biased to electrically control the formation of a two-dimensional gas in the heterostructure 22 between the source region 40 and the drain region 41 .

[0088] The gate structures 43, 44 extend between the source region 40 and the drain region 41. The gate structures 43, 44 may form a closed line having a substantially circular shape in a top plan view, with two portions at Figure 2 For example, according to a specific design layout, the gate structures 43 and 44 may have a circular, polygonal, regular or irregular shape.

[0089] In practice, the gate structures 43 , 44 may be arranged internally with respect to the source region 40 , for example in a substantially concentric manner with respect to the source region 40 .

[0090] The gate structures 43 , 44 form the gate terminal G of the first HEMT 5A.

[0091] In this embodiment, the first HEMT 5A is of a normally-off type, ie, an enrichment type.

[0092] In detail, in this embodiment, the channel-modulation region 43 is made of a semiconductor material and has a conductivity type different from that of the barrier layer 36, for example, a P-type. In particular, the channel-modulation region 43 may be made of P-type gallium nitride (p-GaN).

[0093] However, the channel-modulation region 43 may be formed of a combination of different materials including a dielectric layer, a metal layer, and / or a semiconductor layer serving as a control electrode having an appropriate work function.

[0094] The channel-modulation region 43 extends along the first axis X on the top surface 30 between the source region 40 and the drain region 41 .

[0095] A gate contact region 44 made of an electrically conductive material extends in electrical contact with the channel modulation region 43 , in particular in this case in direct contact therewith.

[0096] The device 1 further comprises a separation region 50 extending in the die 3 within the active area 7A.

[0097] In detail, the separation region 50 extends on the fourth epitaxial region 28 , in particular is in direct contact therewith, and surrounds the epitaxial multilayer 21 .

[0098] exist Figure 2 In the embodiment of FIG. 5 , the separation region 50 extends parallel to the first axis X between the epitaxial multilayer 21 and the fifth epitaxial region 29 .

[0099] In detail, the separation region 50 includes: a defined region 52, for example including oxide, in particular silicon oxide, which extends over and is in direct contact with the fourth epitaxial region 28; and a polycrystalline region 53, which is made of the same material (silicon) as the fifth epitaxial region 29, extending over and is in direct contact with the defined region 52.

[0100] The defined region 52 may be formed of a single layer, such as an oxide layer, in particular a silicon oxide layer, or may be formed of multiple layers, such as including one or more oxide layers and / or one or more nitride layers.

[0101] In detail, according to one embodiment, the definition region 52 may be made of silicon oxide.

[0102] According to various embodiments, the defined region 52 may include an oxide layer, in particular a silicon oxide layer, and a nitride layer. According to one embodiment, the oxide layer may be in direct contact with the semiconductor layer 18 .

[0103] The presence of an oxide, in particular silicon oxide, allows simplifying the manufacture of the heterostructure 22 of the first transistor 5A.

[0104] The defined region 52 may have a thickness along the third axis Z, for example, between 7 nm and 300 nm, in particular and between.

[0105] In this embodiment, the polycrystalline region 53 has a polycrystalline structure.

[0106] In this embodiment, the polycrystalline region 53 and the fifth epitaxial region 29 are a monolithic structure.

[0107] The polycrystalline region 53 has an outer sidewall 55, which separates the polycrystalline region 53 from the fifth epitaxial region 29. The outer sidewall 55 has an inclination, which may depend on the crystal orientation of the fifth epitaxial region 29 and on the thickness of the defined region 52 along the third axis Z. For example, in the fifth epitaxial region 29, the outer sidewall 55 may be inclined according to the crystal orientation. <111> In this orientation, the outer sidewall 55 may form an angle of approximately 54° with a direction parallel to the first axis X.

[0108] The polycrystalline region 53 also has an inner sidewall 56 opposite to the outer sidewall 55 , and the inner sidewall 56 faces the epitaxial multilayer 21 .

[0109] The epitaxial multilayer 21 has a peripheral portion arranged outside the source region 40 , the peripheral portion extending in contact with the inner sidewall 56 of the separation region 50 .

[0110] The shape of the peripheral portion depends on the specific manufacturing steps used to form the device 1, which are not described in detail here and are only Figure 2 Schematically illustrated in FIG.

[0111] For example, the epitaxial multilayer 21 may also be conformally grown on the inner sidewall 56 .

[0112] Separation region 50 may be useful during fabrication to facilitate good crystal quality of epitaxial multilayer 21, as described below with reference to Figure 4A-4H Described in detail.

[0113] Furthermore, the presence of polycrystalline region 53 may be useful for reducing stresses caused by the lattice mismatch between the material forming epitaxial multilayer 21 (e.g., GaN) and the material forming host structure 20 (e.g., silicon). Thus, the presence of polycrystalline region 53 may help reduce the risk of dislocations occurring in die 3 (and thereby reduce the risk that device 1 may be damaged).

[0114] Depending on the specific manufacturing steps used to produce the device 1, the shape and structure of the separation area 50 can be relative to the reference Figure 2 There are variations from what is shown and described. For example, the separation region 50 may not even be present.

[0115] Depending on the specific application and the specific layout of the active area 7A, the device 1 may also include one or more insulating or conductive areas at the first front surface 3A. Figure 2 An insulating region 58 , for example made of silicon oxide, is shown extending around the epitaxial multilayer 21 from the surface 3A into the main structure 20 .

[0116] In detail, the insulating region 58 is in contact with (connected to) the epitaxial multilayer 21 .

[0117] refer to Figure 2 In the embodiment shown in FIG. 5 , the insulating region 58 is connected to the interface between the channel layer 35 and the barrier layer 36 . This may be useful for electrically isolating the 2DEG from the host structure 20 .

[0118] The insulating structure 8 of the first HEMT 5A extends around the body structure 20 of the first HEMT 5A in the die 3 ; in particular, it is connected to (in contact with) the body structure 20 .

[0119] In detail, the insulating structure 8 extends in the die 3 from the first front surface 3A up to the substrate 15 , being in contact therewith.

[0120] In practice, the insulating structure 8 delimits a main structure 20 laterally within the die 3 .

[0121] exist Figure 2 In the embodiment of the present invention, the insulating structure 8 is a junction insulating structure configured to form a PN junction along the side of the main structure 20, especially around it. However, the insulating structure 8 can be of different types, such as a deep trench isolation (DTI) structure.

[0122] In detail, the insulating structure 8 includes a first junction region 60 of an N-type semiconductor material (silicon here) and a second junction region 61 of a P-type semiconductor material (silicon here) adjacent to each other.

[0123] In particular, Figure 2 In the embodiment of FIG. 5 , the first and second junction regions 60 , 61 are in contact with each other.

[0124] The first and second junction regions 60, 61 may be formed by growing one or more epitaxial layers on the substrate 15 and subsequently implanting or diffusing dopant species, in a manner known per se.

[0125] The first junction region 60 extends in a direction parallel to the third axis Z between the substrate 15 and the first front surface 3A of the die 3 .

[0126] In detail, the first junction region 60 is in contact with the substrate 15 ; in particular, it extends from the top surface 15A of the substrate 15 up to the first front surface 3A.

[0127] The first junction region 60 extends in a direction parallel to the first axis X, adjacent to the main structure 20, and in particular connected to (contacting) the first and second epitaxial regions 25, 26. The fact that the first junction region 60 is in contact with the first epitaxial region 25 allows the first junction region 60 to be used to bias the first epitaxial region 25 in use.

[0128] The first junction region 60 has the same conductivity type as the first epitaxial region 25 .

[0129] Depending on the specific application, the first junction region 60 may have a uniform or variable doping level parallel to the third axis Z. For example, the first junction region 60 may have a doping level between 1·10 15 Atom / cm 3 and 5.10 18 Atom / cm 3 between the doping levels.

[0130] The second junction region 61 extends parallel to the third axis Z between the substrate 15 and the first front surface 3A of the die 3 .

[0131] In detail, the second junction region 61 is in contact with the substrate 15 ; in particular, it extends from the top surface 15A of the substrate 15 up to the first front surface 3A.

[0132] The fact that the second junction region 61 is in contact with the substrate 15 allows the second junction region 61 to be used to bias the substrate 15 when in use.

[0133] The second junction region 61 has the same conductivity type as the substrate 15 .

[0134] Depending on the specific application, the second junction region 61 may have a uniform or variable doping level parallel to the third axis Z. For example, the second junction region 61 may have a doping level between 1·10 15 Atom / cm 3 and 5.10 18 Atom / cm 3 between the doping levels.

[0135] The contents described with reference to the first HEMT 5A also apply mutatis mutandis to the second HEMT 5B integrated in the active region 7B. Figure 2 In the embodiment of FIG. 5 , the second HEMT 5B has the same structure as that of the first HEMT 5A. Therefore, the same elements of the second HEMT 5B as those of the first HEMT 5A are designated by the same reference numerals but increased by 50, and are not described in detail.

[0136] In practice, the second HEMT 5B includes a main structure 70 and an epitaxial multilayer 71 .

[0137] In the second HEMT 5B, the body structure 70 also includes a doped region having a conductivity type different from that of the substrate 15 .

[0138] In detail, the main body structure 70 includes a first epitaxial region 75 , a second epitaxial region 76 , a third epitaxial region 77 , a fourth epitaxial region 78 (having a respective central portion 78A and a respective peripheral portion 78B), and a fifth epitaxial region 79 .

[0139] However, depending on the specific application, the size, shape, doping type, and doping level of the epitaxial regions 75 - 79 of the second HEMT 5B may be the same as or different from the epitaxial regions 25 - 29 of the first HEMT 5A.

[0140] The epitaxial multilayer 71 comprises a heterostructure 72 which accommodates a two-dimensional gas of charge carriers, in particular electrons, on which the operation of the second HEMT 5B is based, ie the heterostructure forms a conducting channel of the second HEMT 5B.

[0141] The heterostructure 72 includes a channel layer 85 and a barrier layer 86 .

[0142] The epitaxial multilayer 71 further includes a transition region 82 .

[0143] Depending on the specific application, the shape, size, number of layers, and material of the epitaxial multilayer 71 of the second HEMT 5B may be the same as or different from the shape, size, number of layers, and material of the epitaxial multilayer 21 of the second HEMT 5A.

[0144] The second HEMT 5B further includes a source region 90 , a drain region 91 , and a gate structure formed by a channel-modulation region 93 and a gate-contact region 94 .

[0145] The device 1 further comprises a separation region 100 extending in the die 3 within the active area 7B and comprising a definition region 102 and a polycrystalline region 103. The polycrystalline region 103 has an outer sidewall 105 and an inner sidewall 106.

[0146] The device may also include conductive and / or insulating regions extending in the active area 7B, wherein Figure 2 Only one insulating region 108 is illustrated as an example.

[0147] What has been described for the insulating structure 8 of the first HEMT 5A also applies mutatis mutandis to the insulating structure 9 of the second HEMT 5B. In detail, the insulating structure 9 is also of a junction type and comprises a first junction region 110 and a second insulating region 111 .

[0148] exist Figure 2 In the embodiment of FIG. 5 , the second junction region 111 forms a single region with the second junction region 61 on the side facing the first transistor 5A. Therefore, for the sake of clarity, Figure 2 The second junction regions 61 and 111 are separated by a dotted line.

[0149] In practice, with reference to the first HEMT 5A, the first epitaxial region 25 and the third epitaxial region 27 are buried regions of the host structure 20 , which extend parallel to the third axis Z between the heterostructure 22 and the substrate 15 .

[0150] The fact that the first epitaxial region 25 has a conductivity type different from that of the substrate 15 causes a PN junction to be formed at the top surface 15A of the substrate 15 .

[0151] Thus, in use, the heterostructure 22 may be electrically isolated from the substrate 15 by appropriately biasing the first epitaxial region 25 and the substrate 15 .

[0152] In other words, in use, the substrate 15 may be prevented from acting as an undesired conductive path between the heterostructure 22 and further electronic components integrated in the die 3 (eg, the second HEMT 5B or electronic components based on the single semiconductor material 10 ).

[0153] In practice, in use, the electrical performance of the first HEMT 5A can be prevented from being dependent on the bias voltage of the substrate 15 .

[0154] In addition, the presence of the insulating structure 8 can also electrically insulate the first HEMT 5A laterally (parallel to the first and second axes X, Y) from other electronic components integrated in the die 3. In practice, the insulating structure 8 helps to improve the electrical insulation between the main structure 20 of the first HEMT 5A and adjacent devices.

[0155] Therefore, it is possible to prevent the electrical performance of the first HEMT 5A from being dependent on the operating voltage applied to other electronic components integrated in the die 3 outside the active region 7A in use.

[0156] At the same time, both the substrate 15 and the main structure 20 are made of semiconductor material, here single crystal silicon, especially having <111> The fact of being made of oriented single-crystal silicon allows obtaining a good crystal quality of the heterostructure 22 .

[0157] The contents described with respect to the electrical insulation of the body structure 20 of the first HEMT 5A also apply to the electrical insulation of the body structure 70 of the second HEMT 5B.

[0158] Thus, the body structures 20, 70 of the first and second HEMTs 5A, 5B may be biased independently of each other in use.

[0159] In practice, in device 1, multiple electronic components based on heterogeneous structures can be integrated in the same tube core, while ensuring the electrical decoupling of the corresponding main structures, which has advantages in area occupancy, electrical performance and design flexibility compared to the solution of integrating electronic components in different tube cores.

[0160] For example, according to one embodiment, the device 1 may include a conductive region, Figure 2 , so as to electrically couple the first and second HEMTs 5A, 5B in a source-follower configuration (e.g. Figure 3 ) as shown in the electrical equivalent diagram.

[0161] exist Figure 2 and Figure 3 In the embodiment, the first HEMT 5A is a low-side switch whose source terminal S is coupled to ground, and the second HEMT 5B is a high-side switch whose drain terminal D is coupled to an operating voltage V cc (For example, approximately 48 V.) The source terminal S of the second HEMT 5B and the drain terminal D of the first HEMT 5A are coupled together and form an output terminal OUT of the source-follower circuit.

[0162] As discussed above, the body structures 20, 70 of the first and second HEMTs 5A, 5B may be electrically decoupled from each other and thereby independently biased.

[0163] In the example shown, both the body structure 20 of the first HEMT 5A and the body structure 70 of the second HEMT 5B are electrically connected to the respective source regions 40 , 90 .

[0164] The substrate 15 may be connected to ground.

[0165] The possibility of keeping the body structures 20, 70 decoupled from each other allows maintaining the bias voltage of the body structures 20, 70 stable. Therefore, both the first and second HEMTs 5A, 5B can have a stable on-state resistance without being affected by the potential difference applied between the high voltage connection terminal of the assembly and the substrate potential. Therefore, the device 1 can have high reliability in use even when the first and second HEMTs 5A, 5B are used in a source-follower type configuration.

[0166] Reference below Figure 4A-4H Described is a sequence of manufacturing steps that can be used to produce a semiconductor electronic device 1 .

[0167] In detail, for simplicity and without loss of generality, Figure 4A-4H Only the manufacturing steps concerning a portion of the active area 7A in which the first HEMT 5A is integrated are shown.

[0168] Figure 4A 1 is a cross section of a wafer 150 of single crystalline semiconductor material, particularly silicon, the wafer 150 having a top surface 150A.

[0169] The wafer 150 comprises a substrate 15 on which four epitaxial layers 151, 152, 153, 154 have been grown, which are intended to at least partially form a first epitaxial region 25, a second epitaxial region 26, a third epitaxial region 27 and a fourth epitaxial region 28 (in Figure 4A Indicated in brackets for simplicity).

[0170] The fourth epitaxial layer 154 forms the top surface 150A of the wafer 150 .

[0171] The fourth epitaxial layer 154 includes a first portion 154A intended to form a peripheral portion 28B of the fourth epitaxial region 28 and a second portion 154B intended to form a central portion 28A of the fourth epitaxial region 28 .

[0172] Next( Figure 4B ), a limiting layer 156, such as an oxide layer, in particular a silicon oxide layer, is formed on the top surface 150A.

[0173] The definition layer 156 may have a small thickness along the third axis Z, for example between 7 nm and 300 nm, in particular and between.

[0174] The limiting layer 156 is intended to form a limiting region 52 ( Figure 2 ).

[0175] The defining layer 156 may be formed by oxidation of a surface portion of the fourth epitaxial layer 154 or by deposition on the top surface 150A. Figure 4A The thickness of the fourth epitaxial layer 154 may be reduced after oxidation compared to the thickness of the layer 28 represented in FIG. However, given that the thickness of the confinement layer 156 is much smaller than the thickness of the fourth epitaxial layer 154, for simplicity, it can be assumed that the thickness of the fourth epitaxial layer 154 will remain the same before and after oxidation to a first approximation.

[0176] Then( Figure 4C ), in the first portion 154A of the fourth epitaxial layer 154 (where a Figure 2 The limiting layer 156 is removed from the fifth epitaxial region 29 of the embodiment of the present invention. Therefore, a portion of the limiting layer 156 is left, which is also referred to as the growth mask 157 below.

[0177] In practice, the growth mask 157 exposes the first portion 154A of the fourth epitaxial layer 154 and covers the second portion 154B of the fourth epitaxial layer 154 .

[0178] exist Figure 4DIn the process, a surface layer 160 of semiconductor material is grown on the wafer 150, in particular of the same material as the fourth epitaxial layer 154 (here silicon).

[0179] The surface layer 160 has a top surface 160A (intended to form Figure 2 first front surface 3A).

[0180] The surface layer 160 includes an epitaxial portion 161 grown in parallel with the third axis Z from the fourth epitaxial layer 154 and a sacrificial portion 162 grown in parallel with the third axis Z on the growth mask 157 .

[0181] The epitaxial portion 161 grown from the single crystal substrate maintains the single crystal structure of the fourth epitaxial layer 154 and is intended to form the fifth epitaxial region 29 ( Figure 2 ).

[0182] The sacrificial portion 162 grown from the amorphous substrate has a polycrystalline structure.

[0183] In the wafer 150, a surface layer 160 is now also included, which can also be formed in a manner not shown here and known per se. Figure 2 Insulation structure 8.

[0184] exist Figure 4E In the embodiment of the present invention, an etching mask 163 is formed on the surface layer 160. The etching mask 163 may be formed of one layer or more layers.

[0185] The etch mask 163 forms an opening 166 that at least partially exposes the sacrificial portion 162 .

[0186] Furthermore, before forming the etching mask 163, an insulating layer 165 may be formed in the surface layer 160, for example, by forming an insulating trench, such as a shallow trench isolation (STI). The insulating layer 165 may be intended to form Figure 2 The insulating area 58.

[0187] Next ( Figure 4F ), the insulating layer 165, the sacrificial portion 162 and the growth mask 157 are removed at the opening 166 using the etching mask 163.

[0188] Regarding the sacrificial portion 162, there still exists a portion arranged under the etching mask 163, which will form Figure 2 The polycrystalline region 53 is still designated by 53 .

[0189] With regard to the growth mask 157, there is therefore still a portion arranged below the polycrystalline region 53, which portion is Figure 2 The defined area 52 corresponds to and is therefore designated by the same reference numerals.

[0190] In practice, Figure 4FAfter the etching, the recesses formed in the sacrificial portion 162 and in the growth mask 157 expose a portion of the lower layer portion 154B of the fourth epitaxial layer 154 .

[0191] The etching of the growth mask 157 and the sacrificial portion 162 may be performed using two different etching chemistries. Thus, the growth mask 157 may be etched using a selective chemistry that, in a first approximation, does not etch the fourth epitaxial layer 154. Thus, the fourth epitaxial layer may maintain good surface crystal quality.

[0192] Then( Figure 4G ), grown on the wafer 150 to form Figure 2 The working multilayer 169 of the epitaxial multilayer 21.

[0193] In detail, the working multilayer 169 includes a first buffer layer 170 , such as AlN, extending directly on the exposed portion of the second portion 154B of the fourth epitaxial layer 154 , and a second buffer layer 171 , such as AlGaN, grown on the first buffer layer 170 .

[0194] The first and second buffer layers 170, 171 will form the transition region 32 ( Figure 2 ).

[0195] A channel layer 35 and a barrier layer 36 are further grown on the second buffer layer 171 .

[0196] In the illustrated embodiment, working multilayer 169 is also conformally grown on inner sidewalls 56 of polycrystalline region 53 and on etch mask 163 .

[0197] In practice, the working multilayer 169 includes a raised portion 174 extending on the etching mask 163 and on the inner sidewall 56 , and a useful portion 175 extending directly on the fourth epitaxial layer 154 .

[0198] The useful portion 175 has a substantially flat top surface, in particular substantially parallel to the surface 150A of the wafer 150, and will form the second front surface 30 ( Figure 2 ) and are therefore designated by the same reference numerals.

[0199] Still refer to Figure 4G A channel-modulation region 43 is formed on the top surface 30 of the useful portion 175 in a manner known per se, for example via growth and definition of specific layers.

[0200] In practice, in this embodiment, the useful portion 175 of the working multilayer 169 also includes the channel-modulation region 43 .

[0201] Next( Figure 4H), removing raised portions 174 of working multilayer 169 above etch mask 163, for example via planarization, such as chemical mechanical polishing (CMP) or other etching techniques.

[0202] One or more insulating layers (not shown here) may be formed on the top surface 30 to protect the channel-modulation region 43 .

[0203] In the illustrated embodiment, after the raised portion 174 is removed, only the portion extending on the inner sidewall 56 remains, which portion will form the peripheral portion 178 of the epitaxial multilayer 21 .

[0204] However, as referenced Figure 2 As depicted, the shape of the peripheral portion 178 of the epitaxial multilayer 21 may differ from that shown. For example, a further etching step may be performed to at least partially remove the peripheral portion 178.

[0205] Next, in a manner not shown here, the etching mask 163 is at least partially removed.

[0206] Furthermore, further production steps follow, which are known per se and are not illustrated, for forming the surface structure (metal contact regions and passivation and insulation regions) of the first HEMT 5A.

[0207] This is followed by final manufacturing steps (not shown here), such as forming the top layers of metal interconnects and dicing of the wafer 150 , which results in the formation of the device 1 .

[0208] It will be clear to those skilled in the art that reference Figure 4A-4H The described contents can also be applied to manufacturing the second HEMT 5B.

[0209] It will also be clear to those skilled in the art that the silicon electronic component 10 may be formed in a particular epitaxial layer grown on the substrate 15 in the wafer 150 .

[0210] use <111> The possibility of using a silicon substrate 15 as a starting substrate for forming a semiconductor electronic device 1 can allow obtaining a high epitaxial quality of the heterostructure 22, in particular when the channel layer 35 is made of GaN. As a result, electronic components based on the heterostructure 5 can have excellent electrical properties. The applicant has also found that using <111> The silicon substrate 15 also allows obtaining excellent electrical performance of any silicon-based electronic components 10 integrated in the die 3 .

[0211] Finally, it is clear that other modifications and variations may be made to the electronic device 1 and to the corresponding manufacturing process described and illustrated herein, without departing from the scope of the present disclosure.

[0212] Apart from Figure 1In addition to or in place of the components shown in Figure 1 In addition to the components shown in , the device 1 may also include other silicon-based electronic components 10 integrated in the die 3. For example, the components 10 may include MOS transistors for applications at low voltages, such as less than 15V, or medium voltages, such as 15V to 20V; DMOS transistors and / or drift MOS transistors, such as for applications with operating voltages from 20V to 200V; thin film resistors; OTP or MTP memories; phase change memories; and the like.

[0213] For example, the conductivity type of the individual semiconductor regions, N or P, may be reversed compared to what has been described.

[0214] For example, the substrate 15 may be formed of a substrate having a resistivity between 0.002 Ω·cm and 0.1 Ω·cm on which an epitaxial layer having a thickness between 1 μm and 40 μm and a resistivity between 0.1 Ω·cm and 20 Ω·cm is grown.

[0215] For example, the epitaxial multilayer 21, 71 may not include the respective transition region 32, 82. In other words, the heterostructure 21, 71 may be grown directly on the respective host structure 20, 70. Additionally or alternatively, the heterostructure 22, 72 may include further layers, such as layers of semiconductor or insulating material, depending on the specific application and the specific manufacturing steps used for growth.

[0216] For example, the device 1 may include components based on heterostructures other than HEMTs.

[0217] For example, the first HEMT 5A and / or the second HEMT 5B may be of a normally-off type, and wherein the gate structure may be different from that described above; for example, the gate structure may be of a recessed type, and / or the fabrication of the gate structure may include the use of a fluorine plasma under the gate structure. Alternatively, the first HEMT 5A and / or the second HEMT 5B may be of a normally-on type, i.e., a depletion type.

[0218] For example, the number of epitaxial regions forming body structures 20 and / or 70 may vary depending on the specific application.

[0219] For example, referring to the first (or second) HEMT 5A (or 5B), the fourth epitaxial region 28 (or 78) may not exist, and the epitaxial multilayer 21 (or 71) may be grown directly on the third epitaxial region 27 (or 77), which may be advantageous in reducing manufacturing costs.

[0220] In the case of medium or low voltage applications (e.g. up to approximately 20 V), the body structure 20 and / or 70 may only include the respective first epitaxial region 25, 75. In practice, in this case, the epitaxial multilayer 21 and / or 71 may be grown directly on the respective first epitaxial region 25, 75.

[0221] For example, depending on the specific application, one or more silicon-based electronic components 10 may be integrated in the active regions 7A and / or 7B. In this case, the silicon-based electronic components 10 may be integrated in the epitaxial region connected to the fifth epitaxial region 29. Figure 4D , one or more silicon-based electronic components 10 may be integrated in the epitaxial portion 161 of the surface layer 160 .

[0222] For example, the electronic component 10 may be an electronic component based on a single semiconductor material other than silicon, such as Ge, SiGe, etc.

[0223] For example, referring to the use of the first and second HEMTs 5A, 5B in a source-follower configuration, the body structure 70 of the second HEMT 5B may be coupled to an operating voltage V cc Rather than being coupled to the corresponding source region 90 (as by Figure 3 denoted by the dotted line in ).

[0224] For example, still refer to Figure 3 , the first HEMT 5A may be used as a high-side switch, and the second HEMT 5B may be used as a low-side switch.

[0225] For example, according to one embodiment, the first junction region 60 and the first epitaxial region 25 may be electrically connected to the drain terminal D of the first HEMT 5A instead of being electrically connected to the source terminal S of the first HEMT 5A; and / or the first junction region 110 and the first epitaxial region 75 may be electrically connected to the drain terminal D of the second transistor 5B instead of being electrically connected to the source terminal S of the second transistor 5B. In this way, in use, the regions 75 and 110 may be biased at any potential different from the potential applied to the region 25, and in particular, at any potential higher than the potential applied to the region 25.

[0226] For example, depending on the specific process and the machine used, refer to Figure 4A-4H The described manufacturing steps and their respective execution order may differ from what has been illustrated and discussed.

[0227] For example, depending on the specific growth parameters used, the growth of the epitaxial multilayer 21, 71 can be similar to that of reference Figure 4G Different from what is described. Figure 2 and Figure 4GAs described, the shape of the peripheral portion of the epitaxial multilayer 21, 71 may be different from that shown.

[0228] For example, the multilayer 169 may be selectively grown starting from only the exposed portion 154B of the fourth epitaxial layer 154. In this case, the raised portion 174 will not exist; therefore, Figure 4H The removal indicated in may not exist.

[0229] For example, the described embodiments may be combined together to provide further solutions.

[0230] A semiconductor electronic device (1) is summarized as comprising: a tube core (3), comprising a substrate (15) of a semiconductor material having a first conductivity type (P); and a first electronic component (5A, 5B) based on a heterostructure, comprising a main structure (20, 70) of semiconductor material extending on the substrate (15) in the tube core and an epitaxial multilayer (21, 71) extending in contact with the main structure and comprising a heterostructure (22, 72), wherein the main structure of the first electronic component includes a first doped region (25, 27, 75, 77) of semiconductor material extending between the heterostructure and the substrate and having a second conductivity type (N) different from the first conductivity type.

[0231] The first doped region (25, 27, 75, 77) extends in contact with the substrate.

[0232] The main structure (20, 70) also includes a second doped region (27, 77) having a second conductivity type (N) and extending between the heterostructure and the substrate (15) at a distance from the first doped region (25, 75).

[0233] The main structure (20, 70) comprises a third doped region (28, 78) having a second conductivity type (N) and a doping level lower than that of the first doped region (25, 27, 75, 77), and the epitaxial multilayer (21, 71) extends on the third doped region.

[0234] The electronic device also includes an insulating structure (8, 9) extending in the die (3) and at least partially surrounding the main structure (20, 70) of the first electronic component (5A, 5B).

[0235] The insulating structure is a junction insulating structure or a deep trench insulating structure.

[0236] The main structure (20, 70) is delimited below by a first doped region (25, 75) towards the substrate (15) and laterally by an insulating structure.

[0237] The electronic device also includes a separation region (50, 100), which extends in the chip and at least partially surrounds the epitaxial multilayer (21) and is arranged between the epitaxial multilayer and the main structure (20, 70), in particular in contact with the epitaxial multilayer and the main structure, and the separation region includes a region (53, 103) of polycrystalline type semiconductor material.

[0238] The electronic device also includes a second electronic component (5B) based on a heterostructure, the second electronic component including a corresponding main structure (70) of a semiconductor material extending on a substrate (15) in a chip and a corresponding epitaxial multilayer (71) extending in contact with the main structure of the second electronic component and including a corresponding heterostructure (72), the main structure (20) of the first electronic component (5A) being different from the main structure (70) of the second electronic component (5B), and the epitaxial multilayer (21) of the first electronic component extending at a certain distance from the epitaxial multilayer (71) of the second electronic component, wherein the main structure of the second electronic component includes a first doped region (75, 77) of a semiconductor material of a second conductivity type (N) extending between the corresponding heterostructure (72) and the substrate.

[0239] The first and second electronic components are HEMTs coupled together to form a source-follower type circuit.

[0240] The electronic device further comprises a third electronic component (10) based on a single semiconductor material, such as silicon, and integrated in the die (3).

[0241] A process for manufacturing an electronic device (1) is summarized as comprising: providing a wafer (150) comprising a substrate (15) of a semiconductor material having a first conductivity type (P); and forming a first electronic component (5A, 5B) based on a heterostructure on the wafer, wherein forming the first electronic component comprises: forming a main structure (20, 70) of the semiconductor material on the substrate (15); and forming an epitaxial multilayer (21, 71) in contact with the main structure and comprising a heterostructure (21, 71), wherein the main structure comprises a first doped region (25, 27, 75, 77) of a semiconductor material having a second conductivity type (N) different from the first conductivity type and extending between the heterostructure and the substrate.

[0242] The substrate is made of silicon and has a top surface (15A), for example wherein the top surface is shaped according to a crystal orientation. <111> The substrate is oriented and a main structure (20, 70) is formed via epitaxial growth of one or more layers on a top surface of the substrate.

[0243] Forming an epitaxial multilayer (21) includes: forming a growth mask (157) on an epitaxial layer (154) grown on a substrate (15), the growth mask comprising an oxide; forming an opening in the growth mask to expose a central portion (154B) of the epitaxial layer; and growing the epitaxial multilayer (21, 169) on the exposed portion of the epitaxial layer.

[0244] Forming a growth mask includes: forming a mask layer (156) on the epitaxial layer; removing part of the mask layer to expose the peripheral part (154A) of the epitaxial layer; and growing a surface layer (160) of the same material as the epitaxial layer on the epitaxial layer (154), the surface layer having a first part (161) extending on the peripheral part (154A) of the epitaxial layer (154) and a second part (162) extending on the growth mask (157), wherein forming an opening in the growth mask (157) also includes forming a recess extending to the growth mask through the second part (162) of the surface layer.

[0245] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications, and publications to provide yet further embodiments.

[0246] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. An electronic device, comprising: a die including a substrate having a semiconductor material of a first conductivity type; a first electronic component comprising a main structure of said semiconductor material extending on said substrate and an epitaxial multilayer extending in contact with said main structure and comprising a heterostructure; as well as a separation region extending in the die and surrounding the epitaxial multilayer and between the epitaxial multilayer and the main structure, The main structure of the first electronic component includes a first doped region extending between the heterostructure and the substrate and having a semiconductor material of a second conductivity type different from the first conductivity type.

2. The electronic device according to claim 1, wherein: The first doped region extends in contact with the substrate.

3. The electronic device according to claim 1, wherein: The body structure also includes a second doped region having the second conductivity type and extending between the heterostructure and the substrate, the second doped region being separated from the first doped region by a first distance.

4. The electronic device according to claim 1, wherein: The main structure includes a third doped region having the second conductivity type and a doping level lower than a doping level of the first doped region, and the epitaxial multilayer extends on the third doped region. 5 . The electronic device of claim 1 , further comprising an insulating structure extending within the die and surrounding a main structure of the first electronic component.

6. The electronic device according to claim 5, wherein: The insulating structure is a junction insulating structure.

7. The electronic device according to claim 5, wherein: The main structure is bounded below toward the substrate by the first doped region and laterally by the insulating structure.

8. The electronic device according to claim 1, wherein: The separation region comprises a region of semiconductor material of the polycrystalline type.

9. The electronic device according to claim 1 , further comprising a second electronic component comprising a respective main structure of the semiconductor material extending on the substrate in the die and a respective epitaxial multilayer extending in contact with the main structure of the second electronic component and comprising a respective heterostructure, The main structure of the first electronic component is different from the main structure of the second electronic component, and the epitaxial multilayer of the first electronic component is separated from the epitaxial multilayer of the second electronic component, in, The main structure of the second electronic component includes a first doped region extending between the corresponding heterostructure and the substrate and having a semiconductor material of the second conductivity type.

10. The electronic device according to claim 9, wherein: The first electronic component and the second electronic component are HEMTs coupled together to form a source-follower type circuit.

11. The electronic device of claim 1 further comprising a third electronic component located on a single semiconductor material and integrated into the die.

12. A process for manufacturing an electronic device, comprising: forming a first electronic component on a wafer including a substrate having a semiconductor material of a first conductivity type, Wherein, forming the first electronic component comprises: forming a main structure of semiconductor material on the substrate; and forming an epitaxial multilayer having a first surface coupled to the main structure and a second surface transverse to the first surface; and forming a defined area on the main structure and coupled to the second surface of the epitaxial multilayer, The main structure includes a first doped region extending between the heterostructure and the substrate and having a semiconductor material of a second conductivity type different from the first conductivity type.

13. The manufacturing process of claim 12, wherein: The substrate includes silicon and has a top surface, and the body structure is formed via epitaxial growth on the top surface of the substrate.

14. The manufacturing process of claim 12, wherein: Forming the epitaxial multilayer comprises: forming a growth mask on the epitaxial layer grown on the substrate, wherein the growth mask comprises an oxide; forming an opening in the growth mask to expose a central portion of the epitaxial layer; and The epitaxial multilayer is grown on an exposed central portion of the epitaxial layer.

15. The manufacturing process of claim 14, wherein: Forming the growth mask comprises: forming a mask layer on the epitaxial layer; removing a portion of the mask layer to expose a peripheral portion of the epitaxial layer; and growing a surface layer of the same material as the epitaxial layer on the epitaxial layer, the surface layer having a first portion extending on a peripheral portion of the epitaxial layer and a second portion extending on the growth mask, Wherein, forming an opening in the growth mask further comprises forming a recess extending to the growth mask through the second portion of the surface layer.

16. A device comprising: substrate; The main structure on the substrate comprises: an epitaxial multilayer having a first face extending along a first direction and a second plurality of faces extending along a second direction transverse to the first direction; and A first doped region having a first conductivity type; a second doped region, located between the first doped region and the epitaxial multilayer, the second doped region having a second conductivity type different from the first conductivity type; A third doped region, having the first conductivity type, surrounds the second plurality of faces of the epitaxial multilayer.

17. The device according to claim 16, wherein: The epitaxial multilayer has a first width along the first direction, and the first width is smaller than a first width of the first doping region along the first direction.

18. The apparatus according to claim 16, wherein: The second doped region includes a first portion extending along the second direction and includes a first surface coplanar with a first surface of a first face of the epitaxial multilayer.

19. The apparatus of claim 16, further comprising a buffer layer between the epitaxial multilayer and the second doped region.

20. The apparatus of claim 16, further comprising a separation region between the third doped region and the second plurality of faces of the epitaxial multilayer, the separation region comprising: a silicon oxide defining region coupled to the second doped region; as well as A polycrystalline region is directly coupled to the second plurality of facets of the epitaxial multilayer.

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